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Get improvements from FreeBSD-current (January 2011).

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Successfully tested with WEP, WPA and WPA2 on AR9285.
Reviewed by jmcneill@
This commit is contained in:
cegger 2011-03-07 11:25:41 +00:00
parent 5c3ccd6eba
commit f2fbc0de6d
43 changed files with 622 additions and 240 deletions
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10
sys/dev/ic/ath.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ath.c,v 1.110 2011/02/20 03:55:56 jmcneill Exp $ */
/* $NetBSD: ath.c,v 1.111 2011/03/07 11:25:41 cegger Exp $ */
/*-
* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
@ -41,7 +41,7 @@
__FBSDID("$FreeBSD: src/sys/dev/ath/if_ath.c,v 1.104 2005/09/16 10:09:23 ru Exp $");
#endif
#ifdef __NetBSD__
__KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.110 2011/02/20 03:55:56 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: ath.c,v 1.111 2011/03/07 11:25:41 cegger Exp $");
#endif
/*
@ -468,7 +468,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
*/
sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
if (sc->sc_softled) {
ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
HAL_GPIO_MUX_MAC_NETWORK_LED);
ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
}
@ -723,7 +724,8 @@ ath_resume(struct ath_softc *sc)
ath_hal_resettxqueue(ah, i);
if (sc->sc_softled) {
ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
HAL_GPIO_MUX_MAC_NETWORK_LED);
ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
}
return true;

7
sys/dev/ic/ath_netbsd.c
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@ -1,4 +1,4 @@
/* $NetBSD: ath_netbsd.c,v 1.19 2011/02/20 03:55:56 jmcneill Exp $ */
/* $NetBSD: ath_netbsd.c,v 1.20 2011/03/07 11:25:41 cegger Exp $ */
/*-
* Copyright (c) 2003, 2004 David Young
@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ath_netbsd.c,v 1.19 2011/02/20 03:55:56 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: ath_netbsd.c,v 1.20 2011/03/07 11:25:41 cegger Exp $");
#include <sys/param.h>
#include <sys/types.h>
@ -183,7 +183,8 @@ ath_sysctl_softled(SYSCTLFN_ARGS)
if (softled != sc->sc_softled) {
if (softled) {
/* NB: handle any sc_ledpin change */
ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
HAL_GPIO_MUX_MAC_NETWORK_LED);
ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
!sc->sc_ledon);
}

6
sys/dev/ic/athvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: athvar.h,v 1.33 2010/03/19 01:32:30 dyoung Exp $ */
/* $NetBSD: athvar.h,v 1.34 2011/03/07 11:25:41 cegger Exp $ */
/*-
* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
@ -571,8 +571,8 @@ extern int ath_txbuf;
#define ath_hal_gettxintrtxqs(_ah, _txqs) \
((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
#define ath_hal_gpioCfgOutput(_ah, _gpio) \
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
#define ath_hal_gpioset(_ah, _gpio, _b) \
((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))

7
sys/external/isc/atheros_hal/dist/ah.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah.c,v 1.2 2008/12/11 05:30:29 alc Exp $
* $Id: ah.c,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -525,6 +525,11 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
*result = pCap->halTstampPrecision;
return HAL_OK;
case HAL_CAP_INTRMASK: /* mask of supported interrupts */
*result = pCap->halIntrMask;
return HAL_OK;
case HAL_CAP_BSSIDMATCH: /* hardware has disable bssid match */
return pCap->halBssidMatchSupport ? HAL_OK : HAL_ENOTSUPP;
default:
return HAL_EINVAL;
}

34
sys/external/isc/atheros_hal/dist/ah.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah.h,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ah.h,v 1.4 2011/03/07 11:25:42 cegger Exp $
*/
#ifndef _ATH_AH_H_
@ -63,6 +63,8 @@ typedef enum {
HAL_ENOTSUPP = 13, /* Hardware revision not supported */
HAL_ESELFTEST = 14, /* Hardware self-test failed */
HAL_EINPROGRESS = 15, /* Operation incomplete */
HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
HAL_EEBADCC = 17, /* EEPROM invalid country code */
} HAL_STATUS;
typedef enum {
@ -107,6 +109,8 @@ typedef enum {
HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
HAL_CAP_BB_HANG = 35, /* can baseband hang */
HAL_CAP_MAC_HANG = 36, /* can MAC hang */
HAL_CAP_INTRMASK = 37, /* bitmask of supported interupts */
HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */
} HAL_CAPABILITY_TYPE;
/*
@ -293,6 +297,7 @@ typedef enum {
HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */
} HAL_RX_FILTER;
typedef enum {
@ -319,19 +324,21 @@ typedef enum {
HAL_INT_RXORN = 0x00000020,
HAL_INT_TX = 0x00000040, /* Non-common mapping */
HAL_INT_TXDESC = 0x00000080,
HAL_INT_TIM_TIMER=0x00000100,
HAL_INT_TXURN = 0x00000800,
HAL_INT_MIB = 0x00001000,
HAL_INT_RXPHY = 0x00004000,
HAL_INT_RXKCM = 0x00008000,
HAL_INT_SWBA = 0x00010000,
HAL_INT_BMISS = 0x00040000,
HAL_INT_BNR = 0x00100000, /* Non-common mapping */
HAL_INT_BNR = 0x00100000,
HAL_INT_TIM = 0x00200000, /* Non-common mapping */
HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
HAL_INT_GPIO = 0x01000000,
HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
HAL_INT_CST = 0x10000000, /* Non-common mapping */
HAL_INT_GTT = 0x20000000, /* Non-common mapping */
HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
@ -339,7 +346,8 @@ typedef enum {
HAL_INT_BMISC = HAL_INT_TIM
| HAL_INT_DTIM
| HAL_INT_DTIMSYNC
| HAL_INT_CABEND,
| HAL_INT_CABEND
| HAL_INT_TBTT,
/* Interrupt bits that map directly to ISR/IMR bits */
HAL_INT_COMMON = HAL_INT_RXNOFRM
@ -353,9 +361,26 @@ typedef enum {
| HAL_INT_RXKCM
| HAL_INT_SWBA
| HAL_INT_BMISS
| HAL_INT_BNR
| HAL_INT_GPIO,
} HAL_INT;
typedef enum {
HAL_GPIO_MUX_OUTPUT = 0,
HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
HAL_GPIO_MUX_PCIE_POWER_LED = 2,
HAL_GPIO_MUX_TX_FRAME = 3,
HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
HAL_GPIO_MUX_MAC_POWER_LED = 6
} HAL_GPIO_MUX_TYPE;
typedef enum {
HAL_GPIO_INTR_LOW = 0,
HAL_GPIO_INTR_HIGH = 1,
HAL_GPIO_INTR_DISABLE = 2
} HAL_GPIO_INTR_TYPE;
typedef enum {
HAL_RFGAIN_INACTIVE = 0,
HAL_RFGAIN_READ_REQUESTED = 1,
@ -764,7 +789,8 @@ struct ath_hal {
void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
const uint8_t *bssid, uint16_t assocId);
HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
uint32_t gpio, HAL_GPIO_MUX_TYPE);
HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,

21
sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c vendored
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@ -14,9 +14,8 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah_eeprom_v14.c,v 1.4 2008/12/31 14:08:46 christos Exp $
* $Id: ah_eeprom_v14.c,v 1.5 2011/03/07 11:25:42 cegger Exp $
*/
#include <sys/endian.h>
#include "opt_ah.h"
#include "ah.h"
@ -54,8 +53,8 @@ v14EepromGet(struct ath_hal *ah, int param, void *val)
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
__func__, ath_hal_ether_sprintf(macaddr));
return HAL_EEBADMAC;
} else
return HAL_OK;
}
return HAL_OK;
case AR_EEP_REGDMN_0:
return pBase->regDmn[0];
case AR_EEP_REGDMN_1:
@ -161,20 +160,6 @@ v14EepromDiag(struct ath_hal *ah, int request,
return AH_FALSE;
}
#if 0
/* XXX conditionalize by target byte order */
#ifndef bswap16
static __inline__ uint16_t
__bswap16(uint16_t _x)
{
return ((uint16_t)(
(((const uint8_t *)(&_x))[0] ) |
(((const uint8_t *)(&_x))[1]<< 8))
);
}
#endif
#endif
/* Do structure specific swaps if Eeprom format is non native to host */
static void
eepromSwap(struct ar5416eeprom *ee)

4
sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah_eeprom_v3.c,v 1.2 2008/12/11 05:30:29 alc Exp $
* $Id: ah_eeprom_v3.c,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -1759,7 +1759,7 @@ legacyEepromDetach(struct ath_hal *ah)
HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
if (ee->ee_version >= AR_EEPROM_VER4_0 && ee->ee_eepMap == 1)
return freeEepromRawPowerCalInfo5112(ah, ee);
freeEepromRawPowerCalInfo5112(ah, ee);
ath_hal_free(ee);
AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
}

24
sys/external/isc/atheros_hal/dist/ah_internal.h vendored
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@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ah_internal.h,v 1.5 2011/02/20 11:21:02 jmcneill Exp $
* $Id: ah_internal.h,v 1.6 2011/03/07 11:25:42 cegger Exp $
*/
#ifndef _ATH_AH_INTERAL_H_
#define _ATH_AH_INTERAL_H_
@ -57,6 +57,11 @@ typedef struct {
uint16_t end; /* ending register or zero */
} HAL_REGRANGE;
typedef struct {
uint32_t addr; /* register address/offset */
uint32_t value; /* value to write */
} HAL_REGWRITE;
/*
* Transmit power scale factor.
*
@ -87,12 +92,12 @@ struct ath_hal_chip {
};
#ifndef AH_CHIP
#define AH_CHIP(_name, _probe, _attach) \
static struct ath_hal_chip name##_chip = { \
static struct ath_hal_chip _name##_chip = { \
.name = #_name, \
.probe = _probe, \
.attach = _attach \
}; \
OS_DATA_SET(ah_chips, name##_chip)
OS_DATA_SET(ah_chips, _name##_chip)
#endif
/*
@ -184,7 +189,8 @@ typedef struct {
halExtChanDfsSupport : 1,
halForcePpmSupport : 1,
halEnhancedPmSupport : 1,
halMbssidAggrSupport : 1;
halMbssidAggrSupport : 1,
halBssidMatchSupport : 1;
uint32_t halWirelessModes;
uint16_t halTotalQueues;
uint16_t halKeyCacheSize;
@ -197,6 +203,7 @@ typedef struct {
uint8_t halNumGpioPins;
uint8_t halNumAntCfg2GHz;
uint8_t halNumAntCfg5GHz;
uint32_t halIntrMask;
} HAL_CAPABILITIES;
/*
@ -231,7 +238,8 @@ struct ath_hal_private {
uint16_t *data);
HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
uint16_t data);
HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *,
uint32_t gpio, HAL_GPIO_MUX_TYPE);
HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
HAL_BOOL (*ah_gpioSet)(struct ath_hal *,
@ -308,8 +316,8 @@ struct ath_hal_private {
AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
#define ath_hal_eepromWrite(_ah, _off, _data) \
AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
#define ath_hal_gpioCfgOutput(_ah, _gpio) \
AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
#define ath_hal_gpioCfgInput(_ah, _gpio) \
AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
#define ath_hal_gpioGet(_ah, _gpio) \
@ -328,6 +336,8 @@ struct ath_hal_private {
(_ah)->ah_configPCIE(_ah, _reset)
#define ath_hal_disablePCIE(_ah) \
(_ah)->ah_disablePCIE(_ah)
#define ath_hal_setInterrupts(_ah, _mask) \
(_ah)->ah_setInterrupts(_ah, _mask)
#define ath_hal_eepromDetach(_ah) \
do { \

5
sys/external/isc/atheros_hal/dist/ar5210/ar5210.h vendored
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@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210.h,v 1.2 2009/05/14 09:07:49 reinoud Exp $
* $Id: ar5210.h,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#ifndef _ATH_AR5210_H_
#define _ATH_AR5210_H_
@ -206,7 +206,8 @@ extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
extern void ar5210EnableRfKill(struct ath_hal *);
extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);

7
sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210_attach.c,v 1.2 2011/02/20 11:21:03 jmcneill Exp $
* $Id: ar5210_attach.c,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -382,6 +382,11 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
}
pCap->halTstampPrecision = 15; /* NB: s/w extended from 13 */
pCap->halIntrMask = (HAL_INT_COMMON - HAL_INT_BNR)
| HAL_INT_RX
| HAL_INT_TX
| HAL_INT_FATAL
;
ahpriv->ah_rxornIsFatal = AH_TRUE;
return AH_TRUE;

6
sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210_interrupts.c,v 1.1.1.1 2008/12/11 04:46:27 alc Exp $
* $Id: ar5210_interrupts.c,v 1.2 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -59,7 +59,7 @@ ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
* status bits leak through that weren't requested
* (e.g. RXNOFRM) and that might confuse the caller.
*/
*masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg;
*masked = (isr & (HAL_INT_COMMON - HAL_INT_BNR)) & ahp->ah_maskReg;
if (isr & AR_FATAL_INT)
*masked |= HAL_INT_FATAL;
@ -105,7 +105,7 @@ ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
}
mask = ints & HAL_INT_COMMON;
mask = ints & (HAL_INT_COMMON - HAL_INT_BNR);
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
if (ints & HAL_INT_TX) {

4
sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c vendored
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@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210_misc.c,v 1.1.1.1 2008/12/11 04:46:27 alc Exp $
* $Id: ar5210_misc.c,v 1.2 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -158,7 +158,7 @@ ar5210EnableRfKill(struct ath_hal *ah)
* Configure GPIO Output lines
*/
HAL_BOOL
ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);

4
sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5210_reset.c,v 1.4 2009/01/06 06:03:57 mrg Exp $
* $Id: ar5210_reset.c,v 1.5 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -296,7 +296,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
return AH_TRUE;
bad:
if (*status)
if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL

5
sys/external/isc/atheros_hal/dist/ar5211/ar5211.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5211.h,v 1.2 2009/05/14 09:07:49 reinoud Exp $
* $Id: ar5211.h,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#ifndef _ATH_AR5211_H_
#define _ATH_AR5211_H_
@ -234,7 +234,8 @@ extern u_int ar5211GetWirelessModes(struct ath_hal *);
extern void ar5211EnableRfKill(struct ath_hal *);
extern uint32_t ar5211GpioGet(struct ath_hal *, uint32_t gpio);
extern void ar5211GpioSetIntr(struct ath_hal *, u_int, uint32_t ilevel);
extern HAL_BOOL ar5211GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5211GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5211GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5211GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern void ar5211SetLedState(struct ath_hal *, HAL_LED_STATE);

9
sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5211_attach.c,v 1.2 2011/02/20 11:21:03 jmcneill Exp $
* $Id: ar5211_attach.c,v 1.3 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -510,6 +510,13 @@ ar5211FillCapabilityInfo(struct ath_hal *ah)
}
pCap->halTstampPrecision = 13;
pCap->halIntrMask = HAL_INT_COMMON
| HAL_INT_RX
| HAL_INT_TX
| HAL_INT_FATAL
| HAL_INT_BNR
| HAL_INT_TIM
;
/* XXX might be ok w/ some chip revs */
ahpriv->ah_rxornIsFatal = AH_TRUE;

4
sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5211_misc.c,v 1.1.1.1 2008/12/11 04:46:32 alc Exp $
* $Id: ar5211_misc.c,v 1.2 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -192,7 +192,7 @@ ar5211EnableRfKill(struct ath_hal *ah)
* Configure GPIO Output lines
*/
HAL_BOOL
ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t reg;

4
sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5211_reset.c,v 1.3 2009/01/06 06:03:57 mrg Exp $
* $Id: ar5211_reset.c,v 1.4 2011/03/07 11:25:42 cegger Exp $
*/
#include "opt_ah.h"
@ -552,7 +552,7 @@ uint32_t softLedCfg, softLedState;
return AH_TRUE;
bad:
if (*status)
if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL

11
sys/external/isc/atheros_hal/dist/ar5212/ar5212.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212.h,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5212.h,v 1.4 2011/03/07 11:25:43 cegger Exp $
*/
#ifndef _ATH_AR5212_H_
#define _ATH_AR5212_H_
@ -400,7 +400,8 @@ struct ath_hal_5212 {
(_chan)->channelFlags &= ~CHANNEL_CCK; \
(_chan)->channelFlags |= CHANNEL_OFDM; \
(_flag) = AH_TRUE; \
} \
} else \
(_flag) = AH_FALSE; \
} while (0)
#define RESTORE_CCK(_ah, _chan, _flag) do { \
if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\
@ -451,7 +452,8 @@ extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
uint16_t regDomain, HAL_STATUS *stats);
extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
extern void ar5212EnableRfKill(struct ath_hal *);
extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
@ -601,4 +603,7 @@ extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
HAL_CHANNEL *);
extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
HAL_OPMODE, int);
extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
#endif /* _ATH_AR5212_H_ */

24
sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_ani.c,v 1.1.1.1 2008/12/11 04:46:39 alc Exp $
* $Id: ar5212_ani.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -267,7 +267,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
u_int level = param;
if (level >= params->maxNoiseImmunityLevel) {
if (level > params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxNoiseImmunityLevel);
@ -315,14 +315,12 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
ahp->ah_stats.ast_ani_ofdmon++;
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
}
if (on)
ahp->ah_stats.ast_ani_ofdmon++;
else
ahp->ah_stats.ast_ani_ofdmoff++;
}
aniState->ofdmWeakSigDetectOff = !on;
break;
}
@ -342,7 +340,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_FIRSTEP_LEVEL: {
u_int level = param;
if (level >= params->maxFirstepLevel) {
if (level > params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxFirstepLevel);
@ -360,7 +358,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
u_int level = param;
if (level >= params->maxSpurImmunityLevel) {
if (level > params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
__func__, level, params->maxSpurImmunityLevel);
@ -433,7 +431,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
aniState = ahp->ah_curani;
params = aniState->params;
/* First, raise noise immunity level, up to max */
if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
aniState->noiseImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
@ -441,7 +439,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
return;
}
/* then, raise spur immunity level, up to max */
if (aniState->spurImmunityLevel+1 < params->maxSpurImmunityLevel) {
if (aniState->spurImmunityLevel+1 <= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,
aniState->spurImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
@ -470,7 +468,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
* If weak sig detect is already off, as last resort,
* raise firstep level
*/
if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
@ -490,7 +488,7 @@ ar5212AniOfdmErrTrigger(struct ath_hal *ah)
HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
AH_TRUE);
}
if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: rssi %d raise ST %u\n", __func__, rssi,
aniState->firstepLevel+1);
@ -544,7 +542,7 @@ ar5212AniCckErrTrigger(struct ath_hal *ah)
/* first, raise noise immunity level, up to max */
aniState = ahp->ah_curani;
params = aniState->params;
if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
aniState->noiseImmunityLevel + 1);
ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,

24
sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_attach.c,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5212_attach.c,v 1.4 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -843,13 +843,27 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
ahpriv->ah_rxornIsFatal =
(AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
/* h/w phy counters first appeared in Hainan */
pCap->halHwPhyCounterSupport =
(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
/* enable features that first appeared in Hainan */
if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE;
AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) {
/* h/w phy counters */
pCap->halHwPhyCounterSupport = AH_TRUE;
/* bssid match disable */
pCap->halBssidMatchSupport = AH_TRUE;
}
pCap->halTstampPrecision = 15;
pCap->halIntrMask = HAL_INT_COMMON
| HAL_INT_RX
| HAL_INT_TX
| HAL_INT_FATAL
| HAL_INT_BNR
| HAL_INT_BMISC
;
if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
pCap->halIntrMask &= ~HAL_INT_TBTT;
return AH_TRUE;
#undef IS_COBRA

4
sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_gpio.c,v 1.1.1.1 2008/12/11 04:46:40 alc Exp $
* $Id: ar5212_gpio.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -36,7 +36,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);

30
sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_interrupts.c,v 1.1.1.1 2008/12/11 04:46:40 alc Exp $
* $Id: ar5212_interrupts.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -55,10 +55,11 @@ HAL_BOOL
ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
{
uint32_t isr, isr0, isr1;
uint32_t mask2=0;
uint32_t mask2;
struct ath_hal_5212 *ahp = AH5212(ah);
isr = OS_REG_READ(ah, AR_ISR);
mask2 = 0;
if (isr & AR_ISR_BCNMISC) {
uint32_t isr2;
isr2 = OS_REG_READ(ah, AR_ISR_S2);
@ -68,13 +69,15 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
mask2 |= HAL_INT_DTIM;
if (isr2 & AR_ISR_S2_DTIMSYNC)
mask2 |= HAL_INT_DTIMSYNC;
if (isr2 & (AR_ISR_S2_CABEND ))
if (isr2 & AR_ISR_S2_CABEND)
mask2 |= HAL_INT_CABEND;
if (isr2 & AR_ISR_S2_TBTT)
mask2 |= HAL_INT_TBTT;
}
isr = OS_REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;;
return AH_FALSE;
}
*masked = isr & HAL_INT_COMMON;
@ -137,7 +140,7 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t omask = ahp->ah_maskReg;
uint32_t mask,mask2;
uint32_t mask, mask2;
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
__func__, omask, ints);
@ -171,7 +174,9 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
if (ints & HAL_INT_DTIMSYNC)
mask2 |= AR_IMR_S2_DTIMSYNC;
if (ints & HAL_INT_CABEND)
mask2 |= (AR_IMR_S2_CABEND );
mask2 |= AR_IMR_S2_CABEND;
if (ints & HAL_INT_TBTT)
mask2 |= AR_IMR_S2_TBTT;
}
if (ints & HAL_INT_FATAL) {
/*
@ -184,15 +189,8 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
/* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
OS_REG_WRITE(ah, AR_IMR, mask);
OS_REG_WRITE(ah, AR_IMR_S2,
(OS_REG_READ(ah, AR_IMR_S2) &
~(AR_IMR_S2_TIM |
AR_IMR_S2_DTIM |
AR_IMR_S2_DTIMSYNC |
AR_IMR_S2_CABEND |
AR_IMR_S2_CABTO |
AR_IMR_S2_TSFOOR ) )
| mask2);
OS_REG_WRITE(ah, AR_IMR_S2,
(OS_REG_READ(ah, AR_IMR_S2) & ~AR_IMR_SR2_BCNMISC) | mask2);
ahp->ah_maskReg = ints;
/* Re-enable interrupts if they were enabled before. */
@ -200,7 +198,5 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
}
return omask;
}

43
sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_misc.c,v 1.1.1.1 2008/12/11 04:46:41 alc Exp $
* $Id: ar5212_misc.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -452,7 +452,7 @@ ar5212SetSifsTime(struct ath_hal *ah, u_int us)
return AH_FALSE;
} else {
/* convert to system clocks */
OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
ahp->ah_slottime = us;
return AH_TRUE;
}
@ -462,7 +462,7 @@ u_int
ar5212GetSifsTime(struct ath_hal *ah)
{
u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
}
HAL_BOOL
@ -803,6 +803,7 @@ ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return (ahp->ah_staId1Defaults &
AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
}
return HAL_EINVAL;
case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
switch (capability) {
case 0: /* hardware capability */
@ -1072,3 +1073,39 @@ ar5212GetDiagState(struct ath_hal *ah, int request,
}
return AH_FALSE;
}
/*
* Check whether there's an in-progress NF completion.
*
* Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE
* otherwise.
*/
HAL_BOOL
ar5212IsNFCalInProgress(struct ath_hal *ah)
{
if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
return AH_TRUE;
return AH_FALSE;
}
/*
* Wait for an in-progress NF calibration to complete.
*
* The completion function waits "i" times 10uS.
* It returns AH_TRUE if the NF calibration completed (or was never
* in progress); AH_FALSE if it was still in progress after "i" checks.
*/
HAL_BOOL
ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
{
int j;
if (i <= 0)
i = 1; /* it should run at least once */
for (j = 0; j < i; i++) {
if (! ar5212IsNFCalInProgress(ah))
return AH_TRUE;
OS_DELAY(10);
}
return AH_FALSE;
}

4
sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_power.c,v 1.1.1.1 2008/12/11 04:46:41 alc Exp $
* $Id: ar5212_power.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -39,7 +39,7 @@ ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
{
#define AR_SCR_MASK \
(AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
AR_SCR_SLEPOL|AR_SCR_MIBIE)
AR_SCR_SLEPOL|AR_SCR_MIBIE|AR_SCR_UNKNOWN)
#define POWER_UP_TIME 2000
uint32_t scr, val;
int i;

16
sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_recv.c,v 1.1.1.1 2008/12/11 04:46:41 alc Exp $
* $Id: ar5212_recv.c,v 1.2 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -163,6 +163,9 @@ ar5212GetRxFilter(struct ath_hal *ah)
bits |= HAL_RX_FILTER_PHYRADAR;
if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
bits |= HAL_RX_FILTER_PHYERR;
if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
(AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
bits |= HAL_RX_FILTER_BSSID;
return bits;
}
@ -172,10 +175,12 @@ ar5212GetRxFilter(struct ath_hal *ah)
void
ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t phybits;
OS_REG_WRITE(ah, AR_RX_FILTER,
bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR));
bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
HAL_RX_FILTER_BSSID));
phybits = 0;
if (bits & HAL_RX_FILTER_PHYRADAR)
phybits |= AR_PHY_ERR_RADAR;
@ -189,6 +194,13 @@ ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
OS_REG_WRITE(ah, AR_RXCFG,
OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
}
if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
if (bits & HAL_RX_FILTER_BSSID)
ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
else
ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
}
}
/*

4
sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_reset.c,v 1.3 2011/02/20 11:21:03 jmcneill Exp $
* $Id: ar5212_reset.c,v 1.4 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -692,7 +692,7 @@ bad:
RESTORE_CCK(ah, chan, isBmode);
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
if (*status)
if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL

6
sys/external/isc/atheros_hal/dist/ar5212/ar5212_xmit.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212_xmit.c,v 1.2 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5212_xmit.c,v 1.3 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -54,7 +54,7 @@ ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
/*
* Disable interrupts while futzing with the fifo level.
*/
omask = ar5212SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
txcfg = OS_REG_READ(ah, AR_TXCFG);
curLevel = MS(txcfg, AR_FTRIG);
@ -72,7 +72,7 @@ ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
ahp->ah_txTrigLev = newLevel;
/* re-enable chip interrupts */
ar5212SetInterrupts(ah, omask);
ath_hal_setInterrupts(ah, omask);
return (newLevel != curLevel);
}

16
sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5212reg.h,v 1.1.1.1 2008/12/11 04:46:44 alc Exp $
* $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212reg.h,v 1.4 2010/01/29 10:10:14 rpaulo Exp $
*/
#ifndef _DEV_ATH_AR5212REG_H_
#define _DEV_ATH_AR5212REG_H_
@ -463,7 +463,8 @@
#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */
#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */
#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */
#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */
#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */
#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
@ -531,8 +532,14 @@
#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */
#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */
#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */
#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */
#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */
#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */
/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
#define AR_IMR_SR2_BCNMISC \
(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \
AR_IMR_S2_TBTT)
#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
@ -693,6 +700,7 @@
#define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */
#define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */
#define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */
#define AR_SCR_UNKNOWN 0x00400000
#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */

8
sys/external/isc/atheros_hal/dist/ar5312/ar5312.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5312.h,v 1.2 2008/12/11 05:30:29 alc Exp $
* $Id: ar5312.h,v 1.3 2011/03/07 11:25:43 cegger Exp $
*/
#ifndef _ATH_AR5312_H_
#define _ATH_AR5312_H_
@ -41,14 +41,16 @@
extern HAL_BOOL ar5312IsInterruptPending(struct ath_hal *ah);
/* AR5312 */
extern HAL_BOOL ar5312GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5312GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5312GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5312GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5312GpioGet(struct ath_hal *ah, uint32_t gpio);
extern void ar5312GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
/* AR2315+ */
extern HAL_BOOL ar5315GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5315GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5315GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5315GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5315GpioGet(struct ath_hal *ah, uint32_t gpio);

5
sys/external/isc/atheros_hal/dist/ar5312/ar5312_attach.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5312_attach.c,v 1.2 2008/12/11 05:30:29 alc Exp $
* $Id: ar5312_attach.c,v 1.3 2011/03/07 11:25:43 cegger Exp $
*/
#include "opt_ah.h"
@ -122,7 +122,7 @@ ar5312Attach(uint16_t devid, HAL_SOFTC sc,
/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
if (!ar5312ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
@ -321,6 +321,7 @@ ar5312Probe(uint16_t vendorid, uint16_t devid)
case AR5212_AR2315_REV7:
return "Atheros 2315 WiSoC";
case AR5212_AR2317_REV1:
case AR5212_AR2317_REV2:
return "Atheros 2317 WiSoC";
case AR5212_AR2413:
return "Atheros 2413";

4
sys/external/isc/atheros_hal/dist/ar5312/ar5312_gpio.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5312_gpio.c,v 1.1.1.1 2008/12/11 04:46:45 alc Exp $
* $Id: ar5312_gpio.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -35,7 +35,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));

4
sys/external/isc/atheros_hal/dist/ar5312/ar5312_reset.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5312_reset.c,v 1.1.1.1 2008/12/11 04:46:46 alc Exp $
* $Id: ar5312_reset.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -597,7 +597,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
return AH_TRUE;
bad:
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
if (*status)
if (status != NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL

4
sys/external/isc/atheros_hal/dist/ar5312/ar5315_gpio.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5315_gpio.c,v 1.1.1.1 2008/12/11 04:46:46 alc Exp $
* $Id: ar5315_gpio.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -35,7 +35,7 @@
* Configure GPIO Output lines
*/
HAL_BOOL
ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));

7
sys/external/isc/atheros_hal/dist/ar5416/ar5416.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416.h,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5416.h,v 1.4 2011/03/07 11:25:44 cegger Exp $
*/
#ifndef _ATH_AR5416_H_
#define _ATH_AR5416_H_
@ -45,6 +45,7 @@ typedef struct {
#define AR5416_CCA_MAX_GOOD_VALUE -85
#define AR5416_CCA_MAX_HIGH_VALUE -62
#define AR5416_CCA_MIN_BAD_VALUE -140
#define AR5416_CCA_MIN_GOOD_VALUE -118
#define AR5416_SPUR_RSSI_THRESH 40
@ -68,6 +69,7 @@ struct ath_hal_5416 {
HAL_CHANNEL_INTERNAL *);
u_int ah_globaltxtimeout; /* global tx timeout */
u_int ah_gpioMask;
int ah_hangs; /* h/w hangs state */
uint8_t ah_keytype[AR5416_KEYTABLE_SIZE];
/*
@ -131,7 +133,8 @@ extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah);
extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *, HAL_INT *masked);
extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints);
extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio,
HAL_GPIO_MUX_TYPE);
extern HAL_BOOL ar5416GpioCfgInput(struct ath_hal *, uint32_t gpio);
extern HAL_BOOL ar5416GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
extern uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio);

8
sys/external/isc/atheros_hal/dist/ar5416/ar5416_ani.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_ani.c,v 1.1.1.1 2008/12/11 04:46:47 alc Exp $
* $Id: ar5416_ani.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -220,7 +220,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (level >= params->maxNoiseImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
"%s: immunity level out of range (%u > %u)\n",
__func__, level, params->maxNoiseImmunityLevel);
return AH_FALSE;
}
@ -304,7 +304,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (level >= params->maxFirstepLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
"%s: firstep level out of range (%u > %u)\n",
__func__, level, params->maxFirstepLevel);
return AH_FALSE;
}
@ -322,7 +322,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
if (level >= params->maxSpurImmunityLevel) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: level out of range (%u > %u)\n",
"%s: spur level out of range (%u > %u)\n",
__func__, level, params->maxSpurImmunityLevel);
return AH_FALSE;
}

28
sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_attach.c,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5416_attach.c,v 1.4 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -263,6 +263,13 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
}
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
ar5416AttachPCIE(ah);
ecode = ath_hal_v14EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
__func__);
@ -316,13 +323,6 @@ ar5416Attach(uint16_t devid, HAL_SOFTC sc,
#endif
}
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
ar5416AttachPCIE(ah);
ecode = ath_hal_v14EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
/*
* Got everything we need now to setup the capabilities.
*/
@ -790,6 +790,17 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
pCap->halTstampPrecision = 32;
pCap->halHwPhyCounterSupport = AH_TRUE;
pCap->halIntrMask = HAL_INT_COMMON
| HAL_INT_RX
| HAL_INT_TX
| HAL_INT_FATAL
| HAL_INT_BNR
| HAL_INT_BMISC
| HAL_INT_DTIMSYNC
| HAL_INT_TSFOOR
| HAL_INT_CST
| HAL_INT_GTT
;
pCap->halFastCCSupport = AH_TRUE;
pCap->halNumGpioPins = 6;
@ -809,6 +820,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
pCap->halMbssidAggrSupport = AH_TRUE;
pCap->halForcePpmSupport = AH_TRUE;
pCap->halEnhancedPmSupport = AH_TRUE;
pCap->halBssidMatchSupport = AH_TRUE;
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {

48
sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_cal.c,v 1.1.1.1 2008/12/11 04:46:47 alc Exp $
* $Id: ar5416_cal.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -24,6 +24,8 @@
#include "ah_eeprom_v14.h"
#include "ar5212/ar5212.h" /* for NF cal related declarations */
#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"
@ -218,7 +220,17 @@ ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan)
* higher than normal value if DC offset and noise floor cal are
* triggered at the same time.
*/
/* XXX this actually kicks off a NF calibration -adrian */
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
/*
* Try to make sure the above NF cal completes, just so
* it doesn't clash with subsequent percals - adrian
*/
if (!ar5212WaitNFCalComplete(ah, 10000)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: initial NF calibration did "
"not complete in time; noisy environment?\n", __func__);
return AH_FALSE;
}
/* Initialize list pointers */
cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
@ -395,6 +407,13 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
*isCalDone = AH_TRUE;
/*
* Since ath_hal calls the PerCal method with rxchainmask=0x1;
* override it with the current chainmask. The upper levels currently
* doesn't know about the chainmask.
*/
rxchainmask = AH5416(ah)->ah_rx_chainmask;
/* Invalid channel check */
ichan = ath_hal_checkchannel(ah, chan);
if (ichan == AH_NULL) {
@ -443,12 +462,6 @@ ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
/* start NF calibration, without updating BB NF register*/
ar5416StartNFCal(ah);
if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
/* report up and clear internal state */
chan->channelFlags |= CHANNEL_CW_INT;
ichan->channelFlags &= ~CHANNEL_CW_INT;
}
}
return AH_TRUE;
}
@ -523,7 +536,7 @@ ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
AR_PHY_CH2_EXT_CCA
};
struct ar5212NfCalHist *h;
int i, j;
int i;
int32_t val;
uint8_t chainmask;
@ -559,10 +572,21 @@ ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
/* Wait for load to complete, should be fast, a few 10s of us. */
for (j = 0; j < 1000; j++) {
if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
break;
OS_DELAY(10);
if (! ar5212WaitNFCalComplete(ah, 10000)) {
/*
* We timed out waiting for the noisefloor to load, probably due
* to an in-progress rx. Simply return here and allow the load
* plenty of time to complete before the next calibration
* interval. We need to avoid trying to load -50 (which happens
* below) while the previous load is still in progress as this
* can cause rx deafness. Instead by returning here, the
* baseband nf cal will just be capped by our present
* noisefloor until the next calibration timer.
*/
HALDEBUG(ah, HAL_DEBUG_ANY, "Timeout while waiting for nf "
"to load: AR_PHY_AGC_CONTROL=0x%x\n",
OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
return;
}
/*

4
sys/external/isc/atheros_hal/dist/ar5416/ar5416_cal_iq.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_cal_iq.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
* $Id: ar5416_cal_iq.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -115,7 +115,7 @@ ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains)
if (qCoff > 15)
qCoff = 15;
else if (qCoff <= -16)
qCoff = 16;
qCoff = -16;
HALDEBUG(ah, HAL_DEBUG_PERCAL,
" : iCoff = 0x%x qCoff = 0x%x\n", iCoff, qCoff);

191
sys/external/isc/atheros_hal/dist/ar5416/ar5416_gpio.c vendored
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
* Copyright (c) 2002-2008 Atheros Communications, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -14,43 +14,102 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_gpio.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
* $FreeBSD: src/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c,v 1.5 2010/01/29 10:10:14 rpaulo Exp $
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_devid.h"
#ifdef AH_DEBUG
#include "ah_desc.h" /* NB: for HAL_PHYERR* */
#endif
#include "ar5416/ar5416.h"
#include "ar5416/ar5416reg.h"
#include "ar5416/ar5416phy.h"
#define AR_NUM_GPIO 6 /* 6 GPIO pins */
#define AR_GPIO_BIT(_gpio) (1 << _gpio)
/*
* Configure GPIO Output Mux control
*/
static void
cfgOutputMux(struct ath_hal *ah, uint32_t gpio, uint32_t type)
{
int addr;
uint32_t gpio_shift, reg;
/* each MUX controls 6 GPIO pins */
if (gpio > 11)
addr = AR_GPIO_OUTPUT_MUX3;
else if (gpio > 5)
addr = AR_GPIO_OUTPUT_MUX2;
else
addr = AR_GPIO_OUTPUT_MUX1;
/*
* 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux,
* bits 5..9 for 2nd pin, etc.
*/
gpio_shift = (gpio % 6) * 5;
/*
* From Owl to Merlin 1.0, the value read from MUX1 bit 4 to bit
* 9 are wrong. Here is hardware's coding:
* PRDATA[4:0] <= gpio_output_mux[0];
* PRDATA[9:4] <= gpio_output_mux[1];
* <==== Bit 4 is used by both gpio_output_mux[0] [1].
* Currently the max value for gpio_output_mux[] is 6. So bit 4
* will never be used. So it should be fine that bit 4 won't be
* able to recover.
*/
reg = OS_REG_READ(ah, addr);
if (addr == AR_GPIO_OUTPUT_MUX1 && !AR_SREV_MERLIN_20_OR_LATER(ah))
reg = ((reg & 0x1F0) << 1) | (reg & ~0x1F0);
reg &= ~(0x1f << gpio_shift);
reg |= type << gpio_shift;
OS_REG_WRITE(ah, addr, reg);
}
/*
* Configure GPIO Output lines
*/
HAL_BOOL
ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
{
HALASSERT(gpio < AR_NUM_GPIO);
OS_REG_CLR_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
uint32_t gpio_shift, reg;
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
/* NB: type maps directly to hardware */
cfgOutputMux(ah, gpio, type);
gpio_shift = gpio << 1; /* 2 bits per output mode */
reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
return AH_TRUE;
}
/*
* Configure GPIO Input lines
*/
HAL_BOOL
ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
{
HALASSERT(gpio < AR_NUM_GPIO);
OS_REG_SET_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
uint32_t gpio_shift, reg;
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
/* TODO: configure input mux for AR5416 */
/* If configured as input, set output to tristate */
gpio_shift = gpio << 1;
reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
reg &= ~(AR_GPIO_OE_OUT_DRV << gpio_shift);
reg |= AR_GPIO_OE_OUT_DRV_ALL << gpio_shift;
OS_REG_WRITE(ah, AR_GPIO_OE_OUT, reg);
return AH_TRUE;
}
@ -62,14 +121,14 @@ ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
{
uint32_t reg;
HALASSERT(gpio < AR_NUM_GPIO);
reg = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_OUT_VAL);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
if (val & 1)
reg |= AR_GPIO_BIT(gpio);
else
reg &= ~AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_OUT_VAL, reg);
OS_REG_WRITE(ah, AR_GPIO_IN_OUT, reg);
return AH_TRUE;
}
@ -79,34 +138,94 @@ ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
uint32_t
ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
{
if (gpio >= AR_NUM_GPIO)
uint32_t bits;
if (gpio >= AH_PRIVATE(ah)->ah_caps.halNumGpioPins)
return 0xffffffff;
return ((OS_REG_READ(ah, AR_GPIO_IN) & AR_GPIO_BIT(gpio)) >> gpio);
/*
* Read output value for all gpio's, shift it,
* and verify whether the specific bit is set.
*/
if (AR_SREV_KITE_10_OR_LATER(ah))
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
else if (AR_SREV_MERLIN_10_OR_LATER(ah))
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
else
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
return ((bits & AR_GPIO_BIT(gpio)) != 0);
}
/*
* Set the GPIO Interrupt
* Set the GPIO Interrupt Sync and Async interrupts are both set/cleared.
* Async GPIO interrupts may not be raised when the chip is put to sleep.
*/
void
ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
{
uint32_t val;
HALASSERT(gpio < AR_NUM_GPIO);
/* XXX bounds check gpio */
val = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_INTR_CTRL);
if (ilevel) /* 0 == interrupt on pin high */
val &= ~AR_GPIO_BIT(gpio);
else /* 1 == interrupt on pin low */
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_INTR_CTRL, val);
uint32_t val, mask;
/* Change the interrupt mask. */
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_GPIO);
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_GPIO, val);
HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_GPIO);
val |= AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_GPIO, val);
if (ilevel == HAL_GPIO_INTR_DISABLE) {
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
AR_INTR_ASYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
AR_INTR_ASYNC_ENABLE_GPIO, val);
mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
AR_INTR_ASYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
AR_INTR_ASYNC_MASK_GPIO, mask);
/* Clear synchronous GPIO interrupt registers and pending interrupt flag */
val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
AR_INTR_SYNC_ENABLE_GPIO) &~ AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
AR_INTR_SYNC_ENABLE_GPIO, val);
mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
AR_INTR_SYNC_MASK_GPIO) &~ AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
AR_INTR_SYNC_MASK_GPIO, mask);
val = MS(OS_REG_READ(ah, AR_INTR_SYNC_CAUSE),
AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,
AR_INTR_SYNC_ENABLE_GPIO, val);
} else {
val = MS(OS_REG_READ(ah, AR_GPIO_INTR_POL),
AR_GPIO_INTR_POL_VAL);
if (ilevel == HAL_GPIO_INTR_HIGH) {
/* 0 == interrupt on pin high */
val &= ~AR_GPIO_BIT(gpio);
} else if (ilevel == HAL_GPIO_INTR_LOW) {
/* 1 == interrupt on pin low */
val |= AR_GPIO_BIT(gpio);
}
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,
AR_GPIO_INTR_POL_VAL, val);
/* Change the interrupt mask. */
val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
AR_INTR_ASYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
AR_INTR_ASYNC_ENABLE_GPIO, val);
mask = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK),
AR_INTR_ASYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
AR_INTR_ASYNC_MASK_GPIO, mask);
/* Set synchronous GPIO interrupt registers as well */
val = MS(OS_REG_READ(ah, AR_INTR_SYNC_ENABLE),
AR_INTR_SYNC_ENABLE_GPIO) | AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
AR_INTR_SYNC_ENABLE_GPIO, val);
mask = MS(OS_REG_READ(ah, AR_INTR_SYNC_MASK),
AR_INTR_SYNC_MASK_GPIO) | AR_GPIO_BIT(gpio);
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
AR_INTR_SYNC_MASK_GPIO, mask);
}
AH5416(ah)->ah_gpioMask = mask; /* for ar5416SetInterrupts */
}

13
sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_interrupts.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $
* $Id: ar5416_interrupts.c,v 1.2 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -104,7 +104,7 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
isr = OS_REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
*masked = 0;
return AH_FALSE;;
return AH_FALSE;
}
*masked = isr & HAL_INT_COMMON;
@ -120,6 +120,13 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
}
if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) {
uint32_t isr5;
isr5 = OS_REG_READ(ah, AR_ISR_S5_S);
if (isr5 & AR_ISR_S5_TIM_TIMER)
*masked |= HAL_INT_TIM_TIMER;
}
/* Interrupt Mitigation on AR5416 */
#ifdef AR5416_INT_MITIGATION
if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
@ -167,7 +174,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
{
struct ath_hal_5212 *ahp = AH5212(ah);
uint32_t omask = ahp->ah_maskReg;
uint32_t mask,mask2;
uint32_t mask, mask2;
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
__func__, omask, ints);

22
sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416_reset.c,v 1.4 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5416_reset.c,v 1.5 2011/03/07 11:25:44 cegger Exp $
*/
#include "opt_ah.h"
@ -100,7 +100,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_CHANNEL_INTERNAL *ichan;
uint32_t softLedCfg;
uint32_t saveDefAntenna, saveLedState;
uint32_t macStaId1;
uint16_t rfXpdGain[2];
@ -185,7 +184,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
(AR_MAC_LED_ASSOC | AR_MAC_LED_MODE |
AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
softLedCfg = OS_REG_READ(ah, AR_GPIO_INTR_OUT);
if (!ar5416ChipReset(ah, chan)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
@ -196,11 +194,20 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
if (AR_SREV_MERLIN_10_OR_LATER(ah))
OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
if (AR_SREV_KITE(ah)) {
uint32_t val;
val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
val &= ~AR_PHY_RIFS_INIT_DELAY;
OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
}
AH5416(ah)->ah_writeIni(ah, (HAL_CHANNEL_INTERNAL *)chan);
/* Setup 11n MAC/Phy mode registers */
ar5416Set11nRegs(ah,chan);
ar5416Set11nRegs(ah, chan);
OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
@ -281,9 +288,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
/* Restore previous led state */
OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
/* Restore soft Led state to GPIO */
OS_REG_WRITE(ah, AR_GPIO_INTR_OUT, softLedCfg);
/* Restore previous antenna */
OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
@ -372,7 +376,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
return AH_TRUE;
bad:
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
if (*status)
if (status != AH_NULL)
*status = ecode;
return AH_FALSE;
#undef FAIL
@ -1082,6 +1086,8 @@ ar5416SetResetPowerOn(struct ath_hal *ah)
OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
OS_REG_WRITE(ah, AR_RTC_RESET, 0);
OS_DELAY(20);
OS_REG_WRITE(ah, AR_RC, 0);
OS_REG_WRITE(ah, AR_RTC_RESET, 1);
/*

10
sys/external/isc/atheros_hal/dist/ar5416/ar5416phy.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416phy.h,v 1.2 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5416phy.h,v 1.3 2011/03/07 11:25:44 cegger Exp $
*/
#ifndef _DEV_ATH_AR5416PHY_H_
#define _DEV_ATH_AR5416PHY_H_
@ -48,6 +48,7 @@
#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
#define AR_PHY_TIMING2_USE_FORCE 0x00001000
@ -110,6 +111,9 @@
#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
#define AR_PHY_REFCLKDLY 0x99f4
#define AR_PHY_REFCLKPD 0x99f8
@ -221,6 +225,9 @@
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
#define AR_PHY_MASK2_M_31_45 0xa3a4
#define AR_PHY_MASK2_M_16_30 0xa3a8
@ -261,4 +268,5 @@
#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
#define AR_PHY_CL_CAL_ENABLE 0x00000002
#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
#endif /* _DEV_ATH_AR5416PHY_H_ */

163
sys/external/isc/atheros_hal/dist/ar5416/ar5416reg.h vendored
View File

@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Id: ar5416reg.h,v 1.3 2011/02/21 11:06:38 cegger Exp $
* $Id: ar5416reg.h,v 1.4 2011/03/07 11:25:44 cegger Exp $
*/
#ifndef _DEV_ATH_AR5416REG_H
#define _DEV_ATH_AR5416REG_H
@ -43,8 +43,15 @@
#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */
#define AR5416_PCIE_SERDES 0x4040
#define AR5416_PCIE_SERDES2 0x4044
#define AR_GPIO_IN 0x4048 /* GPIO input register */
#define AR_GPIO_INTR_OUT 0x404c /* GPIO output register */
#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */
#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */
#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */
#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */
#define AR_GPIO_INPUT_MUX1 0x4058
#define AR_GPIO_INPUT_MUX2 0x405c
#define AR_GPIO_OUTPUT_MUX1 0x4060
#define AR_GPIO_OUTPUT_MUX2 0x4064
#define AR_GPIO_OUTPUT_MUX3 0x4068
#define AR_EEPROM_STATUS_DATA 0x407c
#define AR_OBS 0x4080
#define AR_RTC_RC 0x7000 /* reset control */
@ -65,11 +72,11 @@
#define AR_AN_SYNTH9 0x7868
#define AR9285_AN_RF2G1 0x7820
#define AR9285_AN_RF2G2 0x7824
#define AR9285_AN_RF2G3 0x7828
#define AR9285_AN_RF2G4 0x782c
#define AR9285_AN_RF2G3 0x7828
#define AR9285_AN_RF2G4 0x782C
#define AR9285_AN_RF2G6 0x7834
#define AR9285_AN_RF2G7 0x7838
#define AR9285_AN_RF2G8 0x783c
#define AR9285_AN_RF2G8 0x783C
#define AR9285_AN_RF2G9 0x7840
#define AR9285_AN_RXTXBB1 0x7854
#define AR9285_AN_TOP2 0x7868
@ -238,6 +245,10 @@
#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */
#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */
#define AR_ISR_S5 0x0098
#define AR_ISR_S5_S 0x00d8
#define AR_ISR_S5_TIM_TIMER 0x00000010
#define AR_INTR_SPURIOUS 0xffffffff
#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */
#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */
@ -283,6 +294,21 @@
AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
AR_INTR_SYNC_MAC_SLEEP_ACCESS)
#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
#define AR_INTR_SYNC_MASK_GPIO_S 18
#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
#define AR_INTR_SYNC_ENABLE_GPIO_S 18
#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */
#define AR_INTR_ASYNC_MASK_GPIO_S 18
#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */
#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO)
#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */
#define AR_INTR_ASYNC_ENABLE_GPIO_S 18
/* RTC registers */
#define AR_RTC_RC_M 0x00000003
#define AR_RTC_RC_MAC_WARM 0x00000001
@ -350,41 +376,83 @@
#define AR_AN_SYNTH9_REFDIVA_S 27
/* AR9285 Analog registers */
#define AR9285_AN_RF2G3_OB_0 0x00E00000
#define AR9285_AN_RF2G3_OB_0_S 21
#define AR9285_AN_RF2G3_OB_1 0x001C0000
#define AR9285_AN_RF2G3_OB_1_S 18
#define AR9285_AN_RF2G3_OB_2 0x00038000
#define AR9285_AN_RF2G3_OB_2_S 15
#define AR9285_AN_RF2G3_OB_3 0x00007000
#define AR9285_AN_RF2G3_OB_3_S 12
#define AR9285_AN_RF2G3_OB_4 0x00000E00
#define AR9285_AN_RF2G3_OB_4_S 9
#define AR9285_AN_RF2G1_ENPACAL 0x00000800
#define AR9285_AN_RF2G1_ENPACAL_S 11
#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
#define AR9285_AN_RF2G1_PDPADRV1_S 25
#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
#define AR9285_AN_RF2G1_PDPADRV2_S 24
#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
#define AR9285_AN_RF2G1_PDPAOUT_S 23
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
#define AR9285_AN_RF2G3_DB1_0_S 6
#define AR9285_AN_RF2G3_DB1_1 0x00000038
#define AR9285_AN_RF2G3_DB1_1_S 3
#define AR9285_AN_RF2G3_DB1_2 0x00000007
#define AR9285_AN_RF2G3_DB1_2_S 0
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
#define AR9285_AN_RF2G4_DB1_3_S 29
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
#define AR9285_AN_RF2G4_DB1_4_S 26
#define AR9285_AN_RF2G2_OFFCAL 0x00001000
#define AR9285_AN_RF2G2_OFFCAL_S 12
#define AR9285_AN_RF2G4_DB2_0 0x03800000
#define AR9285_AN_RF2G4_DB2_0_S 23
#define AR9285_AN_RF2G4_DB2_1 0x00700000
#define AR9285_AN_RF2G4_DB2_1_S 20
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
#define AR9285_AN_RF2G4_DB2_2_S 17
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
#define AR9285_AN_RF2G4_DB2_3_S 14
#define AR9285_AN_RF2G4_DB2_4 0x00003800
#define AR9285_AN_RF2G4_DB2_4_S 11
#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
#define AR9285_AN_RF2G3_PDVCCOMP_S 25
#define AR9285_AN_RF2G3_OB_0 0x00E00000
#define AR9285_AN_RF2G3_OB_0_S 21
#define AR9285_AN_RF2G3_OB_1 0x001C0000
#define AR9285_AN_RF2G3_OB_1_S 18
#define AR9285_AN_RF2G3_OB_2 0x00038000
#define AR9285_AN_RF2G3_OB_2_S 15
#define AR9285_AN_RF2G3_OB_3 0x00007000
#define AR9285_AN_RF2G3_OB_3_S 12
#define AR9285_AN_RF2G3_OB_4 0x00000E00
#define AR9285_AN_RF2G3_OB_4_S 9
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
#define AR9285_AN_RF2G3_DB1_0_S 6
#define AR9285_AN_RF2G3_DB1_1 0x00000038
#define AR9285_AN_RF2G3_DB1_1_S 3
#define AR9285_AN_RF2G3_DB1_2 0x00000007
#define AR9285_AN_RF2G3_DB1_2_S 0
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
#define AR9285_AN_RF2G4_DB1_3_S 29
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
#define AR9285_AN_RF2G4_DB1_4_S 26
#define AR9285_AN_RF2G4_DB2_0 0x03800000
#define AR9285_AN_RF2G4_DB2_0_S 23
#define AR9285_AN_RF2G4_DB2_1 0x00700000
#define AR9285_AN_RF2G4_DB2_1_S 20
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
#define AR9285_AN_RF2G4_DB2_2_S 17
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
#define AR9285_AN_RF2G4_DB2_3_S 14
#define AR9285_AN_RF2G4_DB2_4 0x00003800
#define AR9285_AN_RF2G4_DB2_4_S 11
#define AR9285_AN_RF2G6_CCOMP 0x00007800
#define AR9285_AN_RF2G6_CCOMP_S 11
#define AR9285_AN_RF2G6_OFFS 0x03f00000
#define AR9285_AN_RF2G6_OFFS_S 20
#define AR9271_AN_RF2G6_OFFS 0x07f00000
#define AR9271_AN_RF2G6_OFFS_S 20
#define AR9285_AN_RF2G7_PWDDB 0x00000002
#define AR9285_AN_RF2G7_PWDDB_S 1
#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
#define AR9285_AN_RXTXBB1_PDV2I_S 7
#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
#define AR9285_AN_RXTXBB1_PDDACIF_S 8
#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
#define AR9285_AN_RXTXBB1_SPARE9_S 0
#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
#define AR9285_AN_TOP3_PWDDAC 0x00800000
#define AR9285_AN_TOP3_PWDDAC_S 23
/* Sleep control */
#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */
@ -444,10 +512,29 @@
#define AR_GPIO_INTR_CTRL 0x3FF00000
#define AR_GPIO_INTR_CTRL_S 20
#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */
#define AR_GPIO_IN_VAL_S 14
#define AR928X_GPIO_IN_VAL 0x000FFC00
#define AR928X_GPIO_IN_VAL_S 10
#define AR9285_GPIO_IN_VAL 0x00FFF000
#define AR9285_GPIO_IN_VAL_S 12
#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */
#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */
#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */
#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */
#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */
#define AR_GPIO_INTR_POL_VAL 0x1FFF
#define AR_GPIO_INTR_POL_VAL_S 0
#define AR_GPIO_JTAG_DISABLE 0x00020000
#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */
#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
/* Eeprom defines */
#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
@ -522,10 +609,10 @@
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
#define AR_SREV_MERLIN_20(_ah) \
(AR_SREV_MERLIN(_ah) && \
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20)
#define AR_SREV_MERLIN_20_OR_LATER(_ah) \
(AR_SREV_MERLIN_20(_ah) || \
AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
#define AR_SREV_KITE(_ah) \
(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)