clear CPU count register interrupt properly (VR4100).
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ca70dbd353
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.24 2000/05/09 13:20:55 shin Exp $ */
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/* $NetBSD: machdep.c,v 1.25 2000/05/14 03:16:11 shin Exp $ */
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/*
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1988 University of Utah.
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@ -43,7 +43,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.24 2000/05/09 13:20:55 shin Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.25 2000/05/14 03:16:11 shin Exp $");
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/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
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/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
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#include "opt_vr41x1.h"
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#include "opt_vr41x1.h"
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@ -731,15 +731,15 @@ cpu_intr(status, cause, pc, ipending)
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{
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{
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uvmexp.intrs++;
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uvmexp.intrs++;
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#if defined(MIPS3) && defined(MIPS_INT_MASK_CLOCK)
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#ifdef VR41X1
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if (ipending & MIPS_INT_MASK_CLOCK) {
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if (ipending & MIPS_INT_MASK_5) {
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/*
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/*
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* Writing a value to the Compare register,
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* Writing a value to the Compare register,
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* as a side effect, clears the timer interrupt request.
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* as a side effect, clears the timer interrupt request.
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*/
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*/
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mips3_write_compare(mips3_cycle_count());
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mips3_write_compare(mips3_cycle_count());
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}
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}
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#endif /* MIPS3 && MIPS_INT_MASK_CLOCK */
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#endif
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/* device interrupts */
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/* device interrupts */
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#ifdef ENABLE_MIPS_TX3900
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#ifdef ENABLE_MIPS_TX3900
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