Driver code for SA11x1 based PCMCIA devices.
This commit is contained in:
toshii
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79d31f6571
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/* $NetBSD: sa11x1_pcic.c,v 1.1 2001/03/10 19:01:27 toshii Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <dev/pcmcia/pcmciachip.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <hpcarm/sa11x0/sa11x0_reg.h>
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#include <hpcarm/sa11x0/sa11x0_var.h>
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#include <hpcarm/sa11x0/sa1111_reg.h>
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#include <hpcarm/sa11x0/sa1111_var.h>
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#include <hpcarm/sa11x0/sa11x1_pcicreg.h>
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#include <hpcarm/sa11x0/sa11xx_pcicvar.h>
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#include "sacpcic.h"
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static int sacpcic_match(struct device *, struct cfdata *, void *);
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static void sacpcic_attach(struct device *, struct device *, void *);
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static int sacpcic_print(void *, const char *);
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static int sacpcic_submatch(struct device *, struct cfdata *, void *);
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static int sacpcic_read(struct sapcic_socket *, int);
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static void sacpcic_write(struct sapcic_socket *, int, int);
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static void sacpcic_set_power(struct sapcic_socket *, int);
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static void sacpcic_clear_intr(int);
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static void *sacpcic_intr_establish(struct sapcic_socket *, int,
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int (*)(void *), void *);
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static void sacpcic_intr_disestablish(struct sapcic_socket *, void *);
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struct sacpcic_softc {
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struct sapcic_softc sc_pc;
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bus_space_handle_t sc_ioh;
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struct sapcic_socket sc_socket[2];
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};
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static struct sapcic_tag sacpcic_functions = {
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sacpcic_read,
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sacpcic_write,
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sacpcic_set_power,
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sacpcic_clear_intr,
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sacpcic_intr_establish,
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sacpcic_intr_disestablish
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};
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struct cfattach sacpcic_ca = {
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sizeof(struct sacpcic_softc), sacpcic_match, sacpcic_attach
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};
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static int
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sacpcic_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return (1);
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}
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static void
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sacpcic_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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int i;
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struct pcmciabus_attach_args paa;
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struct sacpcic_softc *sc = (struct sacpcic_softc *)self;
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struct sacc_softc *psc = (struct sacc_softc *)parent;
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sc->sc_pc.sc_iot = psc->sc_iot;
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sc->sc_ioh = psc->sc_ioh;
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for(i = 0; i < 2; i++) {
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sc->sc_socket[i].sc = (struct sapcic_softc *)sc;
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sc->sc_socket[i].socket = i;
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sc->sc_socket[i].saip_sc = NULL;
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sc->sc_socket[i].sacc_sc = psc;
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sc->sc_socket[i].pcictag = &sacpcic_functions;
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sc->sc_socket[i].pddata = NULL; /* XXX */
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sc->sc_socket[i].event_thread = NULL;
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sc->sc_socket[i].event = 0;
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sc->sc_socket[i].laststatus = SAPCIC_CARD_INVALID;
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sc->sc_socket[i].shutdown = 0;
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paa.paa_busname = "pcmcia";
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paa.pct = (pcmcia_chipset_tag_t)&sa11x0_pcmcia_functions;
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paa.pch = (pcmcia_chipset_handle_t)&sc->sc_socket[i];
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paa.iobase = 0;
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paa.iosize = 0x4000000;
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sc->sc_socket[i].pcmcia =
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(struct device *)config_found_sm(&sc->sc_pc.sc_dev,
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&paa, sacpcic_print, sacpcic_submatch);
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sacc_intr_establish((sacc_chipset_tag_t)psc,
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i ? IRQ_S1_CDVALID : IRQ_S0_CDVALID,
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1, IPL_BIO, sapcic_intr,
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&sc->sc_socket[i]);
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/* schedule kthread creation */
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kthread_create(sapcic_kthread_create, &sc->sc_socket[i]);
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#if 0 /* XXX */
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/* establish_intr should be after creating the kthread */
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config_interrupt(&sc->sc_socket[i], sacpcic_config_intr);
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#endif
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}
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}
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static int
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sacpcic_print(aux, name)
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void *aux;
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const char *name;
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{
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printf("\n");
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return (UNCONF);
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}
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static int
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sacpcic_submatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return (*cf->cf_attach->ca_match)(parent, cf, aux);
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}
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static int
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sacpcic_read(so, reg)
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struct sapcic_socket *so;
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int reg;
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{
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int cr, bit;
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struct sacpcic_softc *sc = (struct sacpcic_softc *)so->sc;
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cr = bus_space_read_4(sc->sc_pc.sc_iot, sc->sc_ioh, SACPCIC_SR);
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switch (reg) {
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case SAPCIC_STATUS_CARD:
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bit = (so->socket ? SR_S1_CARDDETECT : SR_S0_CARDDETECT) & cr;
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if (bit)
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return SAPCIC_CARD_INVALID;
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else
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return SAPCIC_CARD_VALID;
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default:
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panic("sacpcic_read: bogus register\n");
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}
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}
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static void
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sacpcic_write(so, reg, arg)
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struct sapcic_socket *so;
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int reg;
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int arg;
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{
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int s, oldvalue, newvalue, mask;
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struct sacpcic_softc *sc = (struct sacpcic_softc *)so->sc;
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s = splhigh();
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oldvalue = bus_space_read_4(sc->sc_pc.sc_iot, sc->sc_ioh, SACPCIC_CR);
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switch (reg) {
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case SAPCIC_CONTROL_RESET:
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mask = so->socket ? CR_S1_RST : CR_S0_RST;
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newvalue = (oldvalue & ~mask) | (arg ? mask : 0);
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break;
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case SAPCIC_CONTROL_LINEENABLE:
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mask = so->socket ? CR_S1_FLT : CR_S0_FLT;
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newvalue = (oldvalue & ~mask) | (arg ? mask : 0);
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break;
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case SAPCIC_CONTROL_WAITENABLE:
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mask = so->socket ? CR_S1_PWAITEN : CR_S0_PWAITEN;
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newvalue = (oldvalue & ~mask) | (arg ? mask : 0);
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break;
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case SAPCIC_CONTROL_POWERSELECT:
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mask = so->socket ? CR_S1_PSE : CR_S0_PSE;
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newvalue = oldvalue & ~mask;
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switch (arg) {
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case SAPCIC_POWER_3V:
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break;
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case SAPCIC_POWER_5V:
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newvalue |= mask;
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break;
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default:
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splx(s);
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panic("sacpcic_write: bogus arg");
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}
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break;
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default:
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splx(s);
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panic("sacpcic_write: bogus register");
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}
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bus_space_write_4(sc->sc_pc.sc_iot, sc->sc_ioh, SACPCIC_CR, newvalue);
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splx(s);
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}
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static void
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sacpcic_set_power(so, arg)
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struct sapcic_socket *so;
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int arg;
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{
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/* XXX this should go to dev/jornada720.c */
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int newval, oldval, s;
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/* XXX this isn't well confirmed. DANGER DANGER */
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switch (arg) {
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case SAPCIC_POWER_OFF:
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newval = 0;
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break;
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case SAPCIC_POWER_3V:
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newval = 2;
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break;
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case SAPCIC_POWER_5V:
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newval = 1;
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break;
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default:
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panic("sacpcic_set_power: bogus arg\n");
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}
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s = splbio();
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oldval = bus_space_read_4(so->sacc_sc->sc_iot, so->sacc_sc->sc_ioh,
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SACCGPIOA_DVR);
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switch (so->socket) {
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case 0:
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newval = newval | (oldval & 0xc);
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break;
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case 1:
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newval = (newval << 2) | (oldval & 3);
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break;
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default:
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splx(s);
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panic("sacpcic_set_power\n");
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}
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bus_space_write_4(so->sacc_sc->sc_iot, so->sacc_sc->sc_ioh,
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SACCGPIOA_DVR, newval);
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splx(s);
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}
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static void
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sacpcic_clear_intr(arg)
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{
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/* sacc_intr_dispatch takes care of intr status */
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}
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static void *
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sacpcic_intr_establish(so, level, ih_fun, ih_arg)
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struct sapcic_socket *so;
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int level;
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int (*ih_fun)(void *);
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void *ih_arg;
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{
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int irq;
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irq = so->socket ? IRQ_S1_READY : IRQ_S0_READY;
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return (sacc_intr_establish((sacc_chipset_tag_t)so->sacc_sc,
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irq, 1, level, ih_fun, ih_arg));
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}
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static void
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sacpcic_intr_disestablish(so, ih)
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struct sapcic_socket *so;
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void *ih;
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{
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}
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@ -0,0 +1,80 @@
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/* $NetBSD: sa11x1_pcicreg.h,v 1.1 2001/03/10 19:01:27 toshii Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Register locations */
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#define SACPCIC_CR 0x1800
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#define SACPCIC_SSR 0x1804
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#define SACPCIC_SR 0x1808
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/* Control register */
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#define CR_S0_RST 0x01 /* 1 = Assert reset */
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#define CR_S1_RST 0x02
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#define CR_S0_FLT 0x04 /* 0 = Float all S0 control lines */
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#define CR_S1_FLT 0x08
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#define CR_S0_PWAITEN 0x10 /* S0_nPWAIT enable */
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#define CR_S1_PWAITEN 0x20
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#define CR_S0_PSE 0x40 /* 0 = 3V card */
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#define CR_S1_PSE 0x80
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/* Sleep state register */
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#define SSR_S0 0x01
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#define SSR_S1 0x02
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/* Status register */
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#define SR_S0_READY 0x0001
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#define SR_S1_READY 0x0002
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#define SR_S0_CARDDETECT 0x0004
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#define SR_S1_CARDDETECT 0x0008
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#define SR_S0_VS1 0x0010
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#define SR_S0_VS2 0x0020
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#define SR_S1_VS1 0x0040
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#define SR_S1_VS2 0x0080
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#define SR_S0_WP 0x0100
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#define SR_S1_WP 0x0200
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#define SR_S0_BVD1 0x0400
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#define SR_S0_BVD2 0x0800
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#define SR_S1_BVD1 0x1000
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#define SR_S1_BVD2 0x2000
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/* IRQ numbers */
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#define IRQ_S0_READY 49
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#define IRQ_S1_READY 50
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#define IRQ_S0_CDVALID 51
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#define IRQ_S1_CDVALID 52
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#define IRQ_S0_BVD1 53
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#define IRQ_S1_BVD1 54
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