Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify comments

Browse Source 
and snprintb() sring.
This commit is contained in:
msaitoh 2017-05-15 04:02:52 +00:00
parent 9b6f7e6e98
commit f10b5b28e5
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sys/arch/x86/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.69 2017/04/14 04:43:47 kamil Exp $ */
/* $NetBSD: cpu.h,v 1.70 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -180,7 +180,7 @@ struct cpu_info {
const struct cpu_functions *ci_func; /* start/stop functions */
struct trapframe *ci_ddb_regs;
u_int ci_cflush_lsize; /* CFLUSH insn line size */
u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
union descriptor *ci_gdt;

6
sys/arch/x86/include/specialreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: specialreg.h,v 1.97 2017/04/22 04:24:25 nonaka Exp $ */
/* $NetBSD: specialreg.h,v 1.98 2017/05/15 04:02:52 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -144,7 +144,7 @@
#define CPUID_PAT 0x00010000 /* Page Attribute Table */
#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
#define CPUID_PN 0x00040000 /* processor serial number */
#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
#define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */
#define CPUID_B20 0x00100000 /* reserved */
#define CPUID_DS 0x00200000 /* Debug Store */
#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
@ -163,7 +163,7 @@
"\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
"\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
"\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
"\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
"\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
"\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"