Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

The 1000baseT CR and SR are overlapped with the 100base-T2 CR and SR. 

Note this in a comment.  Add the 1000baseT CR and SR bits.
This commit is contained in:
thorpej 2001-05-31 03:06:46 +00:00
parent f998b62e15
commit f07f44812d
1 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
sys/dev/mii/mii.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: mii.h,v 1.7 2001/05/15 23:16:40 matt Exp $ */
/* $NetBSD: mii.h,v 1.8 2001/05/31 03:06:46 thorpej Exp $ */
/*
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
@ -147,9 +147,25 @@
#define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */
/* section 32.5.1 and 37.2.6.1 */
/* This is also the 1000baseT control register */
#define MII_100T2CR 0x09 /* 100base-T2 control register */
#define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */
#define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */
#define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */
#define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */
#define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
#define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
/* This is also the 1000baseT status register */
#define MII_100T2SR 0x0a /* 100base-T2 status register */
#define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */
#define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */
#define GTSR_LRS 0x2000 /* local rx status, 1 = ok */
#define GTSR_RRS 0x1000 /* remove rx status, 1 = ok */
#define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
#define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
#define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */
#define GRSR_IDLE_ERR 0x00ff /* IDLE error count */
#define MII_EXTSR 0x0f /* Extended status register */
#define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */