From f02db5d4f6e6eb9b7d25494cee1016302e48a047 Mon Sep 17 00:00:00 2001
From: pk <pk@NetBSD.org>
Date: Sun, 6 Jul 1997 22:23:37 +0000
Subject: [PATCH] Turn off microsparc II compatibility bit in Fujitsu
 turbosparc processors.

---
 sys/arch/sparc/sparc/cache.c |  9 +++++++--
 sys/arch/sparc/sparc/cpu.c   | 11 +++++++++--
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/sys/arch/sparc/sparc/cache.c b/sys/arch/sparc/sparc/cache.c
index a5475e1b7fdf..1369caa0f7c3 100644
--- a/sys/arch/sparc/sparc/cache.c
+++ b/sys/arch/sparc/sparc/cache.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.c,v 1.30 1997/07/06 21:18:28 pk Exp $ */
+/*	$NetBSD: cache.c,v 1.31 1997/07/06 22:23:38 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -252,7 +252,7 @@ cypress_cache_enable()
 void
 turbosparc_cache_enable()
 {
-	int pcr;
+	int pcr, pcf;
 
 	cache_alias_dist = max(
 		CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
@@ -262,6 +262,11 @@ turbosparc_cache_enable()
 	pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	pcr |= (TURBOSPARC_PCR_ICE | TURBOSPARC_PCR_DCE);
 	sta(SRMMU_PCR, ASI_SRMMU, pcr);
+
+	pcf = lda(SRMMU_PCFG, ASI_SRMMU);
+	if (pcf & TURBOSPARC_PCFG_SNP)
+		printf("DVMA coherent ");
+
 	CACHEINFO.c_enabled = 1;
 	printf("cache enabled\n");
 }
diff --git a/sys/arch/sparc/sparc/cpu.c b/sys/arch/sparc/sparc/cpu.c
index 291b194121f1..95a7cc977b6d 100644
--- a/sys/arch/sparc/sparc/cpu.c
+++ b/sys/arch/sparc/sparc/cpu.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.45 1997/07/06 21:18:27 pk Exp $ */
+/*	$NetBSD: cpu.c,v 1.46 1997/07/06 22:23:37 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -879,7 +879,14 @@ void
 turbosparc_hotfix(sc)
 	struct cpu_softc *sc;
 {
-	/* Turn off uS2 emulation bit */
+	int pcf;
+
+	pcf = lda(SRMMU_PCFG, ASI_SRMMU);
+	if (pcf & TURBOSPARC_PCFG_US2) {
+		/* Turn off uS2 emulation bit */
+		pcf &= ~TURBOSPARC_PCFG_US2;
+		sta(SRMMU_PCFG, ASI_SRMMU, pcf);
+	}
 }
 #endif /* SUN4M */