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Split gcscpcib into MI part, and MD pci attachement which is also in

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charge of attaching the MD pcib device.
Will be used by the upcoming evbmips loongson support.
This commit is contained in:
bouyer 2011-08-27 12:47:49 +00:00
parent 93e326680f
commit efd9548b67
5 changed files with 182 additions and 90 deletions
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7
sys/arch/i386/conf/files.i386
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@ -1,4 +1,4 @@
# $NetBSD: files.i386,v 1.360 2011/06/12 03:35:41 rmind Exp $
# $NetBSD: files.i386,v 1.361 2011/08/27 12:47:49 bouyer Exp $
#
# new style config file for i386 architecture
#
@ -213,8 +213,9 @@ file arch/i386/pci/gscpcib.c gscpcib
# AMD Geode CS5535/CS5536 PCI-ISA bridge
device gcscpcib: isabus, sysmon_wdog, gpiobus
attach gcscpcib at pci
file arch/i386/pci/gcscpcib.c gcscpcib
attach gcscpcib at pci with gcscpcib_pci
file arch/i386/pci/gcscpcib_pci.c gcscpcib_pci
file dev/ic/gcscpcib.c gcscpcib
device piixpcib: isabus, bioscall
attach piixpcib at pci

108
sys/arch/i386/pci/gcscpcib_pci.c Normal file
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@ -0,0 +1,108 @@
/* $NetBSD: gcscpcib_pci.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */
/* $OpenBSD: gcscpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */
/*
* Copyright (c) 2008 Yojiro UO <yuo@nui.org>
* Copyright (c) 2007 Marc Balmer <mbalmer@openbsd.org>
* Copyright (c) 2007 Michael Shalayeff
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
* AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
* AMD CS5535/CS5536 series LPC bridge also containing timer, watchdog and GPIO.
* machine-dependent attachement.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gcscpcib_pci.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/gpio.h>
#include <sys/timetc.h>
#include <sys/wdog.h>
#include <sys/bus.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <dev/gpio/gpiovar.h>
#include <dev/sysmon/sysmonvar.h>
#include <dev/ic/gcscpcibreg.h>
#include <dev/ic/gcscpcibvar.h>
#include <machine/cpufunc.h>
#include <x86/pci/pcibvar.h>
struct gcscpcib_pci_softc {
/* we call pcibattach() which assumes softc starts like this: */
struct pcib_softc sc_pcib;
/* MI gcscpcib datas */
struct gcscpcib_softc sc_gcscpcib;
};
static int gcscpcib_pci_match(device_t, cfdata_t, void *);
static void gcscpcib_pci_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(gcscpcib_pci, sizeof(struct gcscpcib_pci_softc),
gcscpcib_pci_match, gcscpcib_pci_attach, NULL, NULL);
static int
gcscpcib_pci_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
return 0;
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_NS_CS5535_ISA:
case PCI_PRODUCT_AMD_CS5536_PCIB:
return 2; /* supersede pcib(4) */
}
return 0;
}
static void
gcscpcib_pci_attach(device_t parent, device_t self, void *aux)
{
struct gcscpcib_pci_softc *sc = device_private(self);
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
sc->sc_pcib.sc_pc = pa->pa_pc;
sc->sc_pcib.sc_tag = pa->pa_tag;
/* Attach the PCI-ISA bridge at first */
pcibattach(parent, self, aux);
/* then attach gcscpcib itself */
gcscpcib_attach(self, &sc->sc_gcscpcib, pa->pa_iot);
}
uint64_t
gcsc_rdmsr(uint msr)
{
return rdmsr(msr);
}
void
gcsc_wrmsr(uint msr, uint64_t v)
{
wrmsr(msr, v);
}

98
sys/arch/i386/pci/gcscpcib.c → sys/dev/ic/gcscpcib.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gcscpcib.c,v 1.8 2009/09/27 18:31:58 jakllsch Exp $ */
/* $NetBSD: gcscpcib.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */
/* $OpenBSD: gcscpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */
/*
@ -24,7 +24,7 @@
* AMD CS5535/CS5536 series LPC bridge also containing timer, watchdog and GPIO.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gcscpcib.c,v 1.8 2009/09/27 18:31:58 jakllsch Exp $");
__KERNEL_RCSID(0, "$NetBSD: gcscpcib.c,v 1.1 2011/08/27 12:47:49 bouyer Exp $");
#include "gpio.h"
@ -37,19 +37,13 @@ __KERNEL_RCSID(0, "$NetBSD: gcscpcib.c,v 1.8 2009/09/27 18:31:58 jakllsch Exp $"
#include <sys/wdog.h>
#include <sys/bus.h>
#include <machine/cpufunc.h>
#if NGPIO > 0
#include <dev/gpio/gpiovar.h>
#endif
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <dev/sysmon/sysmonvar.h>
#include <arch/i386/pci/gcscpcibreg.h>
#include <arch/x86/pci/pcibvar.h>
#include <dev/ic/gcscpcibreg.h>
#include <dev/ic/gcscpcibvar.h>
/* define if you need to select MFGPT for watchdog manually (0-5). */
/* #define AMD553X_WDT_FORCEUSEMFGPT 0 */
@ -65,52 +59,14 @@ __KERNEL_RCSID(0, "$NetBSD: gcscpcib.c,v 1.8 2009/09/27 18:31:58 jakllsch Exp $"
/* 1 bit replace (not support multiple bit)*/
#define AMD553X_MFGPTx_NR_DISABLE(x, bit) \
( wrmsr(AMD553X_MFGPT_NR, rdmsr(AMD553X_MFGPT_NR) & ~((bit) << (x))) )
( gcsc_wrmsr(AMD553X_MFGPT_NR, gcsc_rdmsr(AMD553X_MFGPT_NR) & ~((bit) << (x))) )
#define AMD553X_MFGPTx_NR_ENABLE(x, bit) \
( wrmsr(AMD553X_MFGPT_NR, rdmsr(AMD553X_MFGPT_NR) | ((bit) << (x))) )
( gcsc_wrmsr(AMD553X_MFGPT_NR, gcsc_rdmsr(AMD553X_MFGPT_NR) | ((bit) << (x))) )
/* caliculate watchdog timer setting */
#define AMD553X_WDT_TICK (1<<(AMD553X_MFGPT_DIV_32K - AMD553X_MFGPT_PRESCALE))
#define AMD553X_WDT_COUNTMAX (0xffff / AMD553X_WDT_TICK)
struct gcscpcib_softc {
/* we call pcibattach() which assumes softc starts like this: */
struct pcib_softc sc_pcib;
pcireg_t sc_pirqrc;
struct timecounter sc_timecounter;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
/* Watchdog Timer */
struct sysmon_wdog sc_smw;
int sc_wdt_mfgpt;
#if NGPIO > 0
/* GPIO interface */
bus_space_tag_t sc_gpio_iot;
bus_space_handle_t sc_gpio_ioh;
struct gpio_chipset_tag sc_gpio_gc;
gpio_pin_t sc_gpio_pins[AMD553X_GPIO_NPINS];
#endif
/* SMbus/i2c interface */
#if 0
bus_space_tag_t sc_smbus_iot;
bus_space_handle_t sc_smbus_ioh;
i2c_addr_t sc_smbus_slaveaddr; /* address of smbus slave */
struct i2c_controller sc_i2c; /* i2c controller info */
krwlock_t sc_smbus_rwlock;
#endif
};
static int gcscpcib_match(device_t, cfdata_t, void *);
static void gcscpcib_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(gcscpcib, sizeof(struct gcscpcib_softc),
gcscpcib_match, gcscpcib_attach, NULL, NULL);
static u_int gcscpcib_get_timecount(struct timecounter *tc);
static int gscspcib_scan_mfgpt(struct gcscpcib_softc *sc);
static void gscspcib_wdog_update(struct gcscpcib_softc *, uint16_t);
@ -126,29 +82,10 @@ static void gcscpcib_gpio_pin_write(void *, int, int);
static void gcscpcib_gpio_pin_ctl(void *, int, int);
#endif
static int
gcscpcib_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
return 0;
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_NS_CS5535_ISA:
case PCI_PRODUCT_AMD_CS5536_PCIB:
return 2; /* supersede pcib(4) */
}
return 0;
}
static void
gcscpcib_attach(device_t parent, device_t self, void *aux)
void
gcscpcib_attach(device_t self, struct gcscpcib_softc *sc,
bus_space_tag_t iot)
{
struct gcscpcib_softc *sc = device_private(self);
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
struct timecounter *tc = &sc->sc_timecounter;
bus_addr_t wdtbase;
int wdt = 0;
@ -158,16 +95,11 @@ gcscpcib_attach(device_t parent, device_t self, void *aux)
int i, gpio;
#endif
sc->sc_pcib.sc_pc = pa->pa_pc;
sc->sc_pcib.sc_tag = pa->pa_tag;
sc->sc_iot = pa->pa_iot;
sc->sc_iot = iot;
#if NGPIO > 0
sc->sc_gpio_iot = pa->pa_iot;
sc->sc_gpio_iot = iot;
#endif
/* Attach the PCI-ISA bridge at first */
pcibattach(parent, self, aux);
/* Attach the CS553[56] timer */
tc->tc_get_timecount = gcscpcib_get_timecount;
tc->tc_counter_mask = 0xffffffff;
@ -178,7 +110,7 @@ gcscpcib_attach(device_t parent, device_t self, void *aux)
tc_init(tc);
/* Attach the watchdog timer */
wdtbase = rdmsr(MSR_LBAR_MFGPT) & 0xffff;
wdtbase = gcsc_rdmsr(MSR_LBAR_MFGPT) & 0xffff;
if (bus_space_map(sc->sc_iot, wdtbase, 64, 0, &sc->sc_ioh)) {
aprint_error_dev(self, "can't map memory space for WDT\n");
} else {
@ -215,7 +147,7 @@ gcscpcib_attach(device_t parent, device_t self, void *aux)
gpio:
#if NGPIO > 0
/* map GPIO I/O space */
gpiobase = rdmsr(MSR_LBAR_GPIO) & 0xffff;
gpiobase = gcsc_rdmsr(MSR_LBAR_GPIO) & 0xffff;
if (!bus_space_map(sc->sc_gpio_iot, gpiobase, 0xff, 0,
&sc->sc_gpio_ioh)) {
aprint_normal(", GPIO");
@ -265,7 +197,7 @@ gpio:
static u_int
gcscpcib_get_timecount(struct timecounter *tc)
{
return rdmsr(AMD553X_TMC);
return gcsc_rdmsr(AMD553X_TMC);
}
/* Watchdog timer support functions */
@ -330,7 +262,7 @@ gscspcib_wdog_update(struct gcscpcib_softc *sc, uint16_t count)
__func__, sc->sc_wdt_mfgpt, cnt,
bus_space_read_2(sc->sc_iot, sc->sc_ioh,
AMD553X_MFGPTX_CNT(sc->sc_wdt_mfgpt)), count,
(uint32_t)(rdmsr(AMD553X_MFGPT_NR))));
(uint32_t)(gcsc_rdmsr(AMD553X_MFGPT_NR))));
}
static void

8
sys/arch/i386/pci/gcscpcibreg.h → sys/dev/ic/gcscpcibreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: gcscpcibreg.h,v 1.1 2008/01/09 14:23:47 xtraeme Exp $ */
/* $NetBSD: gcscpcibreg.h,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */
/* $OpenBSD: glxpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */
/*
@ -23,8 +23,8 @@
* Register definitions for the AMD CS5535/CS5536 Companion Device.
*/
#ifndef _I386_PCI_GCSCPCIBREG_H_
#define _I386_PCI_GCSCPCIBREG_H_
#ifndef _IC_GCSCPCIBREG_H_
#define _IC_GCSCPCIBREG_H_
#define AMD553X_REV 0x51400017
#define AMD553X_REV_MASK 0xff
@ -138,4 +138,4 @@
#define AMD553X_GPIO_IN_NE_STS 0x48 /* input negative edge status */
#define AMD553X_GPIO_IN_PE_STS 0x4c /* input positive edge status */
#endif /* _I386_PCI_GCSCPCIBREG_H_ */
#endif /* _IC_GCSCPCIBREG_H_ */

51
sys/dev/ic/gcscpcibvar.h Normal file
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@ -0,0 +1,51 @@
/* $NetBSD: gcscpcibvar.h,v 1.1 2011/08/27 12:47:49 bouyer Exp $ */
/* $OpenBSD: gcscpcib.c,v 1.6 2007/11/17 17:02:47 mbalmer Exp $ */
/*
* Copyright (c) 2008 Yojiro UO <yuo@nui.org>
* Copyright (c) 2007 Marc Balmer <mbalmer@openbsd.org>
* Copyright (c) 2007 Michael Shalayeff
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
* AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
struct gcscpcib_softc {
struct timecounter sc_timecounter;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
/* Watchdog Timer */
struct sysmon_wdog sc_smw;
int sc_wdt_mfgpt;
/* GPIO interface */
bus_space_tag_t sc_gpio_iot;
bus_space_handle_t sc_gpio_ioh;
struct gpio_chipset_tag sc_gpio_gc;
gpio_pin_t sc_gpio_pins[AMD553X_GPIO_NPINS];
#if 0
/* SMbus/i2c interface */
bus_space_tag_t sc_smbus_iot;
bus_space_handle_t sc_smbus_ioh;
i2c_addr_t sc_smbus_slaveaddr; /* address of smbus slave */
struct i2c_controller sc_i2c; /* i2c controller info */
krwlock_t sc_smbus_rwlock;
#endif
};
void gcscpcib_attach(device_t, struct gcscpcib_softc *, bus_space_tag_t);
uint64_t gcsc_rdmsr(uint);
void gcsc_wrmsr(uint, uint64_t);