fix a few KNF nits ..
This commit is contained in:
mrg
parent
30c351dc59
commit
efb227d3a7
@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.38 1999/05/27 09:45:50 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.39 1999/06/08 10:38:15 mrg Exp $ */
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/*
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* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
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@ -92,20 +92,21 @@ int wdcdebug_pciide_mask = 0;
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/* inlines for reading/writing 8-bit PCI registers */
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static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t,
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int));
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int));
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static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t,
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int, u_int8_t));
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static __inline u_int8_t
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pciide_pci_read(pc, pa, reg)
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pci_chipset_tag_t pc;
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pcitag_t pa;
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int reg;
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{
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return (
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pci_conf_read(pc, pa, (reg & ~0x03)) >> ((reg & 0x03) * 8) & 0xff);
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return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
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((reg & 0x03) * 8) & 0xff);
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}
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static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t,
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int, u_int8_t));
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static __inline void
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pciide_pci_write(pc, pa, reg, val)
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pci_chipset_tag_t pc;
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@ -199,194 +200,193 @@ int pciide_dma_finish __P((void*, int, int, int));
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void pciide_print_modes __P((struct pciide_channel *));
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struct pciide_product_desc {
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u_int32_t ide_product;
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int ide_flags;
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int ide_num_channels;
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const char *ide_name;
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/* init controller's capabilities for drives probe */
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void (*setup_cap) __P((struct pciide_softc*));
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/* init controller after drives probe */
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void (*setup_chip) __P((struct pciide_softc*));
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/* map channel if possible/necessary */
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void (*channel_map) __P((struct pci_attach_args *,
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u_int32_t ide_product;
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int ide_flags;
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int ide_num_channels;
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const char *ide_name;
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/* init controller's capabilities for drives probe */
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void (*setup_cap) __P((struct pciide_softc*));
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/* init controller after drives probe */
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void (*setup_chip) __P((struct pciide_softc*));
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/* map channel if possible/necessary */
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void (*channel_map) __P((struct pci_attach_args *,
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struct pciide_channel *));
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};
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/* Flags for ide_flags */
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#define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */
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#define ONE_QUEUE 0x02 /* device need serialised access */
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#define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */
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#define ONE_QUEUE 0x02 /* device need serialised access */
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/* Default product description for devices not known from this controller */
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const struct pciide_product_desc default_product_desc = {
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0,
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0,
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PCIIDE_NUM_CHANNELS,
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"Generic PCI IDE controller",
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default_setup_cap,
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default_setup_chip,
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default_channel_map
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0,
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0,
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PCIIDE_NUM_CHANNELS,
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"Generic PCI IDE controller",
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default_setup_cap,
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default_setup_chip,
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default_channel_map
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};
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const struct pciide_product_desc pciide_intel_products[] = {
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{ PCI_PRODUCT_INTEL_82092AA,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82092AA IDE controller",
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default_setup_cap,
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default_setup_chip,
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default_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371FB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371FB IDE controller (PIIX)",
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piix_setup_cap,
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piix_setup_chip,
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piix_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371SB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371SB IDE Interface (PIIX3)",
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piix_setup_cap,
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piix3_4_setup_chip,
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piix_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371AB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371AB IDE controller (PIIX4)",
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piix_setup_cap,
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piix3_4_setup_chip,
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piix_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_INTEL_82092AA,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82092AA IDE controller",
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default_setup_cap,
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default_setup_chip,
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default_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371FB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371FB IDE controller (PIIX)",
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piix_setup_cap,
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piix_setup_chip,
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piix_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371SB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371SB IDE Interface (PIIX3)",
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piix_setup_cap,
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piix3_4_setup_chip,
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piix_channel_map
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},
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{ PCI_PRODUCT_INTEL_82371AB_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Intel 82371AB IDE controller (PIIX4)",
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piix_setup_cap,
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piix3_4_setup_chip,
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piix_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_cmd_products[] = {
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{ PCI_PRODUCT_CMDTECH_640,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0640",
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default_setup_cap,
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default_setup_chip,
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cmd_channel_map
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},
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{ PCI_PRODUCT_CMDTECH_643,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0643",
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cmd0643_6_setup_cap,
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cmd0643_6_setup_chip,
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cmd_channel_map
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},
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{ PCI_PRODUCT_CMDTECH_646,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0646",
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cmd0643_6_setup_cap,
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cmd0643_6_setup_chip,
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cmd_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_CMDTECH_640,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0640",
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default_setup_cap,
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default_setup_chip,
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cmd_channel_map
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},
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{ PCI_PRODUCT_CMDTECH_643,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0643",
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cmd0643_6_setup_cap,
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cmd0643_6_setup_chip,
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cmd_channel_map
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},
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{ PCI_PRODUCT_CMDTECH_646,
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ONE_QUEUE | CMD_PCI064x_IOEN,
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PCIIDE_NUM_CHANNELS,
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"CMD Technology PCI0646",
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cmd0643_6_setup_cap,
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cmd0643_6_setup_chip,
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cmd_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_via_products[] = {
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{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"VIA Technologies VT82C586 (Apollo VP) IDE Controller",
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apollo_setup_cap,
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apollo_setup_chip,
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apollo_channel_map
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},
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{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"VIA Technologies VT82C586A IDE Controller",
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apollo_setup_cap,
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apollo_setup_chip,
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apollo_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"VIA Technologies VT82C586 (Apollo VP) IDE Controller",
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apollo_setup_cap,
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apollo_setup_chip,
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apollo_channel_map
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},
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{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"VIA Technologies VT82C586A IDE Controller",
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apollo_setup_cap,
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apollo_setup_chip,
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apollo_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_cypress_products[] = {
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{ PCI_PRODUCT_CONTAQ_82C693,
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0,
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1,
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"Contaq Microsystems CY82C693 IDE Controller",
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cy693_setup_cap,
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cy693_setup_chip,
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cy693_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_CONTAQ_82C693,
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0,
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1,
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"Contaq Microsystems CY82C693 IDE Controller",
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cy693_setup_cap,
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cy693_setup_chip,
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cy693_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_sis_products[] = {
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{ PCI_PRODUCT_SIS_5597_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Silicon Integrated System 5597/5598 IDE controller",
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sis_setup_cap,
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sis_setup_chip,
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sis_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_SIS_5597_IDE,
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0,
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PCIIDE_NUM_CHANNELS,
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"Silicon Integrated System 5597/5598 IDE controller",
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sis_setup_cap,
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sis_setup_chip,
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sis_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_acer_products[] = {
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{ PCI_PRODUCT_ALI_M5229,
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0,
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PCIIDE_NUM_CHANNELS,
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"Acer Labs M5229 UDMA IDE Controller",
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acer_setup_cap,
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acer_setup_chip,
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acer_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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{ PCI_PRODUCT_ALI_M5229,
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0,
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PCIIDE_NUM_CHANNELS,
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"Acer Labs M5229 UDMA IDE Controller",
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acer_setup_cap,
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acer_setup_chip,
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acer_channel_map
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},
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{ 0,
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0,
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0,
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NULL,
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}
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};
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struct pciide_vendor_desc {
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u_int32_t ide_vendor;
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const struct pciide_product_desc *ide_products;
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u_int32_t ide_vendor;
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const struct pciide_product_desc *ide_products;
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};
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const struct pciide_vendor_desc pciide_vendors[] = {
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{ PCI_VENDOR_INTEL, pciide_intel_products },
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{ PCI_VENDOR_CMDTECH, pciide_cmd_products },
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{ PCI_VENDOR_VIATECH, pciide_via_products },
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{ PCI_VENDOR_CONTAQ, pciide_cypress_products },
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{ PCI_VENDOR_SIS, pciide_sis_products },
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{ PCI_VENDOR_ALI, pciide_acer_products },
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{ 0, NULL }
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{ PCI_VENDOR_INTEL, pciide_intel_products },
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{ PCI_VENDOR_CMDTECH, pciide_cmd_products },
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{ PCI_VENDOR_VIATECH, pciide_via_products },
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{ PCI_VENDOR_CONTAQ, pciide_cypress_products },
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{ PCI_VENDOR_SIS, pciide_sis_products },
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{ PCI_VENDOR_ALI, pciide_acer_products },
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{ 0, NULL }
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};
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#define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary")
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/* options passed via the 'flags' config keyword */
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@ -413,27 +413,27 @@ int pciide_compat_intr __P((void *));
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int pciide_pci_intr __P((void *));
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const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t));
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const struct pciide_product_desc*
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const struct pciide_product_desc *
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pciide_lookup_product(id)
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u_int32_t id;
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u_int32_t id;
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{
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const struct pciide_product_desc *pp;
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const struct pciide_vendor_desc *vp;
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const struct pciide_product_desc *pp;
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const struct pciide_vendor_desc *vp;
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for (vp = pciide_vendors; vp->ide_products != NULL; vp++)
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if (PCI_VENDOR(id) == vp->ide_vendor)
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break;
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for (vp = pciide_vendors; vp->ide_products != NULL; vp++)
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if (PCI_VENDOR(id) == vp->ide_vendor)
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break;
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if ((pp = vp->ide_products) == NULL)
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return NULL;
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if ((pp = vp->ide_products) == NULL)
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return NULL;
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for (; pp->ide_name != NULL; pp++)
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if (PCI_PRODUCT(id) == pp->ide_product)
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break;
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for (; pp->ide_name != NULL; pp++)
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if (PCI_PRODUCT(id) == pp->ide_product)
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break;
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if (pp->ide_name == NULL)
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return NULL;
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return pp;
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if (pp->ide_name == NULL)
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return NULL;
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return pp;
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}
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int
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@ -522,7 +522,7 @@ pciide_attach(parent, self, aux)
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* could be mapped.
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*
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* XXX Note that despite the fact that the Bus Master IDE specs
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* XXX say that "The bus master IDE functoin uses 16 bytes of IO
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* XXX say that "The bus master IDE function uses 16 bytes of IO
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* XXX space," some controllers (at least the United
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* XXX Microelectronics UM8886BF) place it in memory space.
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* XXX eventually, we should probably read the register and check
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@ -1781,6 +1781,7 @@ void
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cmd0643_6_setup_cap(sc)
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struct pciide_softc *sc;
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{
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE |
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WDC_CAPABILITY_DMA;
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sc->sc_wdcdev.PIO_cap = 4;
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@ -1861,6 +1862,7 @@ void
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cy693_setup_cap(sc)
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struct pciide_softc *sc;
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{
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE |
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WDC_CAPABILITY_DMA;
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sc->sc_wdcdev.PIO_cap = 4;
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@ -1872,6 +1874,7 @@ void
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cy693_setup_chip(sc)
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struct pciide_softc *sc;
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{
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WDCDEBUG_PRINT(("cy693_setup_chip: old timings reg 0x%x\n",
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pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),
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DEBUG_PROBE);
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@ -1987,6 +1990,7 @@ void
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sis_setup_cap(sc)
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struct pciide_softc *sc;
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{
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE |
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WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.PIO_cap = 4;
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@ -2112,6 +2116,7 @@ void
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acer_setup_cap(sc)
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struct pciide_softc *sc;
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{
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE |
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WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
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sc->sc_wdcdev.PIO_cap = 4;
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