Increase receive ring to 128 entries and handle both endian devices.
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eeh
parent
0fcb9b7701
commit
ef420318e0
@ -1,4 +1,4 @@
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/* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
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/* $NetBSD: gem.c,v 1.2 2001/10/01 23:39:57 eeh Exp $ */
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/*
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*
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@ -224,7 +224,6 @@ gem_config(sc)
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* before this point releases all resources that may have been
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* allocated.
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*/
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sc->sc_flags |= GEMF_ATTACHED;
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/* Announce ourselves. */
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printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
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@ -1075,7 +1074,7 @@ bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK));
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* to do it.
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*/
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sc->sc_txdescs[nexttx].gd_addr =
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htole64(dmamap->dm_segs[seg].ds_addr);
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GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr);
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flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE;
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if (nexttx == firsttx) {
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flags |= GEM_TD_START_OF_PACKET;
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@ -1084,7 +1083,7 @@ bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK));
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flags |= GEM_TD_END_OF_PACKET;
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}
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sc->sc_txdescs[nexttx].gd_flags =
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htole64(flags);
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GEM_DMA_WRITE(sc, flags);
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lasttx = nexttx;
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}
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@ -1094,9 +1093,9 @@ bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK));
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for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) {
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printf("descriptor %d:\t", seg);
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printf("gd_flags: 0x%016llx\t", (long long)
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le64toh(sc->sc_txdescs[seg].gd_flags));
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GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags));
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printf("gd_addr: 0x%016llx\n", (long long)
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le64toh(sc->sc_txdescs[seg].gd_addr));
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GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr));
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if (seg == lasttx)
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break;
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}
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@ -1143,15 +1142,6 @@ bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK));
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if (sc->sc_txfree != ofree) {
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DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
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sc->sc_dev.dv_xname, lasttx, firsttx));
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#if 0
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/*
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* Cause a transmit interrupt to happen on the
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* last packet we enqueued.
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*/
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sc->sc_txdescs[lasttx].gd_flags |= htole64(GEM_TD_INTERRUPT_ME);
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GEM_CDTXSYNC(sc, lasttx, 1,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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#endif
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/*
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* The entire packet chain is set up.
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* Kick the transmitter.
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@ -1168,8 +1158,8 @@ if (gem_opdebug) {
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(long long)bus_space_read_8(sc->sc_bustag, sc->sc_h, GEM_TX_RING_PTR));
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printf("descriptor %d: ", (i = lasttx));
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printf("gd_flags: 0x%016llx\t", (long long)
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le64toh(sc->sc_txdescs[i].gd_flags));
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pa = le64toh(sc->sc_txdescs[i].gd_addr);
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GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
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pa = GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr);
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printf("gd_addr: 0x%016llx\n", (long long) pa);
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printf("GEM_TX_CONFIG %x GEM_MAC_XIF_CONFIG %x GEM_MAC_TX_CONFIG %x\n",
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bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
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@ -1202,8 +1192,7 @@ gem_tint(sc)
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int txlast;
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DPRINTF(sc, ("%s: gem_tint: sc_flags 0x%08x\n",
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sc->sc_dev.dv_xname, sc->sc_flags));
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DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname));
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/*
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* Unload collision counters
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@ -1238,9 +1227,9 @@ gem_tint(sc)
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for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
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printf("descriptor %d: ", i);
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printf("gd_flags: 0x%016llx\t", (long long)
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le64toh(sc->sc_txdescs[i].gd_flags));
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GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
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printf("gd_addr: 0x%016llx\n", (long long)
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le64toh(sc->sc_txdescs[i].gd_addr));
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GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
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if (i == txs->txs_lastdesc)
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break;
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}
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@ -1326,8 +1315,7 @@ gem_rint(sc)
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u_int64_t rxstat;
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int i, len;
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DPRINTF(sc, ("%s: gem_rint: sc_flags 0x%08x\n",
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sc->sc_dev.dv_xname, sc->sc_flags));
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DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname));
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/*
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* XXXX Read the lastrx only once at the top for speed.
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*/
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@ -1340,7 +1328,7 @@ gem_rint(sc)
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GEM_CDRXSYNC(sc, i,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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rxstat = le64toh(sc->sc_rxdescs[i].gd_flags);
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rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
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if (rxstat & GEM_RD_OWN) {
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printf("gem_rint: completed descriptor "
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@ -1364,9 +1352,9 @@ gem_rint(sc)
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if (ifp->if_flags & IFF_DEBUG) {
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printf(" rxsoft %p descriptor %d: ", rxs, i);
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printf("gd_flags: 0x%016llx\t", (long long)
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le64toh(sc->sc_rxdescs[i].gd_flags));
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GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
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printf("gd_addr: 0x%016llx\n", (long long)
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le64toh(sc->sc_rxdescs[i].gd_addr));
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GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
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}
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#endif
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@ -1376,12 +1364,6 @@ gem_rint(sc)
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*/
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len = GEM_RD_BUFLEN(rxstat);
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/*
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* We align the mbuf data in gem_add_rxbuf() so
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* we can use __NO_STRICT_ALIGNMENT here
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*/
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#define __NO_STRICT_ALIGNMENT
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#ifdef __NO_STRICT_ALIGNMENT
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/*
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* Allocate a new mbuf cluster. If that fails, we are
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* out of memory, and must drop the packet and recycle
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@ -1396,42 +1378,6 @@ gem_rint(sc)
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continue;
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}
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m->m_data += 2; /* We're already off by two */
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#else
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/*
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* The Gem's receive buffers must be 4-byte aligned.
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* But this means that the data after the Ethernet header
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* is misaligned. We must allocate a new buffer and
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* copy the data, shifted forward 2 bytes.
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*/
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MGETHDR(m, M_DONTWAIT, MT_DATA);
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if (m == NULL) {
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dropit:
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ifp->if_ierrors++;
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GEM_INIT_RXDESC(sc, i);
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bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
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rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
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continue;
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}
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if (len > (MHLEN - 2)) {
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MCLGET(m, M_DONTWAIT);
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if ((m->m_flags & M_EXT) == 0) {
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m_freem(m);
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goto dropit;
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}
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}
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m->m_data += 2;
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/*
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* Note that we use clusters for incoming frames, so the
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* buffer is virtually contiguous.
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*/
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memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len);
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/* Allow the receive descriptor to continue using its mbuf. */
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GEM_INIT_RXDESC(sc, i);
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bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
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rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
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#endif /* __NO_STRICT_ALIGNMENT */
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ifp->if_ipackets++;
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eh = mtod(m, struct ether_header *);
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@ -1576,8 +1522,8 @@ if (gem_opdebug && (status & GEM_INTR_TX_DONE)) {
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(long long)bus_space_read_8(t, seb, GEM_TX_RING_PTR));
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printf("descriptor %d: ", --i);
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printf("gd_flags: 0x%016llx\t", (long long)
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le64toh(sc->sc_txdescs[i].gd_flags));
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pa = le64toh(sc->sc_txdescs[i].gd_addr);
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GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
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pa = GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr);
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printf("gd_addr: 0x%016llx\n", (long long) pa);
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printf("GEM_TX_CONFIG %x GEM_MAC_XIF_CONFIG %x GEM_MAC_TX_CONFIG %x "
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"GEM_MAC_TX_STATUS %x\n",
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@ -1629,7 +1575,6 @@ gem_watchdog(ifp)
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++ifp->if_oerrors;
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/* Try to get more packets going. */
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// gem_reset(sc);
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gem_start(ifp);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: gemvar.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
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/* $NetBSD: gemvar.h,v 1.2 2001/10/01 23:39:57 eeh Exp $ */
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/*
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*
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@ -62,7 +62,7 @@
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* Receive descriptor list size. We have one Rx buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define GEM_NRXDESC 64
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#define GEM_NRXDESC 128
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#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
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#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
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@ -201,7 +201,6 @@ struct gem_softc {
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/* ========== */
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int sc_inited;
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int sc_flags;
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int sc_debug;
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void *sc_sh; /* shutdownhook cookie */
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u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */
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@ -215,24 +214,9 @@ struct gem_softc {
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#endif
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};
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/* sc_flags */
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#define GEMF_WANT_SETUP 0x00000001 /* want filter setup */
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#define GEMF_DOING_SETUP 0x00000002 /* doing multicast setup */
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#define GEMF_HAS_MII 0x00000004 /* has media on MII */
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#define GEMF_IC_FS 0x00000008 /* IC bit on first tx seg */
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#define GEMF_MRL 0x00000010 /* memory read line okay */
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#define GEMF_MRM 0x00000020 /* memory read multi okay */
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#define GEMF_MWI 0x00000040 /* memory write inval okay */
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#define GEMF_AUTOPOLL 0x00000080 /* chip supports auto-poll */
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#define GEMF_LINK_UP 0x00000100 /* link is up (non-MII) */
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#define GEMF_LINK_VALID 0x00000200 /* link state valid */
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#define GEMF_DOINGAUTO 0x00000400 /* doing autoneg (non-MII) */
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#define GEMF_ATTACHED 0x00000800 /* attach has succeeded */
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#define GEMF_ENABLED 0x00001000 /* chip is enabled */
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#define GEMF_BLE 0x00002000 /* data is big endian */
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#define GEMF_DBO 0x00004000 /* descriptor is big endian */
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#define GEM_IS_ENABLED(sc) ((sc)->sc_flags & GEMF_ENABLED)
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#define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v))
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#define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v))
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/*
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* This macro returns the current media entry for *non-MII* media.
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@ -291,10 +275,11 @@ do { \
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\
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__m->m_data = __m->m_ext.ext_buf; \
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__rxd->gd_addr = \
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htole64(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
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GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \
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__rxd->gd_flags = \
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htole64((((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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GEM_DMA_WRITE((sc), \
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(((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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