Add hardware checksumming support.
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rjs
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40b201d5b9
commit
eebfc9ef1e
@ -1,4 +1,4 @@
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/* $NetBSD: cemacreg.h,v 1.2 2015/08/13 14:51:35 rjs Exp $ */
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/* $NetBSD: cemacreg.h,v 1.3 2015/08/24 18:51:37 rjs Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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@ -164,6 +164,7 @@
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#define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK)
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#define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK)
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#define GEM_CFG_DBW __BITS(22, 21)
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#define GEM_CFG_RX_CHKSUM_OFFLD_EN __BIT(24)
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/* Status Register bits: */
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#define ETH_SR_IDLE 0x0004U /* 1 = PHY logic is running */
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@ -244,30 +245,36 @@ typedef struct eth_dsc {
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#define ETH_RDSC_F_USED 0x00000001U
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/* frame info bits: */
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#define ETH_RDSC_I_BCAST 0x80000000U
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#define ETH_RDSC_I_MULTICAST 0x40000000U
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#define ETH_RDSC_I_UNICAST 0x20000000U
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#define ETH_RDSC_I_BCAST __BIT(31)
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#define ETH_RDSC_I_MULTICAST __BIT(30)
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#define ETH_RDSC_I_UNICAST __BIT(29)
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#define ETH_RDSC_I_VLAN 0x10000000U
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#define ETH_RDSC_I_UNKNOWN_SRC 0x08000000U
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#define ETH_RDSC_I_MATCH1 0x04000000U
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#define ETH_RDSC_I_MATCH2 0x02000000U
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#define ETH_RDSC_I_MATCH3 0x01000000U
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#define ETH_RDSC_I_MATCH4 0x00800000U
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#define ETH_RDSC_I_LEN 0x000007FFU
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#define ETH_RDSC_I_CHKSUM __BITS(23, 22)
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#define ETH_RDSC_I_CHKSUM_NONE __SHIFTIN(0, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_IP __SHIFTIN(1, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_TCP __SHIFTIN(2, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_UDP __SHIFTIN(3, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_LEN __BITS(13, 0)
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#define ETH_TDSC_I_USED __BIT(31) /* done transmitting */
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#define ETH_TDSC_I_WRAP __BIT(30) /* end of descr ring */
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#define ETH_TDSC_I_RETRY_ERR __BIT(29)
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#define ETH_TDSC_I_AHB_ERR __BIT(27)
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#define ETH_TDSC_I_LATE_COLL __BIT(26)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_MASK __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_VLAN_HDR_ERR __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_SNAP_HDR_ERR __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_IP_HDR_ERR __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_UNKNOWN_TYPE __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_UNSUPP_FRAG __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_NOT_TCPUDP __BIT(20)
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#define ETH_TDSC_I_CKSUM_GEN_STAT_SHORT_PKT __BIT(20)
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#define ETH_TDSC_I_CHKSUM __BITS(22, 20)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_NO_ERR __SHIFTIN(0, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_VLAN_HDR_ERR __SHIFTIN(1, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_SNAP_HDR_ERR __SHIFTIN(2, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_IP_HDR_ERR __SHIFTIN(3, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNKNOWN_TYPE __SHIFTIN(4, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNSUPP_FRAG __SHIFTIN(5, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_NOT_TCPUDP __SHIFTIN(6, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_SHORT_PKT __SHIFTIN(7, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_NO_CRC_APPENDED __BIT(16)
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#define ETH_TDSC_I_LAST_BUF __BIT(15) /* last buf in frame */
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#define ETH_TDSC_I_LEN __BITS(13, 0)
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@ -1,4 +1,4 @@
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/* $NetBSD: if_cemac.c,v 1.6 2015/08/24 18:40:57 rjs Exp $ */
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/* $NetBSD: if_cemac.c,v 1.7 2015/08/24 18:51:37 rjs Exp $ */
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/*
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.6 2015/08/24 18:40:57 rjs Exp $");
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__KERNEL_RCSID(0, "$NetBSD: if_cemac.c,v 1.7 2015/08/24 18:51:37 rjs Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -322,7 +322,7 @@ cemac_intr(void *arg)
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uint32_t nfo;
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DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Info));
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while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) {
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int fl;
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int fl, csum;
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struct mbuf *m;
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nfo = sc->RDSC[bi].Info;
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@ -339,6 +339,23 @@ cemac_intr(void *arg)
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sc->rxq[bi].m->m_pkthdr.rcvif = ifp;
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sc->rxq[bi].m->m_pkthdr.len =
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sc->rxq[bi].m->m_len = fl;
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switch (nfo & ETH_RDSC_I_CHKSUM) {
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case ETH_RDSC_I_CHKSUM_IP:
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csum = M_CSUM_IPv4;
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break;
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case ETH_RDSC_I_CHKSUM_UDP:
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csum = M_CSUM_IPv4 | M_CSUM_UDPv4 |
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M_CSUM_UDPv6;
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break;
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case ETH_RDSC_I_CHKSUM_TCP:
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csum = M_CSUM_IPv4 | M_CSUM_TCPv4 |
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M_CSUM_TCPv6;
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break;
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default:
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csum = 0;
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break;
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}
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sc->rxq[bi].m->m_pkthdr.csum_flags = csum;
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bpf_mtap(ifp, sc->rxq[bi].m);
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DPRINTFN(2,("received %u bytes packet\n", fl));
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(*ifp->if_input)(ifp, sc->rxq[bi].m);
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@ -578,6 +595,16 @@ cemac_init(struct cemac_softc *sc)
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CEMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
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| ETH_CTL_CSR | ETH_CTL_MPE);
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#endif
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/*
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* We can support hardware checksumming.
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*/
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ifp->if_capabilities |=
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IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
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IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
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IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
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IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
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IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
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/*
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* We can support 802.1Q VLAN-sized frames.
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*/
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@ -726,10 +753,16 @@ cemac_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
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break;
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default:
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error = ether_ioctl(ifp, cmd, data);
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if (error == ENETRESET) {
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if (ifp->if_flags & IFF_RUNNING)
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cemac_setaddr(ifp);
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error = 0;
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if (error != ENETRESET)
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break;
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error = 0;
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if (cmd == SIOCSIFCAP) {
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error = (*ifp->if_init)(ifp);
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} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
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;
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else if (ifp->if_flags & IFF_RUNNING) {
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cemac_setaddr(ifp);
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}
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}
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splx(s);
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@ -856,10 +889,31 @@ static int
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cemac_ifinit(struct ifnet *ifp)
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{
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struct cemac_softc *sc = ifp->if_softc;
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uint32_t dma, cfg;
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int s = splnet();
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callout_stop(&sc->cemac_tick_ch);
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if (ISSET(sc->cemac_flags, CEMAC_FLAG_GEM)) {
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if (ifp->if_capenable &
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(IFCAP_CSUM_IPv4_Tx |
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IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx |
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IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) {
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dma = CEMAC_READ(GEM_DMA_CFG);
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dma |= GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN;
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CEMAC_WRITE(GEM_DMA_CFG, dma);
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}
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if (ifp->if_capenable &
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(IFCAP_CSUM_IPv4_Rx |
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IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
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IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
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cfg = CEMAC_READ(ETH_CFG);
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cfg |= GEM_CFG_RX_CHKSUM_OFFLD_EN;
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CEMAC_WRITE(ETH_CFG, cfg);
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}
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}
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// enable interrupts
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CEMAC_WRITE(ETH_IDR, -1);
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CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
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