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Enable cpu0 I/D cache. Disable cpu1 it.

This commit is contained in:
kiyohara 2012-10-20 12:45:22 +00:00
parent bc1ed5ac13
commit ee8a036b3d
1 changed files with 22 additions and 1 deletions
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23
sys/arch/bebox/bebox/locore.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.26 2012/10/20 12:13:46 kiyohara Exp $ */
/* $NetBSD: locore.S,v 1.27 2012/10/20 12:45:22 kiyohara Exp $ */
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
/*
@ -49,6 +49,7 @@
#include <machine/asm.h>
#include <powerpc/spr.h>
#include <powerpc/oea/hid.h>
#include <powerpc/oea/spr.h>
/*
@ -123,6 +124,12 @@ __start:
nop
__start_cpu1:
/* Disable data and instruction caches for spinup. */
li 8,0
mtspr SPR_HID0,8
sync
isync
#ifdef MULTIPROCESSOR
li 3, 0x1 /* CPU ID 1 */
ba cpu_spinstart /* cpu_spinstart(CPU ID) */
@ -133,6 +140,20 @@ __start_cpu1:
nop
__start_cpu0:
/* Enable data and instruction caches */
mfspr 8,SPR_HID0
andi. 8,8,(HID0_ICE|HID0_DCE)@l
andi. 0,8,HID0_DCE
ori 7,8,HID0_ICFI
bne 1f
ori 7,7,HID0_DCFI
1:
sync
mtspr SPR_HID0,7
sync
mtspr SPR_HID0,8
sync
isync
/* compute end of kernel memory */
#if defined(DDB) || NKSYMS || defined(MODULAR)