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Dual LVD (1280) support.

This commit is contained in:
mjacob 1999-12-16 05:35:42 +00:00
parent 420c21c43c
commit edf809c8b6
6 changed files with 295 additions and 192 deletions
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109
sys/dev/ic/isp.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: isp.c,v 1.43 1999/12/04 03:08:18 mjacob Exp $ */ /* $NetBSD: isp.c,v 1.44 1999/12/16 05:35:42 mjacob Exp $ */
/* /*
* Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
* All rights reserved. * All rights reserved.
@ -155,7 +155,7 @@ isp_reset(isp)
DISABLE_INTS(isp); DISABLE_INTS(isp);
/* /*
* Put the board into PAUSE mode. * Put the board into PAUSE mode (so we can read the SXP registers).
*/ */
ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
@ -171,37 +171,68 @@ isp_reset(isp)
default: default:
break; break;
} }
} else if (IS_12X0(isp)) { } else if (IS_1240(isp)) {
revname = "12X0"; sdparam *sdp = isp->isp_param;
revname = "1240";
isp->isp_clock = 60; isp->isp_clock = 60;
} else if (IS_1080(isp)) { sdp->isp_ultramode = 1;
sdp++;
sdp->isp_ultramode = 1;
/*
* XXX: Should probably do some bus sensing.
*/
} else if (IS_ULTRA2(isp)) {
static char *m = "%s: bus %d is in %s Mode\n";
u_int16_t l; u_int16_t l;
sdparam *sdp = isp->isp_param; sdparam *sdp = isp->isp_param;
revname = "1080";
isp->isp_clock = 100; isp->isp_clock = 100;
revname = "1080";
l = ISP_READ(isp, SXP_PINS_DIFF) & ISP1080_MODE_MASK; l = ISP_READ(isp, SXP_PINS_DIFF) & ISP1080_MODE_MASK;
switch (l) { switch (l) {
case ISP1080_LVD_MODE: case ISP1080_LVD_MODE:
sdp->isp_lvdmode = 1; sdp->isp_lvdmode = 1;
PRINTF("%s: LVD Mode\n", isp->isp_name); CFGPRINTF(m, isp->isp_name, 0, "LVD");
break; break;
case ISP1080_HVD_MODE: case ISP1080_HVD_MODE:
sdp->isp_diffmode = 1; sdp->isp_diffmode = 1;
CFGPRINTF("%s: Differential Mode\n", isp->isp_name); CFGPRINTF(m, isp->isp_name, 0, "Differential");
break; break;
case ISP1080_SE_MODE: case ISP1080_SE_MODE:
sdp->isp_ultramode = 1; sdp->isp_ultramode = 1;
CFGPRINTF("%s: Single-Ended Mode\n", isp->isp_name); CFGPRINTF(m, isp->isp_name, 0, "Single-Ended");
break; break;
default: default:
/* CFGPRINTF("%s: unknown mode on bus %d (0x%x)\n",
* Hmm. Up in a wierd mode. This means all SCSI I/O isp->isp_name, 0, l);
* buffer lines are tristated, so we're in a lot of
* trouble if we don't set things up right.
*/
PRINTF("%s: Illegal Mode 0x%x\n", isp->isp_name, l);
break; break;
} }
if (IS_1280(isp)) {
sdp++;
revname[1] = '2';
l = ISP_READ(isp, SXP_PINS_DIFF|SXP_BANK1_SELECT);
l &= ISP1080_MODE_MASK;
switch(l) {
case ISP1080_LVD_MODE:
sdp->isp_lvdmode = 1;
CFGPRINTF(m, isp->isp_name, 1, "LVD");
break;
case ISP1080_HVD_MODE:
sdp->isp_diffmode = 1;
CFGPRINTF(m, isp->isp_name, 1, "Differential");
break;
case ISP1080_SE_MODE:
sdp->isp_ultramode = 1;
CFGPRINTF(m, isp->isp_name, 1, "Single-Ended");
break;
default:
CFGPRINTF("%s: unknown mode on bus %d (0x%x)\n",
isp->isp_name, 1, l);
break;
}
}
} else { } else {
sdparam *sdp = isp->isp_param; sdparam *sdp = isp->isp_param;
i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK; i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK;
@ -241,7 +272,7 @@ isp_reset(isp)
isp->isp_clock = 60; isp->isp_clock = 60;
break; break;
case 6: case 6:
revname = "1040C(?)"; revname = "1040C";
isp->isp_type = ISP_HA_SCSI_1040C; isp->isp_type = ISP_HA_SCSI_1040C;
isp->isp_clock = 60; isp->isp_clock = 60;
break; break;
@ -609,7 +640,7 @@ isp_init(isp)
* Must do this first to get defaults established. * Must do this first to get defaults established.
*/ */
isp_setdfltparm(isp, 0); isp_setdfltparm(isp, 0);
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
isp_setdfltparm(isp, 1); isp_setdfltparm(isp, 1);
} }
@ -629,7 +660,7 @@ isp_scsi_init(isp)
sdp_chan0 = isp->isp_param; sdp_chan0 = isp->isp_param;
sdp_chan1 = sdp_chan0; sdp_chan1 = sdp_chan0;
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
sdp_chan1++; sdp_chan1++;
} }
@ -724,7 +755,7 @@ isp_scsi_init(isp)
/* now do per-channel settings */ /* now do per-channel settings */
isp_scsi_channel_init(isp, 0); isp_scsi_channel_init(isp, 0);
if (IS_12X0(isp)) if (IS_DUALBUS(isp))
isp_scsi_channel_init(isp, 1); isp_scsi_channel_init(isp, 1);
/* /*
@ -761,7 +792,7 @@ isp_scsi_init(isp)
* Turn on Fast Posting, LVD transitions * Turn on Fast Posting, LVD transitions
*/ */
if (IS_1080(isp) || if (IS_ULTRA2(isp) ||
ISP_FW_REVX(isp->isp_fwrev) >= ISP_FW_REV(7, 55, 0)) { ISP_FW_REVX(isp->isp_fwrev) >= ISP_FW_REV(7, 55, 0)) {
mbs.param[0] = MBOX_SET_FW_FEATURES; mbs.param[0] = MBOX_SET_FW_FEATURES;
#ifndef ISP_NO_FASTPOST_SCSI #ifndef ISP_NO_FASTPOST_SCSI
@ -769,7 +800,7 @@ isp_scsi_init(isp)
#else #else
mbs.param[1] = 0; mbs.param[1] = 0;
#endif #endif
if (IS_1080(isp)) if (IS_ULTRA2(isp))
mbs.param[1] |= FW_FEATURE_LVD_NOTIFY; mbs.param[1] |= FW_FEATURE_LVD_NOTIFY;
if (mbs.param[1] != 0) { if (mbs.param[1] != 0) {
isp_mboxcmd(isp, &mbs); isp_mboxcmd(isp, &mbs);
@ -827,7 +858,7 @@ isp_scsi_channel_init(isp, channel)
* If we're in LVD mode, then we pretty much should * If we're in LVD mode, then we pretty much should
* only disable tagged queuing. * only disable tagged queuing.
*/ */
if (IS_1080(isp) && sdp->isp_lvdmode) { if (IS_ULTRA2(isp) && sdp->isp_lvdmode) {
sdf = DPARM_DEFAULT & ~DPARM_TQING; sdf = DPARM_DEFAULT & ~DPARM_TQING;
} else { } else {
sdf = DPARM_SAFE_DFLT; sdf = DPARM_SAFE_DFLT;
@ -1920,7 +1951,7 @@ ispscsicmd(xs)
* than which we got here to send a command to. * than which we got here to send a command to.
*/ */
if (isp->isp_sendmarker) { if (isp->isp_sendmarker) {
u_int8_t n = (IS_12X0(isp)? 2: 1); u_int8_t n = (IS_DUALBUS(isp)? 2: 1);
/* /*
* Check ports to send markers for... * Check ports to send markers for...
*/ */
@ -2446,12 +2477,7 @@ isp_parse_async(isp, mbox)
int bus; int bus;
u_int32_t fast_post_handle = 0; u_int32_t fast_post_handle = 0;
/* if (IS_DUALBUS(isp)) {
* It is not documented anywhere that bus is always in OUTMAILBOX6
* for dual bus cards- and we don't have the h/w to prove it either,
* So we'll just assume......
*/
if (IS_1080(isp) || IS_12X0(isp)) {
bus = ISP_READ(isp, OUTMAILBOX6); bus = ISP_READ(isp, OUTMAILBOX6);
} else { } else {
bus = 0; bus = 0;
@ -2705,8 +2731,9 @@ isp_parse_status(isp, sp, xs)
break; break;
case RQCS_RESET_OCCURRED: case RQCS_RESET_OCCURRED:
IDPRINTF(2, ("%s: bus reset destroyed command for target %d " IDPRINTF(2, ("%s: bus %d reset destroyed command for target %d "
"lun %d\n", isp->isp_name, XS_TGT(xs), XS_LUN(xs))); "lun %d\n", isp->isp_name, XS_CHANNEL(xs), XS_TGT(xs),
XS_LUN(xs)));
/* /*
* XXX: Get port number for bus * XXX: Get port number for bus
*/ */
@ -3214,7 +3241,7 @@ command_known:
* XXX Eventually will be fixed by converting register write/read * XXX Eventually will be fixed by converting register write/read
* XXX counts to bitmasks. * XXX counts to bitmasks.
*/ */
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
switch (opcode) { switch (opcode) {
case MBOX_GET_RETRY_COUNT: case MBOX_GET_RETRY_COUNT:
case MBOX_SET_RETRY_COUNT: case MBOX_SET_RETRY_COUNT:
@ -3339,7 +3366,7 @@ command_known:
* Pick up output parameters. Special case some of the readbacks * Pick up output parameters. Special case some of the readbacks
* for the dual port SCSI cards. * for the dual port SCSI cards.
*/ */
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
switch (opcode) { switch (opcode) {
case MBOX_GET_RETRY_COUNT: case MBOX_GET_RETRY_COUNT:
case MBOX_SET_RETRY_COUNT: case MBOX_SET_RETRY_COUNT:
@ -3514,7 +3541,7 @@ isp_dumpregs(isp, msg)
PRINTF(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", PRINTF(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
ISP_READ(isp, SXP_INTERRUPT), ISP_READ(isp, SXP_INTERRUPT),
ISP_READ(isp, SXP_GROSS_ERR), ISP_READ(isp, SXP_GROSS_ERR),
ISP_READ(isp, SXP_PINS_CONTROL)); ISP_READ(isp, SXP_PINS_CTRL));
ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
} }
PRINTF(" mbox regs: %x %x %x %x %x\n", PRINTF(" mbox regs: %x %x %x %x %x\n",
@ -3755,14 +3782,14 @@ isp_setdfltparm(isp, channel)
IDPRINTF(2, ("could not GET ACT NEG STATE\n")); IDPRINTF(2, ("could not GET ACT NEG STATE\n"));
sdp_chan0->isp_req_ack_active_neg = 1; sdp_chan0->isp_req_ack_active_neg = 1;
sdp_chan0->isp_data_line_active_neg = 1; sdp_chan0->isp_data_line_active_neg = 1;
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
sdp_chan1->isp_req_ack_active_neg = 1; sdp_chan1->isp_req_ack_active_neg = 1;
sdp_chan1->isp_data_line_active_neg = 1; sdp_chan1->isp_data_line_active_neg = 1;
} }
} else { } else {
sdp_chan0->isp_req_ack_active_neg = (mbs.param[1] >> 4) & 0x1; sdp_chan0->isp_req_ack_active_neg = (mbs.param[1] >> 4) & 0x1;
sdp_chan0->isp_data_line_active_neg = (mbs.param[1] >> 5) & 0x1; sdp_chan0->isp_data_line_active_neg = (mbs.param[1] >> 5) & 0x1;
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
sdp_chan1->isp_req_ack_active_neg = sdp_chan1->isp_req_ack_active_neg =
(mbs.param[2] >> 4) & 0x1; (mbs.param[2] >> 4) & 0x1;
sdp_chan1->isp_data_line_active_neg = sdp_chan1->isp_data_line_active_neg =
@ -3787,7 +3814,7 @@ isp_setdfltparm(isp, channel)
ISP_10M_SYNCPARMS >> 8; ISP_10M_SYNCPARMS >> 8;
sdp->isp_devparam[tgt].sync_period = sdp->isp_devparam[tgt].sync_period =
ISP_10M_SYNCPARMS & 0xff; ISP_10M_SYNCPARMS & 0xff;
} else if (IS_1080(isp)) { } else if (IS_ULTRA2(isp)) {
sdp->isp_devparam[tgt].sync_offset = sdp->isp_devparam[tgt].sync_offset =
ISP_40M_SYNCPARMS >> 8; ISP_40M_SYNCPARMS >> 8;
sdp->isp_devparam[tgt].sync_period = sdp->isp_devparam[tgt].sync_period =
@ -3941,7 +3968,7 @@ isp_read_nvram(isp)
if (IS_FC(isp)) { if (IS_FC(isp)) {
amt = ISP2100_NVRAM_SIZE; amt = ISP2100_NVRAM_SIZE;
minversion = 1; minversion = 1;
} else if (IS_1080(isp) || IS_12X0(isp)) { } else if (IS_ULTRA2(isp)) {
amt = ISP1080_NVRAM_SIZE; amt = ISP1080_NVRAM_SIZE;
minversion = 0; minversion = 0;
} else { } else {
@ -3981,10 +4008,10 @@ isp_read_nvram(isp)
return (-1); return (-1);
} }
if (IS_1080(isp) || IS_12X0(isp)) { if (IS_ULTRA2(isp)) {
int bus; int bus;
sdparam *sdp = (sdparam *) isp->isp_param; sdparam *sdp = (sdparam *) isp->isp_param;
for (bus = 0; bus < (IS_1080(isp)? 1 : 2); bus++, sdp++) { for (bus = 0; bus < (IS_DUALBUS(isp)? 2 : 1); bus++, sdp++) {
sdp->isp_fifo_threshold = sdp->isp_fifo_threshold =
ISP1080_NVRAM_FIFO_THRESHOLD(nvram_data); ISP1080_NVRAM_FIFO_THRESHOLD(nvram_data);
@ -4344,7 +4371,7 @@ isp_rdnvram_word(isp, wo, rp)
wo &= ((ISP2100_NVRAM_SIZE >> 1) - 1); wo &= ((ISP2100_NVRAM_SIZE >> 1) - 1);
rqst = (ISP_NVRAM_READ << 8) | wo; rqst = (ISP_NVRAM_READ << 8) | wo;
cbits = 10; cbits = 10;
} else if (IS_1080(isp) || IS_12X0(isp)) { } else if (IS_ULTRA2(isp)) {
wo &= ((ISP1080_NVRAM_SIZE >> 1) - 1); wo &= ((ISP1080_NVRAM_SIZE >> 1) - 1);
rqst = (ISP_NVRAM_READ << 8) | wo; rqst = (ISP_NVRAM_READ << 8) | wo;
cbits = 10; cbits = 10;

95
sys/dev/ic/isp_netbsd.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: isp_netbsd.c,v 1.20 1999/12/05 18:20:53 mjacob Exp $ */ /* $NetBSD: isp_netbsd.c,v 1.21 1999/12/16 05:35:43 mjacob Exp $ */
/* /*
* Platform (NetBSD) dependent common attachment code for Qlogic adapters. * Platform (NetBSD) dependent common attachment code for Qlogic adapters.
* Matthew Jacob <mjacob@nas.nasa.gov> * Matthew Jacob <mjacob@nas.nasa.gov>
@ -57,7 +57,8 @@ isp_attach(isp)
isp->isp_osinfo._adapter.scsipi_ioctl = ispioctl; isp->isp_osinfo._adapter.scsipi_ioctl = ispioctl;
isp->isp_state = ISP_RUNSTATE; isp->isp_state = ISP_RUNSTATE;
isp->isp_osinfo._link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; isp->isp_osinfo._link.scsipi_scsi.channel =
(IS_DUALBUS(isp))? 0 : SCSI_CHANNEL_ONLY_ONE;
isp->isp_osinfo._link.adapter_softc = isp; isp->isp_osinfo._link.adapter_softc = isp;
isp->isp_osinfo._link.device = &isp_dev; isp->isp_osinfo._link.device = &isp_dev;
isp->isp_osinfo._link.adapter = &isp->isp_osinfo._adapter; isp->isp_osinfo._link.adapter = &isp->isp_osinfo._adapter;
@ -99,7 +100,7 @@ isp_attach(isp)
isp->isp_osinfo._link.scsipi_scsi.adapter_target = isp->isp_osinfo._link.scsipi_scsi.adapter_target =
sdp->isp_initiator_id; sdp->isp_initiator_id;
isp->isp_osinfo.discovered[0] = 1 << sdp->isp_initiator_id; isp->isp_osinfo.discovered[0] = 1 << sdp->isp_initiator_id;
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
isp->isp_osinfo._link_b = isp->isp_osinfo._link; isp->isp_osinfo._link_b = isp->isp_osinfo._link;
sdp++; sdp++;
isp->isp_osinfo.discovered[1] = isp->isp_osinfo.discovered[1] =
@ -118,7 +119,7 @@ isp_attach(isp)
if (IS_SCSI(isp)) { if (IS_SCSI(isp)) {
int bus = 0; int bus = 0;
(void) isp_control(isp, ISPCTL_RESET_BUS, &bus); (void) isp_control(isp, ISPCTL_RESET_BUS, &bus);
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
bus++; bus++;
(void) isp_control(isp, ISPCTL_RESET_BUS, &bus); (void) isp_control(isp, ISPCTL_RESET_BUS, &bus);
} }
@ -164,7 +165,7 @@ isp_attach(isp)
* And attach children (if any). * And attach children (if any).
*/ */
config_found((void *)isp, &isp->isp_osinfo._link, scsiprint); config_found((void *)isp, &isp->isp_osinfo._link, scsiprint);
if (IS_12X0(isp)) { if (IS_DUALBUS(isp)) {
config_found((void *)isp, &isp->isp_osinfo._link_b, scsiprint); config_found((void *)isp, &isp->isp_osinfo._link_b, scsiprint);
} }
} }
@ -196,7 +197,7 @@ ispcmd_slow(xs)
{ {
sdparam *sdp; sdparam *sdp;
int tgt, chan, s; int tgt, chan, s;
u_int16_t f; u_int16_t flags;
struct ispsoftc *isp = XS_ISP(xs); struct ispsoftc *isp = XS_ISP(xs);
/* /*
@ -204,16 +205,14 @@ ispcmd_slow(xs)
*/ */
tgt = XS_TGT(xs); tgt = XS_TGT(xs);
chan = XS_CHANNEL(xs); chan = XS_CHANNEL(xs);
sdp = isp->isp_param;
sdp += chan;
if ((xs->xs_control & XS_CTL_DISCOVERY) != 0 || if ((xs->xs_control & XS_CTL_DISCOVERY) != 0 ||
(isp->isp_osinfo.discovered[chan] & (1 << tgt)) != 0) { (isp->isp_osinfo.discovered[chan] & (1 << tgt)) != 0) {
return (ispcmd(xs)); return (ispcmd(xs));
} }
f = DPARM_DEFAULT; flags = DPARM_DEFAULT;
if (xs->sc_link->quirks & SDEV_NOSYNC) { if (xs->sc_link->quirks & SDEV_NOSYNC) {
f ^= DPARM_SYNC; flags ^= DPARM_SYNC;
#ifdef DEBUG #ifdef DEBUG
} else { } else {
printf("%s: channel %d target %d can do SYNC xfers\n", printf("%s: channel %d target %d can do SYNC xfers\n",
@ -221,7 +220,7 @@ ispcmd_slow(xs)
#endif #endif
} }
if (xs->sc_link->quirks & SDEV_NOWIDE) { if (xs->sc_link->quirks & SDEV_NOWIDE) {
f ^= DPARM_WIDE; flags ^= DPARM_WIDE;
#ifdef DEBUG #ifdef DEBUG
} else { } else {
printf("%s: channel %d target %d can do WIDE xfers\n", printf("%s: channel %d target %d can do WIDE xfers\n",
@ -229,7 +228,7 @@ ispcmd_slow(xs)
#endif #endif
} }
if (xs->sc_link->quirks & SDEV_NOTAG) { if (xs->sc_link->quirks & SDEV_NOTAG) {
f ^= DPARM_TQING; flags ^= DPARM_TQING;
#ifdef DEBUG #ifdef DEBUG
} else { } else {
printf("%s: channel %d target %d can do TAGGED xfers\n", printf("%s: channel %d target %d can do TAGGED xfers\n",
@ -241,37 +240,12 @@ ispcmd_slow(xs)
* so mark parameters to be updated for it. * so mark parameters to be updated for it.
*/ */
s = splbio(); s = splbio();
sdp->isp_devparam[tgt].dev_flags = f; isp->isp_osinfo.discovered[chan] |= (1 << tgt);
sdp = isp->isp_param;
sdp += chan;
sdp->isp_devparam[tgt].dev_flags = flags;
sdp->isp_devparam[tgt].dev_update = 1; sdp->isp_devparam[tgt].dev_update = 1;
isp->isp_update |= (1 << chan); isp->isp_update |= (1 << chan);
/*
* Now check to see whether we can get out of this checking mode now.
* XXX: WE CANNOT AS YET BECAUSE THERE IS NO MECHANISM TO TELL US
* XXX: WHEN WE'RE DONE DISCOVERY BECAUSE WE NEED ONE COMMAND AFTER
* XXX: DISCOVERY IS DONE FOR EACH TARGET TO TELL US THAT WE'RE DONE
* XXX: AND THAT DOESN'T HAPPEN HERE. AT BEST WE CAN MARK OURSELVES
* XXX: DONE WITH DISCOVERY FOR THIS TARGET AND SO SAVE MAYBE 20
* XXX: LINES OF C CODE.
*/
isp->isp_osinfo.discovered[chan] |= (1 << tgt);
/* do not bother with these lines- they'll never execute correctly */
#if 0
sdp = isp->isp_param;
for (chan = 0; chan < (IS_12X0(isp)? 2 : 1); chan++, sdp++) {
f = 0xffff & ~(1 << sdp->isp_initiator_id);
if (isp->isp_osinfo.discovered[chan] != f) {
break;
}
}
if (chan == (IS_12X0(isp)? 2 : 1)) {
CFGPRINTF("%s: allowing sync/wide negotiation and "
"tag usage\n", isp->isp_name);
isp->isp_osinfo._adapter.scsipi_cmd = ispcmd;
if (IS_12X0(isp))
isp->isp_update |= 2;
}
#endif
splx(s); splx(s);
return (ispcmd(xs)); return (ispcmd(xs));
} }
@ -581,12 +555,47 @@ isp_async(isp, cmd, arg)
tgt = *((int *) arg); tgt = *((int *) arg);
bus = (tgt >> 16) & 0xffff; bus = (tgt >> 16) & 0xffff;
tgt &= 0xffff; tgt &= 0xffff;
sdp += bus;
flags = sdp->isp_devparam[tgt].cur_dflags; flags = sdp->isp_devparam[tgt].cur_dflags;
period = sdp->isp_devparam[tgt].cur_period; period = sdp->isp_devparam[tgt].cur_period;
if ((flags & DPARM_SYNC) && period && if ((flags & DPARM_SYNC) && period &&
(sdp->isp_devparam[tgt].cur_offset) != 0) { (sdp->isp_devparam[tgt].cur_offset) != 0) {
if (sdp->isp_lvdmode) { #if 0
/* CAUSES PANICS */
static char *m = "%s: bus %d now %s mode\n";
u_int16_t r, l;
if (bus == 1)
r = SXP_PINS_DIFF | SXP_BANK1_SELECT;
else
r = SXP_PINS_DIFF;
l = ISP_READ(isp, r) & ISP1080_MODE_MASK;
switch (l) {
case ISP1080_LVD_MODE:
sdp->isp_lvdmode = 1;
printf(m, isp->isp_name, bus, "LVD");
break;
case ISP1080_HVD_MODE:
sdp->isp_diffmode = 1;
printf(m, isp->isp_name, bus, "Differential");
break;
case ISP1080_SE_MODE:
sdp->isp_ultramode = 1;
printf(m, isp->isp_name, bus, "Single-Ended");
break;
default:
printf("%s: unknown mode on bus %d (0x%x)\n",
isp->isp_name, bus, l);
break;
}
#endif
/*
* There's some ambiguity about our negotiated speed
* if we haven't detected LVD mode correctly (which
* seems to happen, unfortunately). If we're in LVD
* mode, then different rules apply about speed.
*/
if (sdp->isp_lvdmode || period < 0xc) {
switch (period) { switch (period) {
case 0xa: case 0xa:
mhz = 40; mhz = 40;

6
sys/dev/ic/isp_netbsd.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: isp_netbsd.h,v 1.19 1999/12/04 02:59:29 mjacob Exp $ */ /* $NetBSD: isp_netbsd.h,v 1.20 1999/12/16 05:35:44 mjacob Exp $ */
/* /*
* NetBSD Specific definitions for the Qlogic ISP Host Adapter * NetBSD Specific definitions for the Qlogic ISP Host Adapter
* Matthew Jacob <mjacob@nas.nasa.gov> * Matthew Jacob <mjacob@nas.nasa.gov>
@ -129,8 +129,8 @@ struct isposinfo {
#define XS_LUN(xs) ((int) (xs)->sc_link->scsipi_scsi.lun) #define XS_LUN(xs) ((int) (xs)->sc_link->scsipi_scsi.lun)
#define XS_TGT(xs) ((int) (xs)->sc_link->scsipi_scsi.target) #define XS_TGT(xs) ((int) (xs)->sc_link->scsipi_scsi.target)
#define XS_CHANNEL(xs) \ #define XS_CHANNEL(xs) \
(((xs)->sc_link == &(((struct ispsoftc *)XS_ISP(xs))->isp_osinfo._link_b))?\ (((int) (xs)->sc_link->scsipi_scsi.channel == SCSI_CHANNEL_ONLY_ONE) ? \
1 : 0) 0 : (xs)->sc_link->scsipi_scsi.channel)
#define XS_RESID(xs) (xs)->resid #define XS_RESID(xs) (xs)->resid
#define XS_XFRLEN(xs) (xs)->datalen #define XS_XFRLEN(xs) (xs)->datalen
#define XS_CDBLEN(xs) (xs)->cmdlen #define XS_CDBLEN(xs) (xs)->cmdlen

184
sys/dev/ic/ispreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ispreg.h,v 1.17 1999/10/17 01:37:12 mjacob Exp $ */ /* $NetBSD: ispreg.h,v 1.18 1999/12/16 05:35:44 mjacob Exp $ */
/* release_6_5_99 */ /* release_6_5_99 */
/* /*
* Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
@ -99,47 +99,47 @@
* Bus Interface Block Register Offsets * Bus Interface Block Register Offsets
*/ */
#define BIU_ID_LO BIU_BLOCK+0x0 /* R : Bus ID, Low */ #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
#define BIU2100_FLASH_ADDR BIU_BLOCK+0x0 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
#define BIU_ID_HI BIU_BLOCK+0x2 /* R : Bus ID, High */ #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
#define BIU2100_FLASH_DATA BIU_BLOCK+0x2 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
#define BIU_CONF0 BIU_BLOCK+0x4 /* R : Bus Configuration #0 */ #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
#define BIU_CONF1 BIU_BLOCK+0x6 /* R : Bus Configuration #1 */ #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
#define BIU2100_CSR BIU_BLOCK+0x6 #define BIU2100_CSR (BIU_BLOCK+0x6)
#define BIU_ICR BIU_BLOCK+0x8 /* RW : Bus Interface Ctrl */ #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
#define BIU_ISR BIU_BLOCK+0xA /* R : Bus Interface Status */ #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
#define BIU_SEMA BIU_BLOCK+0xC /* RW : Bus Semaphore */ #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
#define BIU_NVRAM BIU_BLOCK+0xE /* RW : Bus NVRAM */ #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
#define DFIFO_COMMAND BIU_BLOCK+0x60 /* RW : Command FIFO Port */ #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
#define RDMA2100_CONTROL DFIFO_COMMAND #define RDMA2100_CONTROL DFIFO_COMMAND
#define DFIFO_DATA BIU_BLOCK+0x62 /* RW : Data FIFO Port */ #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
/* /*
* Putzed DMA register layouts. * Putzed DMA register layouts.
*/ */
#define CDMA_CONF DMA_BLOCK+0x20 /* RW*: DMA Configuration */ #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
#define CDMA2100_CONTROL CDMA_CONF #define CDMA2100_CONTROL CDMA_CONF
#define CDMA_CONTROL DMA_BLOCK+0x22 /* RW*: DMA Control */ #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
#define CDMA_STATUS DMA_BLOCK+0x24 /* R : DMA Status */ #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
#define CDMA_FIFO_STS DMA_BLOCK+0x26 /* R : DMA FIFO Status */ #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
#define CDMA_COUNT DMA_BLOCK+0x28 /* RW*: DMA Transfer Count */ #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
#define CDMA_ADDR0 DMA_BLOCK+0x2C /* RW*: DMA Address, Word 0 */ #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
#define CDMA_ADDR1 DMA_BLOCK+0x2E /* RW*: DMA Address, Word 1 */ #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
#define CDMA_ADDR2 DMA_BLOCK+0x30 /* RW*: DMA Address, Word 2 */ #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
#define CDMA_ADDR3 DMA_BLOCK+0x32 /* RW*: DMA Address, Word 3 */ #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
#define DDMA_CONF DMA_BLOCK+0x40 /* RW*: DMA Configuration */ #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
#define TDMA2100_CONTROL DDMA_CONF #define TDMA2100_CONTROL DDMA_CONF
#define DDMA_CONTROL DMA_BLOCK+0x42 /* RW*: DMA Control */ #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
#define DDMA_STATUS DMA_BLOCK+0x44 /* R : DMA Status */ #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
#define DDMA_FIFO_STS DMA_BLOCK+0x46 /* R : DMA FIFO Status */ #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
#define DDMA_COUNT_LO DMA_BLOCK+0x48 /* RW*: DMA Xfer Count, Low */ #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
#define DDMA_COUNT_HI DMA_BLOCK+0x4A /* RW*: DMA Xfer Count, High */ #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
#define DDMA_ADDR0 DMA_BLOCK+0x4C /* RW*: DMA Address, Word 0 */ #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
#define DDMA_ADDR1 DMA_BLOCK+0x4E /* RW*: DMA Address, Word 1 */ #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
/* these are for the 1040A cards */ /* these are for the 1040A cards */
#define DDMA_ADDR2 DMA_BLOCK+0x50 /* RW*: DMA Address, Word 2 */ #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
#define DDMA_ADDR3 DMA_BLOCK+0x52 /* RW*: DMA Address, Word 3 */ #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
/* /*
@ -164,7 +164,8 @@
#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
#define BIU_PCI1080_CONF1_SXP 0x0100 /* SXP bank select */ #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
/* ISP2100 Bus Control/Status Register */ /* ISP2100 Bus Control/Status Register */
@ -320,23 +321,23 @@
* Mailbox Block Register Offsets * Mailbox Block Register Offsets
*/ */
#define INMAILBOX0 MBOX_BLOCK+0x0 #define INMAILBOX0 (MBOX_BLOCK+0x0)
#define INMAILBOX1 MBOX_BLOCK+0x2 #define INMAILBOX1 (MBOX_BLOCK+0x2)
#define INMAILBOX2 MBOX_BLOCK+0x4 #define INMAILBOX2 (MBOX_BLOCK+0x4)
#define INMAILBOX3 MBOX_BLOCK+0x6 #define INMAILBOX3 (MBOX_BLOCK+0x6)
#define INMAILBOX4 MBOX_BLOCK+0x8 #define INMAILBOX4 (MBOX_BLOCK+0x8)
#define INMAILBOX5 MBOX_BLOCK+0xA #define INMAILBOX5 (MBOX_BLOCK+0xA)
#define INMAILBOX6 MBOX_BLOCK+0xC #define INMAILBOX6 (MBOX_BLOCK+0xC)
#define INMAILBOX7 MBOX_BLOCK+0xE #define INMAILBOX7 (MBOX_BLOCK+0xE)
#define OUTMAILBOX0 MBOX_BLOCK+0x0 #define OUTMAILBOX0 (MBOX_BLOCK+0x0)
#define OUTMAILBOX1 MBOX_BLOCK+0x2 #define OUTMAILBOX1 (MBOX_BLOCK+0x2)
#define OUTMAILBOX2 MBOX_BLOCK+0x4 #define OUTMAILBOX2 (MBOX_BLOCK+0x4)
#define OUTMAILBOX3 MBOX_BLOCK+0x6 #define OUTMAILBOX3 (MBOX_BLOCK+0x6)
#define OUTMAILBOX4 MBOX_BLOCK+0x8 #define OUTMAILBOX4 (MBOX_BLOCK+0x8)
#define OUTMAILBOX5 MBOX_BLOCK+0xA #define OUTMAILBOX5 (MBOX_BLOCK+0xA)
#define OUTMAILBOX6 MBOX_BLOCK+0xC #define OUTMAILBOX6 (MBOX_BLOCK+0xC)
#define OUTMAILBOX7 MBOX_BLOCK+0xE #define OUTMAILBOX7 (MBOX_BLOCK+0xE)
#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) #define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2))
#define NMBOX(isp) \ #define NMBOX(isp) \
@ -346,45 +347,48 @@
/* /*
* SXP Block Register Offsets * SXP Block Register Offsets
*/ */
#define SXP_PART_ID SXP_BLOCK+0x0 /* R : Part ID Code */ #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
#define SXP_CONFIG1 SXP_BLOCK+0x2 /* RW*: Configuration Reg #1 */ #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
#define SXP_CONFIG2 SXP_BLOCK+0x4 /* RW*: Configuration Reg #2 */ #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
#define SXP_CONFIG3 SXP_BLOCK+0x6 /* RW*: Configuration Reg #2 */ #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
#define SXP_INSTRUCTION SXP_BLOCK+0xC /* RW*: Instruction Pointer */ #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
#define SXP_RETURN_ADDR SXP_BLOCK+0x10 /* RW*: Return Address */ #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
#define SXP_COMMAND SXP_BLOCK+0x14 /* RW*: Command */ #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
#define SXP_INTERRUPT SXP_BLOCK+0x18 /* R : Interrupt */ #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
#define SXP_SEQUENCE SXP_BLOCK+0x1C /* RW*: Sequence */ #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
#define SXP_GROSS_ERR SXP_BLOCK+0x1E /* R : Gross Error */ #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
#define SXP_EXCEPTION SXP_BLOCK+0x20 /* RW*: Exception Enable */ #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
#define SXP_OVERRIDE SXP_BLOCK+0x24 /* RW*: Override */ #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
#define SXP_LITERAL_BASE SXP_BLOCK+0x28 /* RW*: Literal Base */ #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
#define SXP_USER_FLAGS SXP_BLOCK+0x2C /* RW*: User Flags */ #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
#define SXP_USER_EXCEPT SXP_BLOCK+0x30 /* RW*: User Exception */ #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
#define SXP_BREAKPOINT SXP_BLOCK+0x34 /* RW*: Breakpoint */ #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
#define SXP_SCSI_ID SXP_BLOCK+0x40 /* RW*: SCSI ID */ #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
#define SXP_DEV_CONFIG1 SXP_BLOCK+0x42 /* RW*: Device Config Reg #1 */ #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
#define SXP_DEV_CONFIG2 SXP_BLOCK+0x44 /* RW*: Device Config Reg #2 */ #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
#define SXP_PHASE_POINTER SXP_BLOCK+0x48 /* RW*: SCSI Phase Pointer */ #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
#define SXP_BUF_POINTER SXP_BLOCK+0x4C /* RW*: SCSI Buffer Pointer */ #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
#define SXP_BUF_COUNTER SXP_BLOCK+0x50 /* RW*: SCSI Buffer Counter */ #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
#define SXP_BUFFER SXP_BLOCK+0x52 /* RW*: SCSI Buffer */ #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
#define SXP_BUF_BYTE SXP_BLOCK+0x54 /* RW*: SCSI Buffer Byte */ #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
#define SXP_BUF_WORD SXP_BLOCK+0x56 /* RW*: SCSI Buffer Word */ #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
#define SXP_BUF_WORD_TRAN SXP_BLOCK+0x58 /* RW*: SCSI Buffer Wd xlate */ #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
#define SXP_FIFO SXP_BLOCK+0x5A /* RW*: SCSI FIFO */ #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
#define SXP_FIFO_STATUS SXP_BLOCK+0x5C /* RW*: SCSI FIFO Status */ #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
#define SXP_FIFO_TOP SXP_BLOCK+0x5E /* RW*: SCSI FIFO Top Resid */ #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
#define SXP_FIFO_BOTTOM SXP_BLOCK+0x60 /* RW*: SCSI FIFO Bot Resid */ #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
#define SXP_TRAN_REG SXP_BLOCK+0x64 /* RW*: SCSI Transferr Reg */ #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
#define SXP_TRAN_COUNT_LO SXP_BLOCK+0x68 /* RW*: SCSI Trans Count */ #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
#define SXP_TRAN_COUNT_HI SXP_BLOCK+0x6A /* RW*: SCSI Trans Count */ #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
#define SXP_TRAN_COUNTER_LO SXP_BLOCK+0x6C /* RW*: SCSI Trans Counter */ #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
#define SXP_TRAN_COUNTER_HI SXP_BLOCK+0x6E /* RW*: SCSI Trans Counter */ #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
#define SXP_ARB_DATA SXP_BLOCK+0x70 /* R : SCSI Arb Data */ #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
#define SXP_PINS_CONTROL SXP_BLOCK+0x72 /* RW*: SCSI Control Pins */ #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
#define SXP_PINS_DATA SXP_BLOCK+0x74 /* RW*: SCSI Data Pins */ #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
#define SXP_PINS_DIFF SXP_BLOCK+0x76 /* RW*: SCSI Diff Pins */ #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
/* for 1080/1280/1240 only */
#define SXP_BANK1_SELECT 0x100
/* SXP CONF1 REGISTER */ /* SXP CONF1 REGISTER */
@ -513,7 +517,7 @@
#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
/* 1080 only */ /* Ultra2 only */
#define SXP_PINS_LVD_MODE 0x1000 #define SXP_PINS_LVD_MODE 0x1000
#define SXP_PINS_HVD_MODE 0x0800 #define SXP_PINS_HVD_MODE 0x0800
#define SXP_PINS_SE_MODE 0x0400 #define SXP_PINS_SE_MODE 0x0400

15
sys/dev/ic/ispvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ispvar.h,v 1.26 1999/12/04 03:06:05 mjacob Exp $ */ /* $NetBSD: ispvar.h,v 1.27 1999/12/16 05:35:44 mjacob Exp $ */
/* /*
* Copyright (C) 1999 National Aeronautics & Space Administration * Copyright (C) 1999 National Aeronautics & Space Administration
* All rights reserved. * All rights reserved.
@ -388,15 +388,22 @@ struct ispsoftc {
#define ISP_HA_SCSI_1040A 0x5 #define ISP_HA_SCSI_1040A 0x5
#define ISP_HA_SCSI_1040B 0x6 #define ISP_HA_SCSI_1040B 0x6
#define ISP_HA_SCSI_1040C 0x7 #define ISP_HA_SCSI_1040C 0x7
#define ISP_HA_SCSI_1080 0xd #define ISP_HA_SCSI_1240 0x8
#define ISP_HA_SCSI_12X0 0xe #define ISP_HA_SCSI_1080 0x9
#define ISP_HA_SCSI_1280 0xa
#define ISP_HA_FC 0xf0 #define ISP_HA_FC 0xf0
#define ISP_HA_FC_2100 0x10 #define ISP_HA_FC_2100 0x10
#define ISP_HA_FC_2200 0x20 #define ISP_HA_FC_2200 0x20
#define IS_SCSI(isp) (isp->isp_type & ISP_HA_SCSI) #define IS_SCSI(isp) (isp->isp_type & ISP_HA_SCSI)
#define IS_1240(isp) (isp->isp_type == ISP_HA_SCSI_1240)
#define IS_1080(isp) (isp->isp_type == ISP_HA_SCSI_1080) #define IS_1080(isp) (isp->isp_type == ISP_HA_SCSI_1080)
#define IS_12X0(isp) (isp->isp_type == ISP_HA_SCSI_12X0) #define IS_1280(isp) (isp->isp_type == ISP_HA_SCSI_1280)
#define IS_12X0(isp) \
(isp->isp_type == ISP_HA_SCSI_1240 || isp->isp_type == ISP_HA_SCSI_1280)
#define IS_DUALBUS(isp) IS_12X0(isp)
#define IS_ULTRA2(isp) \
(isp->isp_type == ISP_HA_SCSI_1080 || isp->isp_type == ISP_HA_SCSI_1280)
#define IS_FC(isp) (isp->isp_type & ISP_HA_FC) #define IS_FC(isp) (isp->isp_type & ISP_HA_FC)
/* /*

78
sys/dev/pci/isp_pci.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: isp_pci.c,v 1.47 1999/12/04 02:54:54 mjacob Exp $ */ /* $NetBSD: isp_pci.c,v 1.48 1999/12/16 05:35:46 mjacob Exp $ */
/* /*
* PCI specific probe and attach routines for Qlogic ISP SCSI adapters. * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
* Matthew Jacob (mjacob@nas.nasa.gov) * Matthew Jacob (mjacob@nas.nasa.gov)
@ -160,6 +160,10 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
#endif #endif
#ifndef PCI_PRODUCT_QLOGIC_ISP1280
#define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
#endif
#ifndef PCI_PRODUCT_QLOGIC_ISP2100 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
#endif #endif
@ -176,6 +180,9 @@ static struct ispmdvec mdvec_2200 = {
#define PCI_QLOGIC_ISP1240 \ #define PCI_QLOGIC_ISP1240 \
((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP1280 \
((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
#define PCI_QLOGIC_ISP2100 \ #define PCI_QLOGIC_ISP2100 \
((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
@ -227,6 +234,7 @@ isp_pci_probe(parent, match, aux)
#ifndef ISP_DISABLE_1080_SUPPORT #ifndef ISP_DISABLE_1080_SUPPORT
case PCI_QLOGIC_ISP1080: case PCI_QLOGIC_ISP1080:
case PCI_QLOGIC_ISP1240: case PCI_QLOGIC_ISP1240:
case PCI_QLOGIC_ISP1280:
return (1); return (1);
#endif #endif
#ifndef ISP_DISABLE_2100_SUPPORT #ifndef ISP_DISABLE_2100_SUPPORT
@ -321,7 +329,20 @@ isp_pci_attach(parent, self, aux)
} }
if (pa->pa_id == PCI_QLOGIC_ISP1240) { if (pa->pa_id == PCI_QLOGIC_ISP1240) {
isp->isp_mdvec = &mdvec_1080; isp->isp_mdvec = &mdvec_1080;
isp->isp_type = ISP_HA_SCSI_12X0; isp->isp_type = ISP_HA_SCSI_1240;
isp->isp_param =
malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
if (isp->isp_param == NULL) {
printf(nomem, isp->isp_name);
return;
}
bzero(isp->isp_param, 2 * sizeof (sdparam));
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
ISP1080_DMA_REGS_OFF;
}
if (pa->pa_id == PCI_QLOGIC_ISP1280) {
isp->isp_mdvec = &mdvec_1080;
isp->isp_type = ISP_HA_SCSI_1280;
isp->isp_param = isp->isp_param =
malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT);
if (isp->isp_param == NULL) { if (isp->isp_param == NULL) {
@ -499,12 +520,14 @@ isp_pci_rd_reg(isp, regoff)
*/ */
oldconf = isp_pci_rd_reg(isp, BIU_CONF1); oldconf = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP);
delay(250);
} }
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff); offset += (regoff & 0xff);
rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
isp_pci_wr_reg(isp, BIU_CONF1, oldconf); isp_pci_wr_reg(isp, BIU_CONF1, oldconf);
delay(250);
} }
return (rv); return (rv);
} }
@ -524,12 +547,14 @@ isp_pci_wr_reg(isp, regoff, val)
*/ */
oldconf = isp_pci_rd_reg(isp, BIU_CONF1); oldconf = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP); isp_pci_wr_reg(isp, BIU_CONF1, oldconf | BIU_PCI_CONF1_SXP);
delay(250);
} }
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff); offset += (regoff & 0xff);
bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
isp_pci_wr_reg(isp, BIU_CONF1, oldconf); isp_pci_wr_reg(isp, BIU_CONF1, oldconf);
delay(250);
} }
} }
@ -539,26 +564,41 @@ isp_pci_rd_reg_1080(isp, regoff)
struct ispsoftc *isp; struct ispsoftc *isp;
int regoff; int regoff;
{ {
u_int16_t rv; u_int16_t rv, oc = 0;
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0; int offset;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
u_int16_t tc;
/* /*
* We will assume that someone has paused the RISC processor. * We will assume that someone has paused the RISC processor.
*/ */
oc = isp_pci_rd_reg(isp, BIU_CONF1); oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP); tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (IS_1280(isp)) {
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP0;
else
tc |= BIU_PCI1080_CONF1_SXP1;
} else {
tc |= BIU_PCI1080_CONF1_SXP0;
}
isp_pci_wr_reg(isp, BIU_CONF1, tc);
delay(250);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1); oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
delay(250);
} }
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff); offset += (regoff & 0xff);
rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset); rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || /*
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) { * Okay, because BIU_CONF1 is always nonzero
*/
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc); isp_pci_wr_reg(isp, BIU_CONF1, oc);
delay(250);
} }
return (rv); return (rv);
} }
@ -569,25 +609,41 @@ isp_pci_wr_reg_1080(isp, regoff, val)
int regoff; int regoff;
u_int16_t val; u_int16_t val;
{ {
u_int16_t oc = 0;
struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
int offset, oc = 0; int offset;
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
u_int16_t tc;
/* /*
* We will assume that someone has paused the RISC processor. * We will assume that someone has paused the RISC processor.
*/ */
oc = isp_pci_rd_reg(isp, BIU_CONF1); oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_SXP); tc = oc & ~BIU_PCI1080_CONF1_DMA;
if (IS_1280(isp)) {
if (regoff & SXP_BANK1_SELECT)
tc |= BIU_PCI1080_CONF1_SXP0;
else
tc |= BIU_PCI1080_CONF1_SXP1;
} else {
tc |= BIU_PCI1080_CONF1_SXP0;
}
isp_pci_wr_reg(isp, BIU_CONF1, tc);
delay(250);
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
oc = isp_pci_rd_reg(isp, BIU_CONF1); oc = isp_pci_rd_reg(isp, BIU_CONF1);
isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA); isp_pci_wr_reg(isp, BIU_CONF1, oc | BIU_PCI1080_CONF1_DMA);
delay(250);
} }
offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT]; offset = pcs->pci_poff[(regoff & _BLK_REG_MASK) >> _BLK_REG_SHFT];
offset += (regoff & 0xff); offset += (regoff & 0xff);
bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val); bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || /*
((regoff & _BLK_REG_MASK) == DMA_BLOCK)) { * Okay, because BIU_CONF1 is always nonzero
*/
if (oc) {
isp_pci_wr_reg(isp, BIU_CONF1, oc); isp_pci_wr_reg(isp, BIU_CONF1, oc);
delay(250);
} }
} }
#endif #endif