Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability. While here convert some other M[TF]C0 uses to already exising accessor functions, e.g. mipsNN_cp0_ebase_read
This commit is contained in:
skrll
parent
21f81d6b53
commit
ed6f73360e
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $ */
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/* $NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $");
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#include "opt_multiprocessor.h"
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@ -38,6 +38,7 @@ __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $");
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#include <sys/systm.h>
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#include <sys/timetc.h>
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#include <mips/ingenic/ingenic_var.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include "opt_ingenic.h"
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@ -236,7 +237,7 @@ ingenic_clockintr(struct clockframe *cf)
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* XXX
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* needs to take the IPI lock and ping all online CPUs, not just core 1
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*/
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MTC0(1 << IPI_CLOCK, 20, 1);
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mips_cp0_corembox_write(1, 1 << IPI_CLOCK);
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#endif
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hardclock(cf);
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splx(s);
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $ */
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/* $NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -36,7 +36,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $");
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#include "opt_ingenic.h"
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#include "opt_multiprocessor.h"
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@ -47,8 +47,9 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
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#include <sys/cpu.h>
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#include <mips/locore.h>
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#include <mips/asm.h>
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#include <mips/ingenic/ingenic_coreregs.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include <mips/ingenic/ingenic_var.h>
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static int cpu_match(device_t, cfdata_t, void *);
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static void cpu_attach(device_t, device_t, void *);
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@ -85,14 +86,16 @@ cpu_attach(device_t parent, device_t self, void *aux)
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ci = startup_cpu_info;
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wbflush();
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vec = (uint32_t)&ingenic_wakeup;
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reg = MFC0(12, 4); /* reset entry reg */
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reg = mips_cp0_corereim_read();
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reg &= ~REIM_ENTRY_M;
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reg |= vec;
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MTC0(reg, 12, 4);
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reg = MFC0(12, 2); /* core control reg */
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mips_cp0_corereim_write(reg);
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reg = mips_cp0_corectrl_read();
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reg |= CC_RPC1; /* use our exception vector */
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reg &= ~CC_SW_RST1; /* get core 1 out of reset */
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MTC0(reg, 12, 2);
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mips_cp0_corectrl_write(reg);
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while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) {
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delay(1000);
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bail--;
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $ */
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/* $NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $");
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#define __INTR_PRIVATE
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@ -44,7 +44,9 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
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#include <mips/locore.h>
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#include <machine/intr.h>
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#include <mips/ingenic/ingenic_var.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include <mips/ingenic/ingenic_coreregs.h>
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#include "opt_ingenic.h"
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@ -126,14 +128,15 @@ evbmips_intr_init(void)
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writereg(JZ_ICMR1, 0xffffffff);
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/* allow peripheral interrupts to core 0 only */
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reg = MFC0(12, 4); /* reset entry and interrupts */
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reg = mips_cp0_corereim_read();
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reg &= 0xffff0000;
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reg |= REIM_IRQ0_M | REIM_MIRQ0_M;
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#ifdef MULTIPROCESSOR
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reg |= REIM_MIRQ1_M;
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#endif
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MTC0(reg, 12, 4);
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MTC0(0, 20, 1); /* ping the 2nd core */
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mips_cp0_corereim_write(reg);
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mips_cp0_corembox_write(1, 0); /* ping the 2nd core */
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DPRINTF("%s %08x\n", __func__, reg);
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}
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@ -146,12 +149,12 @@ evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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#if 0
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snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
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MFC0(MIPS_COP_0_CAUSE, 0));
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mipsNN_cp0_cause_read());
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ingenic_puts(buffer);
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#endif
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#endif
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/* see which core we're on */
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id = MFC0(15, 1) & 7;
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id = mipsNN_cp0_ebase_read() & 7;
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/*
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* XXX
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@ -166,12 +169,12 @@ evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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int s = splsched();
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/* read pending IPIs */
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reg = MFC0(12, 3);
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reg = mips_cp0_corestatus_read();
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if (id == 0) {
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if (reg & CS_MIRQ0_P) {
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#ifdef MULTIPROCESSOR
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uint32_t tag;
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tag = MFC0(CP0_CORE_MBOX, 0);
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tag = mips_cp0_corembox_read(id);
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ipi_process(curcpu(), tag);
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#ifdef INGENIC_INTR_DEBUG
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@ -182,13 +185,13 @@ evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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#endif
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reg &= (~CS_MIRQ0_P);
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/* clear it */
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MTC0(reg, 12, 3);
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mips_cp0_corestatus_write(reg);
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}
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} else if (id == 1) {
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if (reg & CS_MIRQ1_P) {
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#ifdef MULTIPROCESSOR
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uint32_t tag;
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tag = MFC0(CP0_CORE_MBOX, 1);
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tag = mips_cp0_corembox_read(id);
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ingenic_puts("1");
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if (tag & 0x400)
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hardclock(cf);
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@ -201,7 +204,7 @@ evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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#endif
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reg &= (~CS_MIRQ1_P);
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/* clear it */
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MTC0(reg, 12, 3);
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mips_cp0_corestatus_write(reg);
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}
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}
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splx(s);
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $ */
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/* $NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -61,6 +61,7 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $");
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#include <mips/locore.h>
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#include <mips/cpuregs.h>
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#include <mips/ingenic/ingenic_coreregs.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include <mips/ingenic/ingenic_var.h>
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@ -128,12 +129,12 @@ ingenic_cpu_init(struct cpu_info *ci)
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uint32_t reg;
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/* enable IPIs for this core */
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reg = MFC0(12, 4); /* reset entry and interrupts */
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reg = mips_cp0_corereim_read();
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if (cpu_index(ci) == 1) {
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reg |= REIM_MIRQ1_M;
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} else
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reg |= REIM_MIRQ0_M;
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MTC0(reg, 12, 4);
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mips_cp0_corereim_write(reg);
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printf("%s %d %08x\n", __func__, cpu_index(ci), reg);
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}
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@ -147,9 +148,9 @@ ingenic_send_ipi(struct cpu_info *ci, int tag)
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mutex_enter(&ingenic_ipi_lock);
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if (kcpuset_isset(cpus_running, cpu_index(ci))) {
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if (cpu_index(ci) == 0) {
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MTC0(msg, CP0_CORE_MBOX, 0);
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mips_cp0_corembox_write(msg, 0);
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} else {
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MTC0(msg, CP0_CORE_MBOX, 1);
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mips_cp0_corembox_write(msg, 1);
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}
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}
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mutex_exit(&ingenic_ipi_lock);
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@ -1,4 +1,4 @@
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/* $NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $ */
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/* $NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $");
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#include "opt_multiprocessor.h"
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@ -95,11 +95,11 @@ mainbus_attach(device_t parent, device_t self, void *aux)
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printf("TMR: %08x\n", readreg(JZ_TC_TMR));
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/* send ourselves an IPI */
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MTC0(0x12345678, CP0_CORE_MBOX, 0);
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mips_cp0_corembox_write(0x12345678, 0);
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delay(1000);
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/* send the other core an IPI */
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MTC0(0x12345678, CP0_CORE_MBOX, 1);
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mips_cp0_corembox_write(0x12345678, 1);
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delay(1000);
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#endif
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}
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@ -1,6 +1,7 @@
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# $NetBSD: files.ingenic,v 1.9 2017/05/19 07:30:24 skrll Exp $
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# $NetBSD: files.ingenic,v 1.10 2017/05/21 06:49:13 skrll Exp $
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file arch/mips/mips/bus_dma.c
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file arch/mips/mips/locore_ingenic.S
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include "dev/scsipi/files.scsipi" # SCSI devices
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include "dev/ata/files.ata" # ATA devices
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@ -0,0 +1,70 @@
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/* $NetBSD: ingenic_coreregs.h,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef INGENIC_COREREGS_H
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#define INGENIC_COREREGS_H
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#ifdef _LOCORE
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#define _(n) __CONCAT($,n)
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#else
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#define _(n) n
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#endif
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/* cores status, 12 select 3 */
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#define CP0_CORE_CTRL _(12), 2 /* select 2 */
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#define CC_SW_RST0 __BIT(0) /* reset core 0 */
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#define CC_SW_RST1 __BIT(1) /* reset core 1 */
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#define CC_RPC0 __BIT(8) /* dedicated reset entry core 0 */
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#define CC_RPC1 __BIT(9) /* -- || -- core 1 */
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#define CC_SLEEP0M __BIT(16) /* mask sleep core 0 */
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#define CC_SLEEP1M __BIT(17) /* mask sleep core 1 */
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/* cores status, 12 select 3 */
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#define CP0_CORE_STATUS _(12), 3
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#define CS_MIRQ0_P __BIT(0) /* mailbox IRQ for 0 pending */
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#define CS_MIRQ1_P __BIT(1) /* || core 1 */
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#define CS_IRQ0_P __BIT(8) /* peripheral IRQ for core 0 */
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#define CS_IRQ1_P __BIT(9) /* || core 1 */
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#define CS_SLEEP0 __BIT(16) /* core 0 sleeping */
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#define CS_SLEEP1 __BIT(17) /* core 1 sleeping */
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/* cores reset entry & IRQ masks - 12 select 4 */
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#define CP0_CORE_REIM _(12), 4
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#define REIM_MIRQ0_M __BIT(0) /* allow mailbox IRQ for core 0 */
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#define REIM_MIRQ1_M __BIT(1) /* allow mailbox IRQ for core 1 */
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#define REIM_IRQ0_M __BIT(8) /* allow peripheral IRQ for core 0 */
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#define REIM_IRQ1_M __BIT(9) /* allow peripheral IRQ for core 1 */
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#define REIM_ENTRY_M __BITS(31,16) /* reset exception entry if RPCn=1 */
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#define CP0_SPINLOCK _(12), 5
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#define CP0_SPINATOMIC _(12), 6
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#define CP0_CORE0_MBOX _(20), 0
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#define CP0_CORE1_MBOX _(20), 1
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#endif /* INGENIC_COREREGS_H */
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@ -1,4 +1,4 @@
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/* $NetBSD: ingenic_regs.h,v 1.24 2016/08/27 05:56:33 skrll Exp $ */
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/* $NetBSD: ingenic_regs.h,v 1.25 2017/05/21 06:49:13 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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@ -129,47 +129,6 @@ readreg(uint32_t reg)
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return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
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}
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/* extra CP0 registers */
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static inline uint32_t
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MFC0(uint32_t r, uint32_t s)
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{
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uint32_t ret = 0x12345678;
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__asm volatile("mfc0 %0, $%1, %2; nop;" : "=r"(ret) : "i"(r), "i"(s));
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return ret;
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}
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#define MTC0(v, r, s) __asm volatile("mtc0 %0, $%1, %2; nop;" :: "r"(v), "i"(r), "i"(s))
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#define CP0_CORE_CTRL 12 /* select 2 */
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#define CC_SW_RST0 1 /* reset core 0 */
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#define CC_SW_RST1 2 /* reset core 1 */
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#define CC_RPC0 0x100 /* dedicated reset entry core 0 */
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#define CC_RPC1 0x200 /* -- || -- core 1 */
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#define CC_SLEEP0M 0x10000 /* mask sleep core 0 */
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#define CC_SLEEP1M 0x20000 /* mask sleep core 1 */
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/* cores status, 12 select 3 */
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#define CS_MIRQ0_P 0x00001 /* mailbox IRQ for 0 pending */
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#define CS_MIRQ1_P 0x00002 /* || core 1 */
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#define CS_IRQ0_P 0x00100 /* peripheral IRQ for core 0 */
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#define CS_IRQ1_P 0x00200 /* || core 1 */
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#define CS_SLEEP0 0x10000 /* core 0 sleeping */
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#define CS_SLEEP1 0x20000 /* core 1 sleeping */
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/* cores reset entry & IRQ masks - 12 select 4 */
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#define REIM_MIRQ0_M 0x00001 /* allow mailbox IRQ for core 0 */
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#define REIM_MIRQ1_M 0x00002 /* allow mailbox IRQ for core 1 */
|
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#define REIM_IRQ0_M 0x00100 /* allow peripheral IRQ for core 0 */
|
||||
#define REIM_IRQ1_M 0x00200 /* allow peripheral IRQ for core 1 */
|
||||
#define REIM_ENTRY_M 0xfffff000 /* reset exception entry if RPCn=1 */
|
||||
|
||||
#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
|
||||
|
||||
#define CP0_CORE0_MBOX _(20), 0
|
||||
#define CP0_CORE1_MBOX _(20), 1
|
||||
|
||||
|
||||
|
||||
/* power management */
|
||||
#define JZ_CPCCR 0x10000000 /* Clock Control Register */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: ingenic_var.h,v 1.5 2015/05/18 15:07:52 macallan Exp $ */
|
||||
/* $NetBSD: ingenic_var.h,v 1.6 2017/05/21 06:49:13 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2014 Michael Lorenz
|
||||
|
|
@ -45,4 +45,14 @@ struct apbus_attach_args {
|
|||
extern bus_space_tag_t ingenic_memt;
|
||||
void apbus_init(void);
|
||||
|
||||
uint32_t mips_cp0_corectrl_read(void);
|
||||
uint32_t mips_cp0_corestatus_read(void);
|
||||
uint32_t mips_cp0_corereim_read(void);
|
||||
uint32_t mips_cp0_corembox_read(u_int);
|
||||
|
||||
void mips_cp0_corectrl_write(uint32_t);
|
||||
void mips_cp0_corestatus_write(uint32_t);
|
||||
void mips_cp0_corereim_write(uint32_t);
|
||||
void mips_cp0_corembox_write(u_int, uint32_t);
|
||||
|
||||
#endif /* INGENIC_VAR_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,150 @@
|
|||
/* $NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2017 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Nick Hudson
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <mips/asm.h>
|
||||
RCSID("$NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $")
|
||||
|
||||
#include <mips/cpuregs.h>
|
||||
#include <mips/ingenic/ingenic_coreregs.h>
|
||||
|
||||
#include "assym.h"
|
||||
|
||||
.set noreorder
|
||||
.set noat
|
||||
.set arch=mips32r2
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* uint32_t mips_cp0_corectrl_read(void)
|
||||
*
|
||||
* Return the current value of the CP0 Core Control register.
|
||||
*/
|
||||
LEAF(mips_cp0_corectrl_read)
|
||||
mfc0 v0, CP0_CORE_CTRL
|
||||
jr ra
|
||||
nop
|
||||
END(mips_cp0_corectrl_read)
|
||||
|
||||
/*
|
||||
* void mips_cp0_corectrl_write(uint32_t)
|
||||
*
|
||||
* Set the value of the CP0 Core Control register.
|
||||
*/
|
||||
LEAF(mips_cp0_corectrl_write)
|
||||
mtc0 a0, CP0_CORE_CTRL
|
||||
jr.hb ra
|
||||
nop
|
||||
END(mips_cp0_corectrl_write)
|
||||
|
||||
/*
|
||||
* uint32_t mips_cp0_corestatus_read(void)
|
||||
*
|
||||
* Return the current value of the CP0 Core Status register.
|
||||
*/
|
||||
LEAF(mips_cp0_corestatus_read)
|
||||
mfc0 v0, CP0_CORE_STATUS
|
||||
jr ra
|
||||
nop
|
||||
END(mips_cp0_corestatus_read)
|
||||
|
||||
/*
|
||||
* void mips_cp0_corestatus_write(uint32_t)
|
||||
*
|
||||
* Set the value of the CP0 Core Status register.
|
||||
*/
|
||||
LEAF(mips_cp0_corestatus_write)
|
||||
mtc0 a0, CP0_CORE_STATUS
|
||||
jr.hb ra
|
||||
nop
|
||||
END(mips_cp0_corestatus_write)
|
||||
|
||||
|
||||
/*
|
||||
* uint32_t mips_cp0_corereim_read(void)
|
||||
*
|
||||
* Return the current value of the CP0 Reset Entry & IRQ Mask register.
|
||||
*/
|
||||
LEAF(mips_cp0_corereim_read)
|
||||
mfc0 v0, CP0_CORE_REIM
|
||||
jr ra
|
||||
nop
|
||||
END(mips_cp0_corereim_read)
|
||||
|
||||
/*
|
||||
* void mips_cp0_corereim_write(uint32_t)
|
||||
*
|
||||
* Set the value of the CP0 Core Reset Entry & IRQ Mask register.
|
||||
*/
|
||||
LEAF(mips_cp0_corereim_write)
|
||||
mtc0 a0, CP0_CORE_REIM
|
||||
jr.hb ra
|
||||
nop
|
||||
END(mips_cp0_corereim_write)
|
||||
|
||||
|
||||
/*
|
||||
* uintptr_t mips_cp0_corembox_read(u_int sel)
|
||||
*
|
||||
* Return the current value of the selected CP0 Mailbox register.
|
||||
*/
|
||||
LEAF(mips_cp0_corembox_read)
|
||||
sll a0, 2
|
||||
PTR_LA t9, 1f
|
||||
PTR_ADDU t9, a0
|
||||
jr t9
|
||||
nop
|
||||
1:
|
||||
jr ra
|
||||
mfc0 v0, CP0_CORE0_MBOX
|
||||
jr ra
|
||||
mfc0 v0, CP0_CORE1_MBOX
|
||||
jr ra
|
||||
END(mips_cp0_corembox_read)
|
||||
|
||||
/*
|
||||
* void mips_cp0_watchlo_write(u_int sel, uinte32_t val)
|
||||
*
|
||||
* Set the current value of the selected CP0 Mailbox register.
|
||||
*/
|
||||
LEAF(mips_cp0_corembox_write)
|
||||
sll a0, 2
|
||||
PTR_LA t9, 1f
|
||||
PTR_ADDU t9, a0
|
||||
jr t9
|
||||
nop
|
||||
1:
|
||||
jr.hb ra
|
||||
mtc0 a1, CP0_CORE0_MBOX
|
||||
jr.hb ra
|
||||
mtc0 a1, CP0_CORE1_MBOX
|
||||
jr.hb ra
|
||||
END(mips_cp0_corembox_write)
|
||||
Loading…
Reference in New Issue