The Ricoh power hackery is not reliable -- many cards just do not have the
voltage sense wired. So, disable it and force the card to 5V by default. Also, recode the hack to use the "direct Vcc" feature of the chip, letting it manage the voltage directly, as this is supported on both the 296 and 396.
This commit is contained in:
parent
91e2bd73c5
commit
ec14ab4b89
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@ -1,4 +1,4 @@
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/* $NetBSD: i82365.c,v 1.75 2003/09/05 01:02:51 mycroft Exp $ */
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/* $NetBSD: i82365.c,v 1.76 2003/09/12 22:09:04 mycroft Exp $ */
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/*
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* Copyright (c) 2000 Christian E. Hopps. All rights reserved.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.75 2003/09/05 01:02:51 mycroft Exp $");
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__KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.76 2003/09/12 22:09:04 mycroft Exp $");
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#define PCICDEBUG
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@ -1425,7 +1425,6 @@ pcic_chip_socket_enable(pch)
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{
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struct pcic_handle *h = (struct pcic_handle *) pch;
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int cardtype, win, intr, pwr;
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int vcc_3v, regtmp;
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#if defined(DIAGNOSTIC) || defined(PCICDEBUG)
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int reg;
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#endif
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@ -1456,25 +1455,16 @@ pcic_chip_socket_enable(pch)
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switch( h->vendor ) {
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case PCIC_VENDOR_RICOH_5C296:
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case PCIC_VENDOR_RICOH_5C396:
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vcc_3v = 0;
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regtmp = pcic_read(h, PCIC_CARD_DETECT);
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if(regtmp & PCIC_CARD_DETECT_GPI_ENABLE) {
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DPRINTF(("\nGPI is enabled. Can't sense VS1\n"));
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} else {
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regtmp = pcic_read(h, PCIC_IF_STATUS) ;
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vcc_3v = (regtmp & PCIC_IF_STATUS_GPI) ? 1 : 0;
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DPRINTF(("\n5VDET = %s\n",
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vcc_3v ? "1 (3.3V)" : "0 (5V)"));
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}
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{
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int regtmp;
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regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2);
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regtmp &= ~PCIC_RICOH_MCR2_VCC_SEL_MASK;
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if(vcc_3v) {
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regtmp |= PCIC_RICOH_MCR2_VCC_SEL_3V;
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} else {
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regtmp |= PCIC_RICOH_MCR2_VCC_SEL_5V;
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}
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#ifdef RICOH_POWER_HACK
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regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT;
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#else
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regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V);
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#endif
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pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp);
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}
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break;
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default:
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break;
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@ -1,4 +1,4 @@
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/* $NetBSD: i82365reg.h,v 1.7 2002/11/24 02:46:55 takemura Exp $ */
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/* $NetBSD: i82365reg.h,v 1.8 2003/09/12 22:09:04 mycroft Exp $ */
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/*
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* Copyright (c) 1997 Marc Horowitz. All rights reserved.
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#define PCIC_RICOH_CHIP_ID_5C296 0x32
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#define PCIC_RICOH_CHIP_ID_5C396 0xB2
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#define PCIC_RICOH_REG_MCR2 0x2F
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#define PCIC_RICOH_MCR2_VCC_DIRECT 0x08
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#define PCIC_RICOH_MCR2_VCC_SEL_MASK 0x01
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#define PCIC_RICOH_MCR2_VCC_SEL_3V 0x01
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#define PCIC_RICOH_MCR2_VCC_SEL_5V 0x00
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