Pulldown from marc-pcmcia branch: garbage-collect NE2000 support from
this file. The "ne" driver is now used, instead.
This commit is contained in:
thorpej
parent
4dee791caf
commit
ec0566e1f8
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@ -1,4 +1,4 @@
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/* $NetBSD: if_ed.c,v 1.113 1997/10/13 00:47:28 explorer Exp $ */
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/* $NetBSD: if_ed.c,v 1.114 1997/10/14 23:04:19 thorpej Exp $ */
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/*
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* Device driver for National Semiconductor DS8390/WD83C690 based ethernet
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@ -107,7 +107,6 @@ struct ed_softc {
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int mem_size; /* total NIC memory size */
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int mem_ring; /* offset of RX ring-buffer (in NIC mem) */
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u_char mem_shared; /* NIC memory is shared with host */
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u_char txb_cnt; /* number of transmit buffers */
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u_char txb_inuse; /* number of transmit buffers active */
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@ -135,8 +134,6 @@ int ed_find_WD80x3 __P((struct ed_softc *, struct cfdata *,
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struct isa_attach_args *ia));
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int ed_find_3Com __P((struct ed_softc *, struct cfdata *,
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struct isa_attach_args *ia));
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int ed_find_Novell __P((struct ed_softc *, struct cfdata *,
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struct isa_attach_args *ia));
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int edintr __P((void *));
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int edioctl __P((struct ifnet *, u_long, caddr_t));
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void edstart __P((struct ifnet *));
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@ -158,10 +155,6 @@ static inline void ed_xmit __P((struct ed_softc *));
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static inline int ed_ring_copy __P((struct ed_softc *, int, caddr_t,
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u_short));
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void ed_pio_readmem __P((struct ed_softc *, u_short, caddr_t, u_short));
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void ed_pio_writemem __P((struct ed_softc *, caddr_t, u_short, u_short));
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u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, u_short));
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struct cfattach ed_ca = {
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sizeof(struct ed_softc), edprobe, edattach
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};
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@ -207,8 +200,6 @@ ed_find(sc, cf, ia)
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return (1);
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if (ed_find_3Com(sc, cf, ia))
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return (1);
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if (ed_find_Novell(sc, cf, ia))
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return (1);
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return (0);
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}
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@ -519,7 +510,6 @@ ed_find_WD80x3(sc, cf, ia)
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/* XXX Figure out the shared memory address. */
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sc->isa16bit = isa16bit;
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sc->mem_shared = 1;
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ia->ia_msize = memsize;
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if (bus_space_map(memt, ia->ia_maddr, memsize, 0, &memh))
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goto out;
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@ -808,7 +798,6 @@ ed_find_3Com(sc, cf, ia)
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sc->vendor = ED_VENDOR_3COM;
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sc->type_str = "3c503";
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sc->mem_shared = 1;
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sc->cr_proto = ED_CR_RD2;
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/*
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@ -997,253 +986,6 @@ ed_find_3Com(sc, cf, ia)
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return 0;
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}
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/*
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* Probe and vendor-specific initialization routine for NE1000/2000 boards.
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*/
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int
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ed_find_Novell(sc, cf, ia)
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struct ed_softc *sc;
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struct cfdata *cf;
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struct isa_attach_args *ia;
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{
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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u_int memsize, n;
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u_char romdata[16], tmp;
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static u_char test_pattern[32] = "THIS is A memory TEST pattern";
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u_char test_buffer[32];
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int asicbase, nicbase;
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iot = ia->ia_iot;
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if (bus_space_map(iot, ia->ia_iobase, ED_NOVELL_IO_PORTS, 0, &ioh))
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return (0);
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sc->asic_base = asicbase = ED_NOVELL_ASIC_OFFSET;
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sc->nic_base = nicbase = ED_NOVELL_NIC_OFFSET;
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/* XXX - do Novell-specific probe here */
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/* Reset the board. */
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#ifdef GWETHER
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bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, 0);
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delay(200);
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#endif /* GWETHER */
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tmp = bus_space_read_1(iot, ioh, asicbase + ED_NOVELL_RESET);
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/*
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* I don't know if this is necessary; probably cruft leftover from
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* Clarkson packet driver code. Doesn't do a thing on the boards I've
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* tested. -DG [note that a outb(0x84, 0) seems to work here, and is
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* non-invasive...but some boards don't seem to reset and I don't have
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* complete documentation on what the 'right' thing to do is...so we do
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* the invasive thing for now. Yuck.]
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*/
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bus_space_write_1(iot, ioh, asicbase + ED_NOVELL_RESET, tmp);
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delay(5000);
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/*
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* This is needed because some NE clones apparently don't reset the NIC
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* properly (or the NIC chip doesn't reset fully on power-up)
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* XXX - this makes the probe invasive! ...Done against my better
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* judgement. -DLG
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*/
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NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
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ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STP);
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delay(5000);
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/* Make sure that we really have an 8390 based board. */
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if (!ed_probe_generic8390(iot, ioh, nicbase))
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goto out;
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sc->vendor = ED_VENDOR_NOVELL;
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sc->mem_shared = 0;
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sc->cr_proto = ED_CR_RD2;
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ia->ia_msize = 0;
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/*
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* Test the ability to read and write to the NIC memory. This has the
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* side affect of determining if this is an NE1000 or an NE2000.
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*/
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/*
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* This prevents packets from being stored in the NIC memory when the
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* readmem routine turns on the start bit in the CR.
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*/
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NIC_PUT(iot, ioh, nicbase, ED_P0_RCR, ED_RCR_MON);
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/* Temporarily initialize DCR for byte operations. */
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NIC_PUT(iot, ioh, nicbase, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
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NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 8192 >> ED_PAGE_SHIFT);
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NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 16384 >> ED_PAGE_SHIFT);
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sc->isa16bit = 0;
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/*
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* XXX indirect brokenness, used by ed_pio{read,write}mem()
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*/
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sc->sc_iot = iot;
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sc->sc_ioh = ioh;
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/*
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* Write a test pattern in byte mode. If this fails, then there
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* probably isn't any memory at 8k - which likely means that the board
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* is an NE2000.
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*/
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ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
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ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
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if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
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/* not an NE1000 - try NE2000 */
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NIC_PUT(iot, ioh, nicbase, ED_P0_DCR,
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ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
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NIC_PUT(iot, ioh, nicbase, ED_P0_PSTART, 16384 >> ED_PAGE_SHIFT);
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NIC_PUT(iot, ioh, nicbase, ED_P0_PSTOP, 32768 >> ED_PAGE_SHIFT);
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sc->isa16bit = 1;
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/*
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* Write a test pattern in word mode. If this also fails, then
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* we don't know what this board is.
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*/
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ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
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ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
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if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
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goto out; /* not an NE2000 either */
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sc->type = ED_TYPE_NE2000;
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sc->type_str = "NE2000";
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} else {
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sc->type = ED_TYPE_NE1000;
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sc->type_str = "NE1000";
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}
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if (ia->ia_irq == IRQUNK) {
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printf("%s: %s does not have soft configuration\n",
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sc->sc_dev.dv_xname, sc->type_str);
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goto out;
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}
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/* 8k of memory plus an additional 8k if 16-bit. */
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memsize = 8192 + sc->isa16bit * 8192;
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#if 0 /* probably not useful - NE boards only come two ways */
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/* Allow kernel config file overrides. */
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if (ia->ia_msize)
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memsize = ia->ia_msize;
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#endif
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/* NIC memory doesn't start at zero on an NE board. */
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/* The start address is tied to the bus width. */
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sc->mem_start = (8192 + sc->isa16bit * 8192);
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sc->tx_page_start = memsize >> ED_PAGE_SHIFT;
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#ifdef GWETHER
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{
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int x, i, mstart = 0;
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char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
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for (i = 0; i < ED_PAGE_SIZE; i++)
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pbuf0[i] = 0;
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/* Search for the start of RAM. */
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for (x = 1; x < 256; x++) {
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ed_pio_writemem(sc, pbuf0, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
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ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
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if (!bcmp(pbuf0, tbuf, ED_PAGE_SIZE)) {
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for (i = 0; i < ED_PAGE_SIZE; i++)
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pbuf[i] = 255 - x;
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ed_pio_writemem(sc, pbuf, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
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ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
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if (!bcmp(pbuf, tbuf, ED_PAGE_SIZE)) {
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mstart = x << ED_PAGE_SHIFT;
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memsize = ED_PAGE_SIZE;
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break;
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}
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}
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}
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if (mstart == 0) {
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printf("%s: cannot find start of RAM\n",
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sc->sc_dev.dv_xname);
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goto err;
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}
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/* Search for the end of RAM. */
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for (++x; x < 256; x++) {
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ed_pio_writemem(sc, pbuf0, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
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ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
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if (!bcmp(pbuf0, tbuf, ED_PAGE_SIZE)) {
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for (i = 0; i < ED_PAGE_SIZE; i++)
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pbuf[i] = 255 - x;
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ed_pio_writemem(sc, pbuf, x << ED_PAGE_SHIFT, ED_PAGE_SIZE);
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ed_pio_readmem(sc, x << ED_PAGE_SHIFT, tbuf, ED_PAGE_SIZE);
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if (!bcmp(pbuf, tbuf, ED_PAGE_SIZE))
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memsize += ED_PAGE_SIZE;
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else
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break;
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} else
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break;
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}
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printf("%s: RAM start %x, size %d\n",
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sc->sc_dev.dv_xname, mstart, memsize);
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sc->mem_start = (caddr_t)mstart;
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sc->tx_page_start = mstart >> ED_PAGE_SHIFT;
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}
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#endif /* GWETHER */
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sc->mem_size = memsize;
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sc->mem_end = sc->mem_start + memsize;
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/*
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* Use one xmit buffer if < 16k, two buffers otherwise (if not told
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* otherwise).
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*/
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if ((memsize < 16384) || (cf->cf_flags & ED_FLAGS_NO_MULTI_BUFFERING))
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sc->txb_cnt = 1;
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else
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sc->txb_cnt = 2;
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sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
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sc->rec_page_stop = sc->tx_page_start + (memsize >> ED_PAGE_SHIFT);
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sc->mem_ring =
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sc->mem_start + ((sc->txb_cnt * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
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ed_pio_readmem(sc, 0, romdata, 16);
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for (n = 0; n < ETHER_ADDR_LEN; n++)
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sc->sc_enaddr[n] = romdata[n*(sc->isa16bit+1)];
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#ifdef GWETHER
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if (sc->sc_enaddr[2] == 0x86)
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sc->type_str = "Gateway AT";
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#endif /* GWETHER */
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/* Clear any pending interrupts that might have occurred above. */
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NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, 0xff);
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ia->ia_iosize = ED_NOVELL_IO_PORTS;
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/*
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* XXX Sould always unmap, but we can't yet.
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* XXX Need to squish "indirect" first.
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*/
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sc->sc_iot = iot;
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sc->sc_ioh = ioh;
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/* sc_memh is not used by this driver */
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return 1;
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out:
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bus_space_unmap(iot, ioh, ED_NOVELL_IO_PORTS);
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return 0;
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}
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/*
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* Install interface into kernel networking data structures.
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*/
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@ -1641,62 +1383,59 @@ outloop:
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buffer = sc->mem_start +
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((sc->txb_new * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
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if (sc->mem_shared) {
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/* Special case setup for 16 bit boards... */
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switch (sc->vendor) {
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/*
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* For 16bit 3Com boards (which have 16k of memory), we
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* have the xmit buffers in a different page of memory
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* ('page 0') - so change pages.
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*/
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case ED_VENDOR_3COM:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh,
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asicbase + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL);
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break;
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/*
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* Enable 16bit access to shared memory on WD/SMC
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* boards.
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*/
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case ED_VENDOR_WD_SMC:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
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sc->wd_msr_proto | ED_WD_MSR_MENB);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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break;
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}
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/* Special case setup for 16 bit boards... */
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switch (sc->vendor) {
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/*
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* For 16bit 3Com boards (which have 16k of memory), we
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* have the xmit buffers in a different page of memory
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* ('page 0') - so change pages.
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*/
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case ED_VENDOR_3COM:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh,
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asicbase + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL);
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break;
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/*
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* Enable 16bit access to shared memory on WD/SMC
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* boards.
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*/
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case ED_VENDOR_WD_SMC:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
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sc->wd_msr_proto | ED_WD_MSR_MENB);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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break;
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}
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for (m = m0; m != 0; m = m->m_next) {
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ed_shared_writemem(sc, mtod(m, caddr_t), buffer,
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m->m_len);
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buffer += m->m_len;
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}
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len = m0->m_pkthdr.len;
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for (m = m0; m != 0; m = m->m_next) {
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ed_shared_writemem(sc, mtod(m, caddr_t), buffer,
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m->m_len);
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buffer += m->m_len;
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}
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len = m0->m_pkthdr.len;
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/* Restore previous shared memory access. */
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switch (sc->vendor) {
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case ED_VENDOR_3COM:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh,
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asicbase + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
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break;
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case ED_VENDOR_WD_SMC:
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bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
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sc->wd_msr_proto);
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
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sc->wd_laar_proto);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
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break;
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}
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} else
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len = ed_pio_write_mbufs(sc, m0, (long)buffer);
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/* Restore previous shared memory access. */
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switch (sc->vendor) {
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case ED_VENDOR_3COM:
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if (sc->isa16bit)
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bus_space_write_1(iot, ioh,
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asicbase + ED_3COM_GACFR,
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ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
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break;
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case ED_VENDOR_WD_SMC:
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bus_space_write_1(iot, ioh, asicbase + ED_WD_MSR,
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sc->wd_msr_proto);
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if (sc->isa16bit)
|
||||
bus_space_write_1(iot, ioh, asicbase + ED_WD_LAAR,
|
||||
sc->wd_laar_proto);
|
||||
(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
|
||||
(void) bus_space_read_1(iot, sc->sc_delaybah, 0);
|
||||
break;
|
||||
}
|
||||
|
||||
m_freem(m0);
|
||||
sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN);
|
||||
|
|
@ -1760,12 +1499,8 @@ loop:
|
|||
* The byte count includes a 4 byte header that was added by
|
||||
* the NIC.
|
||||
*/
|
||||
if (sc->mem_shared)
|
||||
ed_shared_readmem(sc, packet_ptr, (caddr_t)&packet_hdr,
|
||||
sizeof(packet_hdr));
|
||||
else
|
||||
ed_pio_readmem(sc, (long)packet_ptr,
|
||||
(caddr_t) &packet_hdr, sizeof(packet_hdr));
|
||||
ed_shared_readmem(sc, packet_ptr, (caddr_t)&packet_hdr,
|
||||
sizeof(packet_hdr));
|
||||
len = packet_hdr.count;
|
||||
|
||||
/*
|
||||
|
|
@ -2212,217 +1947,6 @@ edread(sc, buf, len)
|
|||
* Supporting routines.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Given a NIC memory source address and a host memory destination address,
|
||||
* copy 'amount' from NIC to host using Programmed I/O. The 'amount' is
|
||||
* rounded up to a word - okay as long as mbufs are word sized.
|
||||
* This routine is currently Novell-specific.
|
||||
*/
|
||||
void
|
||||
ed_pio_readmem(sc, src, dst, amount)
|
||||
struct ed_softc *sc;
|
||||
u_short src;
|
||||
caddr_t dst;
|
||||
u_short amount;
|
||||
{
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
bus_space_handle_t ioh = sc->sc_ioh;
|
||||
int nicbase = sc->nic_base;
|
||||
|
||||
/* Select page 0 registers. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
/* Round up to a word. */
|
||||
if (amount & 1)
|
||||
++amount;
|
||||
|
||||
/* Set up DMA byte count. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, amount);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, amount >> 8);
|
||||
|
||||
/* Set up source address in NIC mem. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, src);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, src >> 8);
|
||||
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD0 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
if (sc->isa16bit)
|
||||
bus_space_read_multi_2(iot, ioh, sc->asic_base + ED_NOVELL_DATA,
|
||||
(u_int16_t *)dst, amount / 2);
|
||||
else
|
||||
bus_space_read_multi_1(iot, ioh, sc->asic_base + ED_NOVELL_DATA,
|
||||
dst, amount);
|
||||
}
|
||||
|
||||
/*
|
||||
* Stripped down routine for writing a linear buffer to NIC memory. Only used
|
||||
* in the probe routine to test the memory. 'len' must be even.
|
||||
*/
|
||||
void
|
||||
ed_pio_writemem(sc, src, dst, len)
|
||||
struct ed_softc *sc;
|
||||
caddr_t src;
|
||||
u_short dst;
|
||||
u_short len;
|
||||
{
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
bus_space_handle_t ioh = sc->sc_ioh;
|
||||
int nicbase = sc->nic_base;
|
||||
int maxwait = 100; /* about 120us */
|
||||
|
||||
/* Select page 0 registers. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
/* Reset remote DMA complete flag. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
|
||||
|
||||
/* Set up DMA byte count. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
|
||||
|
||||
/* Set up destination address in NIC mem. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
|
||||
|
||||
/* Set remote DMA write. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
if (sc->isa16bit)
|
||||
bus_space_write_multi_2(iot, ioh, sc->asic_base + ED_NOVELL_DATA,
|
||||
(u_int16_t *)src, len / 2);
|
||||
else
|
||||
bus_space_write_multi_1(iot, ioh, sc->asic_base + ED_NOVELL_DATA,
|
||||
src, len);
|
||||
|
||||
/*
|
||||
* Wait for remote DMA complete. This is necessary because on the
|
||||
* transmit side, data is handled internally by the NIC in bursts and
|
||||
* we can't start another remote DMA until this one completes. Not
|
||||
* waiting causes really bad things to happen - like the NIC
|
||||
* irrecoverably jamming the ISA bus.
|
||||
*/
|
||||
while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
|
||||
ED_ISR_RDC) && --maxwait);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write an mbuf chain to the destination NIC memory address using programmed
|
||||
* I/O.
|
||||
*/
|
||||
u_short
|
||||
ed_pio_write_mbufs(sc, m, dst)
|
||||
struct ed_softc *sc;
|
||||
struct mbuf *m;
|
||||
u_short dst;
|
||||
{
|
||||
bus_space_tag_t iot = sc->sc_iot;
|
||||
bus_space_handle_t ioh = sc->sc_ioh;
|
||||
int nicbase = sc->nic_base, asicbase = sc->asic_base;
|
||||
u_short len;
|
||||
int maxwait = 100; /* about 120us */
|
||||
|
||||
len = m->m_pkthdr.len;
|
||||
|
||||
/* Select page 0 registers. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD2 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
/* Reset remote DMA complete flag. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_ISR, ED_ISR_RDC);
|
||||
|
||||
/* Set up DMA byte count. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR0, len);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RBCR1, len >> 8);
|
||||
|
||||
/* Set up destination address in NIC mem. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR0, dst);
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_RSAR1, dst >> 8);
|
||||
|
||||
/* Set remote DMA write. */
|
||||
NIC_PUT(iot, ioh, nicbase, ED_P0_CR,
|
||||
ED_CR_RD1 | ED_CR_PAGE_0 | ED_CR_STA);
|
||||
|
||||
/*
|
||||
* Transfer the mbuf chain to the NIC memory.
|
||||
* 16-bit cards require that data be transferred as words, and only
|
||||
* words, so that case requires some extra code to patch over
|
||||
* odd-length mbufs.
|
||||
*/
|
||||
if (!sc->isa16bit) {
|
||||
/* NE1000s are easy. */
|
||||
for (; m != 0; m = m->m_next) {
|
||||
if (m->m_len) {
|
||||
bus_space_write_multi_1(iot, ioh,
|
||||
asicbase + ED_NOVELL_DATA,
|
||||
mtod(m, u_char *), m->m_len);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* NE2000s are a bit trickier. */
|
||||
u_int8_t *data, savebyte[2];
|
||||
int len, wantbyte;
|
||||
|
||||
wantbyte = 0;
|
||||
for (; m != 0; m = m->m_next) {
|
||||
len = m->m_len;
|
||||
if (len == 0)
|
||||
continue;
|
||||
data = mtod(m, u_int8_t *);
|
||||
/* Finish the last word. */
|
||||
if (wantbyte) {
|
||||
savebyte[1] = *data;
|
||||
bus_space_write_2(iot, ioh,
|
||||
asicbase + ED_NOVELL_DATA,
|
||||
*(u_int16_t *)savebyte);
|
||||
data++;
|
||||
len--;
|
||||
wantbyte = 0;
|
||||
}
|
||||
/* Output contiguous words. */
|
||||
if (len > 1) {
|
||||
bus_space_write_multi_2(iot, ioh,
|
||||
asicbase + ED_NOVELL_DATA,
|
||||
(u_int16_t *)data, len >> 1);
|
||||
}
|
||||
/* Save last byte, if necessary. */
|
||||
if (len & 1) {
|
||||
data += len & ~1;
|
||||
savebyte[0] = *data;
|
||||
wantbyte = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (wantbyte) {
|
||||
savebyte[1] = 0;
|
||||
bus_space_write_2(iot, ioh, asicbase + ED_NOVELL_DATA,
|
||||
*(u_int16_t *)savebyte);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for remote DMA complete. This is necessary because on the
|
||||
* transmit side, data is handled internally by the NIC in bursts and
|
||||
* we can't start another remote DMA until this one completes. Not
|
||||
* waiting causes really bad things to happen - like the NIC
|
||||
* irrecoverably jamming the ISA bus.
|
||||
*/
|
||||
while (((NIC_GET(iot, ioh, nicbase, ED_P0_ISR) & ED_ISR_RDC) !=
|
||||
ED_ISR_RDC) && --maxwait);
|
||||
|
||||
if (!maxwait) {
|
||||
log(LOG_WARNING,
|
||||
"%s: remote transmit DMA failed to complete\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
edreset(sc);
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
/*
|
||||
* Given a source and destination address, copy 'amount' of a packet from the
|
||||
* ring buffer into a linear destination buffer. Takes into account ring-wrap.
|
||||
|
|
@ -2441,20 +1965,14 @@ ed_ring_copy(sc, src, dst, amount)
|
|||
tmp_amount = sc->mem_end - src;
|
||||
|
||||
/* Copy amount up to end of NIC memory. */
|
||||
if (sc->mem_shared)
|
||||
ed_shared_readmem(sc, src, dst, tmp_amount);
|
||||
else
|
||||
ed_pio_readmem(sc, (long)src, dst, tmp_amount);
|
||||
ed_shared_readmem(sc, src, dst, tmp_amount);
|
||||
|
||||
amount -= tmp_amount;
|
||||
src = sc->mem_ring;
|
||||
dst += tmp_amount;
|
||||
}
|
||||
|
||||
if (sc->mem_shared)
|
||||
ed_shared_readmem(sc, src, dst, amount);
|
||||
else
|
||||
ed_pio_readmem(sc, (long)src, dst, amount);
|
||||
ed_shared_readmem(sc, src, dst, amount);
|
||||
|
||||
return (src + amount);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: if_edreg.h,v 1.15 1996/01/10 16:49:22 chuck Exp $ */
|
||||
/* $NetBSD: if_edreg.h,v 1.16 1997/10/14 23:04:26 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* National Semiconductor DS8390 NIC register definitions.
|
||||
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
|
||||
#define ED_VENDOR_3COM 0x01 /* 3Com */
|
||||
#define ED_VENDOR_NOVELL 0x02 /* Novell */
|
||||
|
||||
/*
|
||||
* Compile-time config flags
|
||||
|
|
@ -388,31 +387,3 @@
|
|||
* Register File Access LSB
|
||||
*/
|
||||
#define ED_3COM_RFLSB 0x0f
|
||||
|
||||
/*
|
||||
* Definitions for Novell NE1000/2000 boards
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board type codes
|
||||
*/
|
||||
#define ED_TYPE_NE1000 0x01
|
||||
#define ED_TYPE_NE2000 0x02
|
||||
|
||||
/*
|
||||
* Register offsets/total
|
||||
*/
|
||||
#define ED_NOVELL_NIC_OFFSET 0x00
|
||||
#define ED_NOVELL_ASIC_OFFSET 0x10
|
||||
#define ED_NOVELL_IO_PORTS 32
|
||||
|
||||
/*
|
||||
* Remote DMA data register; for reading or writing to the NIC mem via
|
||||
* programmed I/O (offset from ASIC base).
|
||||
*/
|
||||
#define ED_NOVELL_DATA 0x00
|
||||
|
||||
/*
|
||||
* Reset register; reading from this register causes a board reset.
|
||||
*/
|
||||
#define ED_NOVELL_RESET 0x0f
|
||||
|
|
|
|||
Loading…
Reference in New Issue