Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache. PR/55138 

Commented "I think this is bad copy&paste" from skrll@.
No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
This commit is contained in:
tsutsui 2020-06-14 14:16:49 +00:00
parent 98cb956aa1
commit ebe3c25e56
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sys/arch/mips/mips/cache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $ */
/* $NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $");
__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@ -495,11 +495,11 @@ primary_cache_is_2way:
case 32:
/* used internally by mipsNN_picache_sync_range */
mco->mco_intern_icache_sync_range =
cache_r4k_icache_hit_inv_16;
cache_r4k_icache_hit_inv_32;
/* used internally by mipsNN_picache_sync_range_index */
mco->mco_intern_icache_sync_range_index =
cache_r4k_icache_index_inv_16;
cache_r4k_icache_index_inv_32;
break;
default: