Define DECchip 21142/21143 register bits, and since the Macronix chips
are nearly perfect 21143 clones, delete a bunch of redundant info in that section of the file.
This commit is contained in:
thorpej
parent
9a6b48c680
commit
eb16cd3aa7
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@ -1,4 +1,4 @@
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/* $NetBSD: tulipreg.h,v 1.11 1999/09/30 17:41:39 thorpej Exp $ */
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/* $NetBSD: tulipreg.h,v 1.12 1999/11/03 22:22:49 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -445,8 +445,8 @@ struct tulip_desc {
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#define STATUS_RWT 0x00000200 /* receive watchdog timeout */
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#define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed
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(21040) */
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#define STATUS_PMAC_ETI 0x00000400 /* early transmit interrupt */
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#define STATUS_WINB_TEI 0x00000400 /* transmit early interrupt */
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#define STATUS_ETI 0x00000400 /* early transmit interrupt
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(21142/PMAC/Winbond) */
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#define STATUS_FD 0x00000800 /* full duplex short frame
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received (21040) */
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#define STATUS_TM 0x00000800 /* timer expired (21041) */
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@ -488,8 +488,10 @@ struct tulip_desc {
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#define STATUS_EB_PARITY 0x00000000 /* parity errror */
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#define STATUS_EB_MABT 0x00800000 /* master abort */
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#define STATUS_EB_TABT 0x01000000 /* target abort */
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#define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */
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#define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */
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#define STATUS_PMAC_LC 0x08000000 /* 100baseTX link change */
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#define STATUS_LC 0x08000000 /* 100baseTX link change
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(21142/PMAC) */
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#define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */
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@ -545,6 +547,8 @@ struct tulip_desc {
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#define OPMODE_PCS 0x00800000 /* PCS function (21140) */
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#define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */
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#define OPMODE_MBO 0x02000000 /* must be one (21140) */
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#define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB
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(21142) */
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#define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx
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frames (PNIC) */
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#define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */
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@ -630,14 +634,26 @@ struct tulip_desc {
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#define CSR_GPT TULIP_CSR11
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#define GPT_VALUE 0x0000ffff /* timer value */
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#define GPT_CON 0x00010000 /* continuous mode */
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/* 21143-PD and 21143-TD Interrupt Mitigation bits */
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#define GPT_NRX 0x000e0000 /* number of Rx packets */
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#define GPT_RXT 0x00f00000 /* Rx timer */
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#define GPT_NTX 0x07000000 /* number of Tx packets */
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#define GPT_TXT 0x78000000 /* Tx timer */
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#define GPT_CYCLE 0x80000000 /* cycle size */
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/* CSR12 - SIA Status Register (21040, 21041). */
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/* CSR12 - SIA Status Register. */
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#define CSR_SIASTAT TULIP_CSR12
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#define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication
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(21040) */
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#define SIASTAT_MRA 0x00000001 /* MII receive activity
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(21142) */
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#define SIASTAT_NCR 0x00000002 /* network connection error */
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#define SIASTAT_LS100 0x00000002 /* 100baseT link status
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0 == pass (21142) */
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#define SIASTAT_LKF 0x00000004 /* link fail status */
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#define SIASTAT_LS10 0x00000004 /* 10baseT link status
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0 == pass (21142) */
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#define SIASTAT_APS 0x00000008 /* auto polarity status */
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#define SIASTAT_DSD 0x00000010 /* PLL self test done */
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#define SIASTAT_DSP 0x00000020 /* PLL self test pass */
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@ -645,8 +661,12 @@ struct tulip_desc {
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#define SIASTAT_DAO 0x00000080 /* PLL all one */
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#define SIASTAT_SRA 0x00000100 /* selected port receive
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activity (21041) */
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#define SIASTAT_ARA 0x00000100 /* AUI receive activity
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(21142) */
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#define SIASTAT_NRA 0x00000200 /* non-selected port
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receive activity (21041) */
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#define SIASTAT_TRA 0x00000200 /* 10base-T receive activity
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(21142) */
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#define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected
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(21041) */
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#define SIASTAT_TRF 0x00000800 /* transmit remote fault
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@ -658,7 +678,7 @@ struct tulip_desc {
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#define SIASTAT_ANS_ABD 0x00002000 /* ability detect */
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#define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */
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#define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */
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#define SIASTAT_ANS_FPLGOOD 0x00005000 /* FLP link good */
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#define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */
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#define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */
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#define SIASTAT_LPN 0x00008000 /* link partner negotiable
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(21041) */
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@ -667,9 +687,10 @@ struct tulip_desc {
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#define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16)
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/* CSR13 - SIA Connectivity Register (21040, 21041). */
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/* CSR13 - SIA Connectivity Register. */
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#define CSR_SIACONN TULIP_CSR13
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#define SIACONN_SRL 0x00000001 /* SIA reset */
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#define SIACONN_SRL 0x00000001 /* SIA reset
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(0 == reset) */
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#define SIACONN_PS 0x00000002 /* pin AUI/TP selection
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(21040) */
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#define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */
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@ -698,7 +719,7 @@ struct tulip_desc {
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(21041) */
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/* CSR14 - SIA Transmit Receive Register (21040, 21041). */
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/* CSR14 - SIA Transmit Receive Register. */
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#define CSR_SIATXRX TULIP_CSR14
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#define SIATXRX_ECEN 0x00000001 /* encoder enable */
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#define SIATXRX_LBK 0x00000002 /* loopback enable */
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@ -710,8 +731,9 @@ struct tulip_desc {
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#define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */
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#define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */
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#define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */
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#define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */
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#define SIATXRX_ANE 0x00000080 /* autonegotiation enable
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(21041) */
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(21041/21142) */
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#define SIATXRX_RSQ 0x00000100 /* receive squelch enable */
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#define SIATXRX_CSQ 0x00000200 /* collision squelch enable */
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#define SIATXRX_CLD 0x00000400 /* collision detect enable */
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@ -721,10 +743,13 @@ struct tulip_desc {
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#define SIATXRX_APE 0x00002000 /* auto-polarity enable */
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#define SIATXRX_SPP 0x00004000 /* set plarity plus */
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#define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing
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enable (21041) */
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enable (21041/21142) */
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#define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */
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#define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */
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#define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */
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/* CSR15 - SIA General Register (21040, 21041). */
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/* CSR15 - SIA General Register. */
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#define CSR_SIAGEN TULIP_CSR15
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#define SIAGEN_JBD 0x00000001 /* jabber disable */
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#define SIAGEN_HUJ 0x00000002 /* host unjab */
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@ -739,10 +764,23 @@ struct tulip_desc {
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#define SIAGEN_FLF 0x00000400 /* force link fail */
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#define SIAGEN_LSD 0x00000800 /* LED stretch disable
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(21041) */
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#define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */
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#define SIAGEN_DPST 0x00001000 /* PLL self-test start */
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#define SIAGEN_FRL 0x00002000 /* force receiver low */
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#define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */
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#define SIAGEN_RMP 0x00004000 /* received magic packet
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(21143) */
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#define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */
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#define SIAGEN_HCKR 0x00008000 /* hacker (21143) */
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#define SIAGEN_MD 0x000f0000 /* general purpose mode/data */
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#define SIAGEN_LGS 0x00f00000 /* LED/GEP select */
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#define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */
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#define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */
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#define SIAGEN_RME 0x04000000 /* receive match enable */
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#define SIAGEN_CWE 0x08000000 /* control write enable */
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#define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */
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#define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */
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#define SIAGEN_RMI 0x40000000 /* receive match interrupt */
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/* CSR12 - General Purpose Port (21140+). */
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@ -770,15 +808,6 @@ struct tulip_desc {
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#define GPP_PNIC_PIN_LNK100X 3
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/* CSR15 - Watchdog timer (21140+). */
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#define CSR_WATCHDOG TULIP_CSR15
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#define WATCHDOG_JBD 0x00000001 /* jabber disable */
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#define WATCHDOG_HUJ 0x00000002 /* host unjab */
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#define WATCHDOG_JCK 0x00000004 /* jabber clock */
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#define WATCHDOG_RWD 0x00000010 /* receive watchdog disable */
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#define WATCHDOG_RWR 0x00000020 /* receive watchdog release */
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/*
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* Digital Semiconductor 21040 registers.
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*/
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@ -861,7 +890,29 @@ struct tulip_desc {
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* Digital Semiconductor 21142/21143 registers.
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*/
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/* XXX */
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/* SIA configuration for 10baseT (from the 21143 manual) */
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#define SIACONN_21142_10BASET 0x00000001
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#define SIATXRX_21142_10BASET 0x00007f3f
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#define SIAGEN_21142_10BASET 0x00000008
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/* SIA configuration for 10baseT full-duplex (from the 21143 manual) */
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#define SIACONN_21142_10BASET_FDX 0x00000001
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#define SIATXRX_21142_10BASET_FDX 0x00007f3d
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#define SIAGEN_21142_10BASET_FDX 0x00000008
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/* SIA configuration for 10base5 (from the 21143 manual) */
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#define SIACONN_21142_AUI 0x00000009
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#define SIATXRX_21142_AUI 0x00004705
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#define SIAGEN_21142_AUI 0x0000000e
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/* SIA configuration for 10base2 (from the 21143 manual) */
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#define SIACONN_21142_BNC 0x00000009
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#define SIATXRX_21142_BNC 0x00004705
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#define SIAGEN_21142_BNC 0x00000006
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/*
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* Lite-On 82C168/82C169 registers.
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@ -951,53 +1002,33 @@ struct tulip_desc {
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*/
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/* CSR12 - 10base-T Status Port (similar to SIASTAT) */
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/* See SIASTAT 21142/21143 bits */
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#define CSR_PMAC_10TSTAT TULIP_CSR12
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#define PMAC_10TSTAT_LS100 0x00000002 /* link status 100TX
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0 = link up */
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#define PMAC_10TSTAT_LS10 0x00000004 /* link status 10T
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0 = link up */
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#define PMAC_10TSTAT_APS 0x00000008 /* auto polarity status */
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#define PMAC_10TSTAT_TRF 0x00000800 /* transmit remote fault
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(21041) */
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#define PMAC_10TSTAT_ANS 0x00007000 /* autonegotiation state
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(21041) */
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#define PMAC_10TSTAT_ANS_DIS 0x00000000 /* disabled */
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#define PMAC_10TSTAT_ANS_TXDIS 0x00001000 /* transmit disabled */
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#define PMAC_10TSTAT_ANS_ABD 0x00002000 /* ability detect */
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#define PMAC_10TSTAT_ANS_ACKD 0x00003000 /* acknowledge detect */
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#define PMAC_10TSTAT_ANS_ACKC 0x00004000 /* complete acknowledge */
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#define PMAC_10TSTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */
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#define PMAC_10TSTAT_ANS_LINKCHECK 0x00006000 /* link check */
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#define PMAC_10TSTAT_LPN 0x00008000 /* link partner negotiable
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(21041) */
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#define PMAC_10TSTAT_LPC 0xffff0000 /* link partner code word */
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#define PMAC_10TSTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16)
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#define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \
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SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \
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SIASTAT_LPN|SIASTAT_LPC)
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/* CSR13 - NWAY Reset Register */
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#define CSR_PMAC_NWAYRESET TULIP_CSR13
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#define PMAC_NWAYRESET_RESET 0x00000000 /* NWay reset */
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/* See SIACONN 21142/21143 bits */
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#define PMAC_SIACONN_MASK (SIACONN_SRL)
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#define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */
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/* CSR14 - 10base-T Control Port */
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#define CSR_PMAC_10TCTL TULIP_CSR14
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#define PMAC_10TCTL_LBK 0x00000002 /* loopback */
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#define PMAC_10TCTL_PWD10 0x00000004 /* power down 10base-T:
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0 == power down
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1 == normal operation */
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#define PMAC_10TCTL_HDE 0x00000040 /* half-duplex enable */
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#define PMAC_10TCTL_ANE 0x00000080 /* autonegotiation enable */
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#define PMAC_10TCTL_RSQ 0x00000100 /* receive squelch enable */
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#define PMAC_10TCTL_LTE 0x00001000 /* link test enable */
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#define PMAC_10TCTL_TXH 0x00010000 /* adv. 100tx */
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#define PMAC_10TCTL_TXF 0x00020000 /* adv. 100tx-fdx */
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#define PMAC_10TCTL_T4 0x00040000 /* adv. 100t4 */
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/* See SIATXRX 21142/21143 bits */
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#define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \
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SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \
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SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4)
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/* CSR15 - Watchdog Timer Register */
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/* See 21140 CSR15 */
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/* MX98713: see 21140 CSR15 */
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/* others: see SIAGEN 21142/21143 bits */
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#define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \
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SIAGEN_RWD|SIAGEN_RWR)
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/* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */
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