From eae8282d657a6ec112091e9bf10125b98fd87f44 Mon Sep 17 00:00:00 2001 From: martin Date: Sun, 16 Mar 2014 09:34:45 +0000 Subject: [PATCH] Add umcs(4) - a driver for moschip 78{1,2,4}0 based multiport serial adapters. Ported from FreeBSD. --- sys/dev/usb/files.usb | 7 +- sys/dev/usb/umcs.c | 944 ++++++++++++++++++++++++++++++++++ sys/dev/usb/umcs.h | 648 +++++++++++++++++++++++ sys/dev/usb/usbdevices.config | 10 +- 4 files changed, 1605 insertions(+), 4 deletions(-) create mode 100644 sys/dev/usb/umcs.c create mode 100644 sys/dev/usb/umcs.h diff --git a/sys/dev/usb/files.usb b/sys/dev/usb/files.usb index 4d0888a05314..e6dce22f4f9e 100644 --- a/sys/dev/usb/files.usb +++ b/sys/dev/usb/files.usb @@ -1,4 +1,4 @@ -# $NetBSD: files.usb,v 1.130 2013/10/26 09:16:20 nonaka Exp $ +# $NetBSD: files.usb,v 1.131 2014/03/16 09:34:45 martin Exp $ # # Config file and device description for machine-independent USB code. # Included by ports that need it. Ports that use it must provide @@ -327,6 +327,11 @@ device moscom: ucombus attach moscom at usbdevif file dev/usb/moscom.c moscom +# andother driver for the same chip +device umcs: ucombus +attach umcs at usbdevif +file dev/usb/umcs.c umcs + # SUNTAC Slipper U VS-10U driver device uvscom: ucombus attach uvscom at usbdevif diff --git a/sys/dev/usb/umcs.c b/sys/dev/usb/umcs.c new file mode 100644 index 000000000000..e70fb5bca459 --- /dev/null +++ b/sys/dev/usb/umcs.c @@ -0,0 +1,944 @@ +/* $NetBSD: umcs.c,v 1.1 2014/03/16 09:34:45 martin Exp $ */ +/* $FreeBSD: head/sys/dev/usb/serial/umcs.c 260559 2014-01-12 11:44:28Z hselasky $ */ + +/*- + * Copyright (c) 2010 Lev Serebryakov . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * This driver supports several multiport USB-to-RS232 serial adapters driven + * by MosChip mos7820 and mos7840, bridge chips. + * The adapters are sold under many different brand names. + * + * Datasheets are available at MosChip www site at + * http://www.moschip.com. The datasheets don't contain full + * programming information for the chip. + * + * It is nornal to have only two enabled ports in devices, based on + * quad-port mos7840. + * + */ +#include +__KERNEL_RCSID(0, "$NetBSD: umcs.c,v 1.1 2014/03/16 09:34:45 martin Exp $"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "umcs.h" + +#if 0 +#define DPRINTF(ARG) printf ARG +#else +#define DPRINTF(ARG) +#endif + +/* + * Two-port devices (both with 7820 chip and 7840 chip configured as two-port) + * have ports 0 and 2, with ports 1 and 3 omitted. + * So, PHYSICAL port numbers on two-port device will be 0 and 2. + * + * We use an array of the following struct, indexed by ucom port index, + * and include the physical port number in it. + */ +struct umcs7840_softc_oneport { + device_t sc_port_ucom; /* ucom subdevice */ + uint32_t sc_port_changed; /* call ucom_status_change() */ + unsigned int sc_port_phys; /* physical port number */ + uint8_t sc_port_lcr; /* local line control register */ + uint8_t sc_port_mcr; /* local modem control register */ +}; + +struct umcs7840_softc { + device_t sc_dev; /* ourself */ + usbd_interface_handle sc_iface; /* the usb interface */ + usbd_device_handle sc_udev; /* the usb device */ + usbd_pipe_handle sc_intr_pipe; /* interrupt pipe */ + usbd_xfer_handle sc_intr_xfer; /* and preallocated xfer */ + uint8_t *sc_intr_buf; /* buffer for interrupt xfer */ + struct workqueue *sc_change_wq; /* workqueue for status changes */ + struct work sc_work; /* work for said workqueue. */ + struct umcs7840_softc_oneport sc_ports[UMCS7840_MAX_PORTS]; + /* data for each port */ + uint8_t sc_numports; /* number of ports (subunits) */ + bool sc_init_done; /* special one time init in open */ + bool sc_dying; /* we have been deactivated */ +}; + +static int umcs7840_get_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data); +static int umcs7840_set_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t data); +static int umcs7840_get_UART_reg(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t *data); +static int umcs7840_set_UART_reg(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data); +static int umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk); +static void umcs7840_dtr(struct umcs7840_softc *sc, int portno, bool onoff); +static void umcs7840_rts(struct umcs7840_softc *sc, int portno, bool onoff); +static void umcs7840_break(struct umcs7840_softc *sc, int portno, bool onoff); + +static int umcs7840_match(device_t, cfdata_t, void *); +static void umcs7840_attach(device_t, device_t, void *); +static int umcs7840_detach(device_t, int); +static void umcs7840_intr(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status); +static void umcs7840_change_worker(struct work *w, void *arg); +static int umcs7840_activate(device_t, enum devact); +static void umcs7840_childdet(device_t, device_t); + +static void umcs7840_get_status(void *, int, u_char *, u_char *); +static void umcs7840_set(void *, int, int, int); +static int umcs7840_param(void *, int, struct termios *); +static int umcs7840_port_open(void *sc, int portno); +static void umcs7840_port_close(void *sc, int portno); + +struct ucom_methods umcs7840_methods = { + umcs7840_get_status, + umcs7840_set, + umcs7840_param, + NULL, + umcs7840_port_open, + umcs7840_port_close, +}; + +static const struct usb_devno umcs7840_devs[] = { + { USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7703 }, + { USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7810 }, + { USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7820 }, + { USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7840 }, + { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC2324 } +}; +#define umcs7840_lookup(v, p) usb_lookup(umcs7840_devs, v, p) + +CFATTACH_DECL2_NEW(umcs, sizeof(struct umcs7840_softc), umcs7840_match, + umcs7840_attach, umcs7840_detach, umcs7840_activate, NULL, + umcs7840_childdet); + +static inline int +umcs7840_reg_sp(int phyport) +{ + KASSERT(phyport >= 0 && phyport < 4); + switch (phyport) { + default: + case 0: return MCS7840_DEV_REG_SP1; + case 1: return MCS7840_DEV_REG_SP2; + case 2: return MCS7840_DEV_REG_SP3; + case 3: return MCS7840_DEV_REG_SP4; + } +} + +static inline int +umcs7840_reg_ctrl(int phyport) +{ + KASSERT(phyport >= 0 && phyport < 4); + switch (phyport) { + default: + case 0: return MCS7840_DEV_REG_CONTROL1; + case 1: return MCS7840_DEV_REG_CONTROL2; + case 2: return MCS7840_DEV_REG_CONTROL3; + case 3: return MCS7840_DEV_REG_CONTROL4; + } +} + +static inline int +umcs7840_reg_dcr0(int phyport) +{ + KASSERT(phyport >= 0 && phyport < 4); + switch (phyport) { + default: + case 0: return MCS7840_DEV_REG_DCR0_1; + case 1: return MCS7840_DEV_REG_DCR0_2; + case 2: return MCS7840_DEV_REG_DCR0_3; + case 3: return MCS7840_DEV_REG_DCR0_4; + } +} + +static int +umcs7840_match(device_t dev, cfdata_t match, void *aux) +{ + struct usb_attach_arg *uaa = aux; + + return (umcs7840_lookup(uaa->vendor, uaa->product) != NULL ? + UMATCH_VENDOR_PRODUCT : UMATCH_NONE); +} + +static void +umcs7840_attach(device_t parent, device_t self, void * aux) +{ + struct umcs7840_softc *sc = device_private(self); + struct usb_attach_arg *uaa = aux; + usbd_device_handle dev = uaa->device; + usb_interface_descriptor_t *id; + usb_endpoint_descriptor_t *ed; + char *devinfop; + struct ucom_attach_args uca; + int error, i, intr_addr; + uint8_t data; + uint16_t isize; + + sc->sc_dev = self; + sc->sc_udev = uaa->device; + + if (usbd_set_config_index(sc->sc_udev, MCS7840_CONFIG_INDEX, 1) != 0) { + aprint_error(": could not set configuration no\n"); + return; + } + + /* get the first interface handle */ + error = usbd_device2interface_handle(sc->sc_udev, MCS7840_IFACE_INDEX, + &sc->sc_iface); + if (error != 0) { + aprint_error(": could not get interface handle\n"); + return; + } + + /* + * Get number of ports + * Documentation (full datasheet) says, that number of ports is + * set as MCS7840_DEV_MODE_SELECT24S bit in MODE R/Only + * register. But vendor driver uses these undocumented + * register & bit. + * + * Experiments show, that MODE register can have `0' + * (4 ports) bit on 2-port device, so use vendor driver's way. + * + * Also, see notes in header file for these constants. + */ + umcs7840_get_reg(sc, MCS7840_DEV_REG_GPIO, &data); + if (data & MCS7840_DEV_GPIO_4PORTS) { + sc->sc_numports = 4; + /* physical port no are : 0, 1, 2, 3 */ + } else { + if (uaa->product == USB_PRODUCT_MOSCHIP_MCS7810) + sc->sc_numports = 1; + else { + sc->sc_numports = 2; + /* physical port no are : 0 and 2 */ + } + } + devinfop = usbd_devinfo_alloc(dev, 0); + aprint_normal(": %s\n", devinfop); + usbd_devinfo_free(devinfop); + aprint_verbose_dev(self, "found %d active ports\n", sc->sc_numports); + + if (!umcs7840_get_reg(sc, MCS7840_DEV_REG_MODE, &data)) { + aprint_verbose_dev(self, "On-die confguration: RST: active %s, " + "HRD: %s, PLL: %s, POR: %s, Ports: %s, EEPROM write %s, " + "IrDA is %savailable\n", + (data & MCS7840_DEV_MODE_RESET) ? "low" : "high", + (data & MCS7840_DEV_MODE_SER_PRSNT) ? "yes" : "no", + (data & MCS7840_DEV_MODE_PLLBYPASS) ? "bypassed" : "avail", + (data & MCS7840_DEV_MODE_PORBYPASS) ? "bypassed" : "avail", + (data & MCS7840_DEV_MODE_SELECT24S) ? "2" : "4", + (data & MCS7840_DEV_MODE_EEPROMWR) ? "enabled" : "disabled", + (data & MCS7840_DEV_MODE_IRDA) ? "" : "not "); + } + + /* + * Set up the interrupt pipe + */ + id = usbd_get_interface_descriptor(sc->sc_iface); + isize = 0; + intr_addr = -1; + for (i = 0 ; i < id->bNumEndpoints ; i++) { + ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); + if (ed == NULL) continue; + if (UE_GET_DIR(ed->bEndpointAddress) != UE_DIR_IN + || UE_GET_XFERTYPE(ed->bmAttributes) != UE_INTERRUPT) + continue; + isize = UGETW(ed->wMaxPacketSize); + intr_addr = ed->bEndpointAddress; + break; + } + if (intr_addr < 0) { + aprint_error_dev(self, "interrupt pipe not found\n"); + return; + } + sc->sc_intr_buf = malloc(isize, M_USBDEV, M_WAITOK); + + error = usbd_open_pipe_intr(sc->sc_iface, intr_addr, + USBD_SHORT_XFER_OK, &sc->sc_intr_pipe, sc, sc->sc_intr_buf, + isize, umcs7840_intr, 100); + if (error) { + aprint_error_dev(self, "cannot open interrupt pipe " + "(addr %d)\n", intr_addr); + return; + } + + sc->sc_intr_xfer = usbd_alloc_xfer(uaa->device); + if (sc->sc_intr_xfer == NULL) { + aprint_error_dev(self, "alloc intr xfer failed\n"); + return; + } + if (workqueue_create(&sc->sc_change_wq, "umcsq", + umcs7840_change_worker, sc, PRI_NONE, IPL_USB, WQ_MPSAFE)) { + aprint_error_dev(self, "workqueue creation failed\n"); + return; + } + + usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, + sc->sc_dev); + + memset(&uca, 0, sizeof uca); + uca.ibufsize = 256; + uca.obufsize = 256; + uca.ibufsizepad = 256; + uca.opkthdrlen = 0; + uca.device = sc->sc_udev; + uca.iface = sc->sc_iface; + uca.methods = &umcs7840_methods; + uca.arg = sc; + + for (i = 0; i < sc->sc_numports; i++) { + uca.bulkin = uca.bulkout = -1; + + /* + * On four port cards, endpoints are 0/1 for first, + * 2/3 for second, ... + * On two port cards, they are 0/1 for first, 4/5 for second. + * On single port, just 0/1 will be used. + */ + int phyport = i * (sc->sc_numports == 2 ? 2 : 1); + + ed = usbd_interface2endpoint_descriptor(sc->sc_iface, + phyport*2); + if (ed == NULL) { + aprint_error_dev(self, + "no bulk in endpoint found for %d\n", i); + return; + } + uca.bulkin = ed->bEndpointAddress; + + ed = usbd_interface2endpoint_descriptor(sc->sc_iface, + phyport*2 + 1); + if (ed == NULL) { + aprint_error_dev(self, + "no bulk out endpoint found for %d\n", i); + return; + } + uca.bulkout = ed->bEndpointAddress; + uca.portno = i; + DPRINTF(("port %d physical port %d bulk-in %d bulk-out %d\n", + i, phyport, uca.bulkin, uca.bulkout)); + + sc->sc_ports[i].sc_port_phys = phyport; + sc->sc_ports[i].sc_port_ucom = + config_found_sm_loc(self, "ucombus", NULL, &uca, + ucomprint, ucomsubmatch); + } +} + +static int +umcs7840_get_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data) +{ + usb_device_request_t req; + int err; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = MCS7840_RDREQ; + USETW(req.wValue, 0); + USETW(req.wIndex, reg); + USETW(req.wLength, UMCS7840_READ_LENGTH); + + err = usbd_do_request(sc->sc_udev, &req, data); + if (err) + aprint_normal_dev(sc->sc_dev, + "Reading register %d failed: %s\n", reg, usbd_errstr(err)); + return err; +} + +static int +umcs7840_set_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t data) +{ + usb_device_request_t req; + int err; + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = MCS7840_WRREQ; + USETW(req.wValue, data); + USETW(req.wIndex, reg); + USETW(req.wLength, 0); + + err = usbd_do_request(sc->sc_udev, &req, 0); + if (err) + aprint_normal_dev(sc->sc_dev, "Writing register %d failed: %s\n", reg, usbd_errstr(err)); + + return err; +} + +static int +umcs7840_get_UART_reg(struct umcs7840_softc *sc, uint8_t portno, + uint8_t reg, uint8_t *data) +{ + usb_device_request_t req; + uint16_t wVal; + int err; + + /* portno is port number */ + wVal = ((uint16_t)(portno + 1)) << 8; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = MCS7840_RDREQ; + USETW(req.wValue, wVal); + USETW(req.wIndex, reg); + USETW(req.wLength, UMCS7840_READ_LENGTH); + + err = usbd_do_request(sc->sc_udev, &req, data); + if (err) + aprint_normal_dev(sc->sc_dev, "Reading UART %d register %d failed: %s\n", portno, reg, usbd_errstr(err)); + return err; +} + +static int +umcs7840_set_UART_reg(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data) +{ + usb_device_request_t req; + int err; + uint16_t wVal; + + /* portno is the physical port number */ + wVal = ((uint16_t)(portno + 1)) << 8 | data; + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = MCS7840_WRREQ; + USETW(req.wValue, wVal); + USETW(req.wIndex, reg); + USETW(req.wLength, 0); + + err = usbd_do_request(sc->sc_udev, &req, NULL); + if (err) + device_printf(sc->sc_dev, "Writing UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err)); + return err; +} + +static int +umcs7840_set_baudrate(struct umcs7840_softc *sc, uint8_t portno, uint32_t rate) +{ + int err; + uint16_t divisor; + uint8_t clk; + uint8_t data; + uint8_t physport = sc->sc_ports[portno].sc_port_phys; + int spreg = umcs7840_reg_sp(physport); + + if (umcs7840_calc_baudrate(rate, &divisor, &clk)) { + DPRINTF(("Port %d bad speed: %d\n", portno, rate)); + return (-1); + } + if (divisor == 0 || (clk & MCS7840_DEV_SPx_CLOCK_MASK) != clk) { + DPRINTF(("Port %d bad speed calculation: %d\n", portno, rate)); + return (-1); + } + DPRINTF(("Port %d set speed: %d (%02x / %d)\n", portno, rate, clk, divisor)); + + /* Set clock source for standard BAUD frequences */ + err = umcs7840_get_reg(sc, spreg, &data); + if (err) + return err; + data &= MCS7840_DEV_SPx_CLOCK_MASK; + data |= clk; + err = umcs7840_set_reg(sc, spreg, data); + if (err) + return err; + + /* Set divider */ + sc->sc_ports[portno].sc_port_lcr |= MCS7840_UART_LCR_DIVISORS; + err = umcs7840_set_UART_reg(sc, physport, MCS7840_UART_REG_LCR, sc->sc_ports[portno].sc_port_lcr); + if (err) + return err; + + err = umcs7840_set_UART_reg(sc, physport, MCS7840_UART_REG_DLL, (uint8_t)(divisor & 0xff)); + if (err) + return err; + err = umcs7840_set_UART_reg(sc, physport, MCS7840_UART_REG_DLM, (uint8_t)((divisor >> 8) & 0xff)); + if (err) + return err; + + /* Turn off access to DLL/DLM registers of UART */ + sc->sc_ports[portno].sc_port_lcr &= ~MCS7840_UART_LCR_DIVISORS; + err = umcs7840_set_UART_reg(sc, physport, MCS7840_UART_REG_LCR, sc->sc_ports[portno].sc_port_lcr); + if (err) + return err; + return (0); +} + +static int +umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk) +{ + /* Maximum speeds for standard frequences, when PLL is not used */ + static const uint32_t umcs7840_baudrate_divisors[] = + {0, 115200, 230400, 403200, 460800, 806400, 921600, + 1572864, 3145728,}; + static const uint8_t umcs7840_baudrate_divisors_len = + __arraycount(umcs7840_baudrate_divisors); + uint8_t i = 0; + + if (rate > umcs7840_baudrate_divisors[umcs7840_baudrate_divisors_len - 1]) + return (-1); + + for (i = 0; i < umcs7840_baudrate_divisors_len - 1 + && !(rate > umcs7840_baudrate_divisors[i] + && rate <= umcs7840_baudrate_divisors[i + 1]); ++i); + *divisor = umcs7840_baudrate_divisors[i + 1] / rate; + /* 0x00 .. 0x70 */ + *clk = i << MCS7840_DEV_SPx_CLOCK_SHIFT; + return (0); +} + +static int +umcs7840_detach(device_t self, int flags) +{ + struct umcs7840_softc *sc = device_private(self); + int rv = 0, i; + + /* close interrupt pipe */ + if (sc->sc_intr_pipe != NULL) { + rv = usbd_abort_pipe(sc->sc_intr_pipe); + if (rv) + aprint_error_dev(sc->sc_dev, + "abort interrupt pipe failed: %s\n", + usbd_errstr(rv)); + rv = usbd_close_pipe(sc->sc_intr_pipe); + if (rv) + aprint_error_dev(sc->sc_dev, + "close interrupt pipe failed: %s\n", + usbd_errstr(rv)); + free(sc->sc_intr_buf, M_USBDEV); + sc->sc_intr_pipe = NULL; + } + if (sc->sc_change_wq != NULL) + workqueue_destroy(sc->sc_change_wq); + + for (i = 0; i < sc->sc_numports; i++) { + if (sc->sc_ports[i].sc_port_ucom) { + rv = config_detach(sc->sc_ports[i].sc_port_ucom, + flags); + if (rv) + break; + } + } + + usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, + sc->sc_dev); + + return rv; +} + +int +umcs7840_activate(device_t self, enum devact act) +{ + struct umcs7840_softc *sc = device_private(self); + + switch (act) { + case DVACT_DEACTIVATE: + sc->sc_dying = true; + return 0; + default: + return EOPNOTSUPP; + } +} + +static void +umcs7840_childdet(device_t self, device_t child) +{ + struct umcs7840_softc *sc = device_private(self); + int i; + + for (i = 0; i < sc->sc_numports; i++) { + if (child == sc->sc_ports[i].sc_port_ucom) { + sc->sc_ports[i].sc_port_ucom = NULL; + return; + } + } +} + +static void +umcs7840_get_status(void *self, int portno, u_char *lsr, u_char *msr) +{ + struct umcs7840_softc *sc = self; + uint8_t pn = sc->sc_ports[portno].sc_port_phys; + uint8_t hw_lsr = 0; /* local line status register */ + uint8_t hw_msr = 0; /* local modem status register */ + + /* Read LSR & MSR */ + umcs7840_get_UART_reg(sc, pn, MCS7840_UART_REG_LSR, &hw_lsr); + umcs7840_get_UART_reg(sc, pn, MCS7840_UART_REG_MSR, &hw_msr); + + *lsr = hw_lsr; + *msr = hw_msr; +} + +static void +umcs7840_set(void *self, int portno, int reg, int onoff) +{ + struct umcs7840_softc *sc = self; + int pn = sc->sc_ports[portno].sc_port_phys; + + if (sc->sc_dying) + return; + + switch (reg) { + case UCOM_SET_DTR: + umcs7840_dtr(sc, pn, onoff); + break; + case UCOM_SET_RTS: + umcs7840_rts(sc, pn, onoff); + break; + case UCOM_SET_BREAK: + umcs7840_break(sc, pn, onoff); + break; + default: + break; + } +} + +static int +umcs7840_param(void *self, int portno, struct termios *t) +{ + struct umcs7840_softc *sc = self; + int pn = sc->sc_ports[portno].sc_port_phys; + uint8_t lcr = sc->sc_ports[portno].sc_port_lcr; + uint8_t mcr = sc->sc_ports[portno].sc_port_mcr; + + if (t->c_cflag & CSTOPB) { + lcr |= MCS7840_UART_LCR_STOPB2; + } else { + lcr |= MCS7840_UART_LCR_STOPB1; + } + + lcr &= ~MCS7840_UART_LCR_PARITYMASK; + if (t->c_cflag & PARENB) { + lcr |= MCS7840_UART_LCR_PARITYON; + if (t->c_cflag & PARODD) { + lcr = MCS7840_UART_LCR_PARITYODD; + } else { + lcr = MCS7840_UART_LCR_PARITYEVEN; + } + } else { + lcr &= ~MCS7840_UART_LCR_PARITYON; + } + + lcr &= ~MCS7840_UART_LCR_DATALENMASK; + switch (t->c_cflag & CSIZE) { + case CS5: + lcr |= MCS7840_UART_LCR_DATALEN5; + break; + case CS6: + lcr |= MCS7840_UART_LCR_DATALEN6; + break; + case CS7: + lcr |= MCS7840_UART_LCR_DATALEN7; + break; + case CS8: + lcr |= MCS7840_UART_LCR_DATALEN8; + break; + } + + if (t->c_cflag & CRTSCTS) + mcr |= MCS7840_UART_MCR_CTSRTS; + else + mcr &= ~MCS7840_UART_MCR_CTSRTS; + + if (t->c_cflag & CLOCAL) + mcr &= ~MCS7840_UART_MCR_DTRDSR; + else + mcr |= MCS7840_UART_MCR_DTRDSR; + + sc->sc_ports[portno].sc_port_lcr = lcr; + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_LCR, + sc->sc_ports[pn].sc_port_lcr); + + sc->sc_ports[portno].sc_port_mcr = mcr; + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_MCR, + sc->sc_ports[pn].sc_port_mcr); + + if (umcs7840_set_baudrate(sc, pn, t->c_ospeed)) + return EIO; + + return 0; +} + +static void +umcs7840_dtr(struct umcs7840_softc *sc, int portno, bool onoff) +{ + int pn = sc->sc_ports[portno].sc_port_phys; + uint8_t mcr = sc->sc_ports[portno].sc_port_mcr; + + if (onoff) + mcr |= MCS7840_UART_MCR_DTR; + else + mcr &= ~MCS7840_UART_MCR_DTR; + + sc->sc_ports[portno].sc_port_mcr = mcr; + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_MCR, + sc->sc_ports[pn].sc_port_mcr); +} + +static void +umcs7840_rts(struct umcs7840_softc *sc, int portno, bool onoff) +{ + int pn = sc->sc_ports[portno].sc_port_phys; + uint8_t mcr = sc->sc_ports[portno].sc_port_mcr; + + if (onoff) + mcr |= MCS7840_UART_MCR_RTS; + else + mcr &= ~MCS7840_UART_MCR_RTS; + + sc->sc_ports[portno].sc_port_mcr = mcr; + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_MCR, + sc->sc_ports[pn].sc_port_mcr); +} + +static void +umcs7840_break(struct umcs7840_softc *sc, int portno, bool onoff) +{ + int pn = sc->sc_ports[portno].sc_port_phys; + uint8_t lcr = sc->sc_ports[portno].sc_port_lcr; + + if (onoff) + lcr |= MCS7840_UART_LCR_BREAK; + else + lcr &= ~MCS7840_UART_LCR_BREAK; + + sc->sc_ports[portno].sc_port_lcr = lcr; + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_LCR, + sc->sc_ports[pn].sc_port_lcr); +} + +static int +umcs7840_port_open(void *self, int portno) +{ + struct umcs7840_softc *sc = self; + int pn = sc->sc_ports[portno].sc_port_phys; + int spreg = umcs7840_reg_sp(pn); + int ctrlreg = umcs7840_reg_ctrl(pn); + uint8_t data; + + if (sc->sc_dying) + return EIO; + + /* If it very first open, finish global configuration */ + if (!sc->sc_init_done) { + if (umcs7840_get_reg(sc, MCS7840_DEV_REG_CONTROL1, &data)) + return EIO; + data |= MCS7840_DEV_CONTROL1_DRIVER_DONE; + if (umcs7840_set_reg(sc, MCS7840_DEV_REG_CONTROL1, data)) + return EIO; + sc->sc_init_done = 1; + } + + /* Toggle reset bit on-off */ + if (umcs7840_get_reg(sc, spreg, &data)) + return EIO; + data |= MCS7840_DEV_SPx_UART_RESET; + if (umcs7840_set_reg(sc, spreg, data)) + return EIO; + data &= ~MCS7840_DEV_SPx_UART_RESET; + if (umcs7840_set_reg(sc, spreg, data)) + return EIO; + + /* Set RS-232 mode */ + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_SCRATCHPAD, + MCS7840_UART_SCRATCHPAD_RS232)) + return EIO; + + /* Disable RX on time of initialization */ + if (umcs7840_get_reg(sc, ctrlreg, &data)) + return EIO; + data |= MCS7840_DEV_CONTROLx_RX_DISABLE; + if (umcs7840_set_reg(sc, ctrlreg, data)) + return EIO; + + /* Disable all interrupts */ + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_IER, 0)) + return EIO; + + /* Reset FIFO -- documented */ + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_FCR, 0)) + return EIO; + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_FCR, + MCS7840_UART_FCR_ENABLE | MCS7840_UART_FCR_FLUSHRHR | + MCS7840_UART_FCR_FLUSHTHR | MCS7840_UART_FCR_RTL_1_14)) + return EIO; + + /* Set 8 bit, no parity, 1 stop bit -- documented */ + sc->sc_ports[pn].sc_port_lcr = + MCS7840_UART_LCR_DATALEN8 | MCS7840_UART_LCR_STOPB1; + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_LCR, + sc->sc_ports[pn].sc_port_lcr)) + return EIO; + + /* + * Enable DTR/RTS on modem control, enable modem interrupts -- + * documented + */ + sc->sc_ports[pn].sc_port_mcr = MCS7840_UART_MCR_DTR + | MCS7840_UART_MCR_RTS | MCS7840_UART_MCR_IE; + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_MCR, + sc->sc_ports[pn].sc_port_mcr)) + return EIO; + + /* Clearing Bulkin and Bulkout FIFO */ + if (umcs7840_get_reg(sc, spreg, &data)) + return EIO; + data |= MCS7840_DEV_SPx_RESET_OUT_FIFO | MCS7840_DEV_SPx_RESET_IN_FIFO; + if (umcs7840_set_reg(sc, spreg, data)) + return EIO; + data &= ~(MCS7840_DEV_SPx_RESET_OUT_FIFO + | MCS7840_DEV_SPx_RESET_IN_FIFO); + if (umcs7840_set_reg(sc, spreg, data)) + return EIO; + + /* Set speed 9600 */ + if (umcs7840_set_baudrate(sc, pn, 9600)) + return EIO; + + + /* Finally enable all interrupts -- documented */ + /* + * Copied from vendor driver, I don't know why we should read LCR + * here + */ + if (umcs7840_get_UART_reg(sc, pn, MCS7840_UART_REG_LCR, + &sc->sc_ports[pn].sc_port_lcr)) + return EIO; + if (umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_IER, + MCS7840_UART_IER_RXSTAT | MCS7840_UART_IER_MODEM)) + return EIO; + + /* Enable RX */ + if (umcs7840_get_reg(sc, ctrlreg, &data)) + return EIO; + data &= ~MCS7840_DEV_CONTROLx_RX_DISABLE; + if (umcs7840_set_reg(sc, ctrlreg, data)) + return EIO; + return 0; +} + +static void +umcs7840_port_close(void *self, int portno) +{ + struct umcs7840_softc *sc = self; + int pn = sc->sc_ports[portno].sc_port_phys; + int ctrlreg = umcs7840_reg_ctrl(pn); + uint8_t data; + + atomic_swap_32(&sc->sc_ports[portno].sc_port_changed, 0); + + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_MCR, 0); + umcs7840_set_UART_reg(sc, pn, MCS7840_UART_REG_IER, 0); + + /* Disable RX */ + if (umcs7840_get_reg(sc, ctrlreg, &data)) + return; + data |= MCS7840_DEV_CONTROLx_RX_DISABLE; + if (umcs7840_set_reg(sc, ctrlreg, data)) + return; +} + +static void +umcs7840_intr(usbd_xfer_handle xfer, usbd_private_handle priv, + usbd_status status) +{ + struct umcs7840_softc *sc = priv; + u_char *buf = sc->sc_intr_buf; + int actlen; + int subunit, found; + + if (sc->sc_dying) + return; + + found = 0; + if (status != USBD_NORMAL_COMPLETION) { + if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) + return; + + aprint_error_dev(sc->sc_dev, + "umcs7840_intr: abnormal status: %s\n", + usbd_errstr(status)); + usbd_clear_endpoint_stall_async(sc->sc_intr_pipe); + return; + } + + usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); + if (actlen == 5 || actlen == 13) { + /* Check status of all ports */ + for (subunit = 0; subunit < sc->sc_numports; subunit++) { + uint8_t pn = sc->sc_ports[subunit].sc_port_phys; + if (buf[pn] & MCS7840_UART_ISR_NOPENDING) + continue; + DPRINTF(("Port %d has pending interrupt: %02x " + "(FIFO: %02x)\n", pn, + buf[pn] & MCS7840_UART_ISR_INTMASK, + buf[pn] & (~MCS7840_UART_ISR_INTMASK))); + switch (buf[pn] & MCS7840_UART_ISR_INTMASK) { + case MCS7840_UART_ISR_RXERR: + case MCS7840_UART_ISR_RXHASDATA: + case MCS7840_UART_ISR_RXTIMEOUT: + case MCS7840_UART_ISR_MSCHANGE: + atomic_swap_32( + &sc->sc_ports[subunit].sc_port_changed, + 1); + found++; + break; + default: + /* Do nothing */ + break; + } + } + if (found) + workqueue_enqueue(sc->sc_change_wq, &sc->sc_work, + NULL); + } else { + device_printf(sc->sc_dev, "Invalid interrupt data length %d", + actlen); + } +} + +static void +umcs7840_change_worker(struct work *w, void *arg) +{ + struct umcs7840_softc *sc = arg; + int i; + + for (i = 0; i < sc->sc_numports; i++) { + if (sc->sc_ports[i].sc_port_changed) { + ucom_status_change(device_private( + sc->sc_ports[i].sc_port_ucom)); + atomic_swap_32(&sc->sc_ports[i].sc_port_changed, 0); + } + } +} diff --git a/sys/dev/usb/umcs.h b/sys/dev/usb/umcs.h new file mode 100644 index 000000000000..9c2a2205405a --- /dev/null +++ b/sys/dev/usb/umcs.h @@ -0,0 +1,648 @@ +/* $NetBSD: umcs.h,v 1.1 2014/03/16 09:34:45 martin Exp $ */ +/* $FreeBSD: head/sys/dev/usb/serial/umcs.h 252123 2013-06-23 20:19:51Z thomas $ */ + +/*- + * Copyright (c) 2010 Lev Serebryakov . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _UMCS7840_H_ +#define _UMCS7840_H_ + +#define UMCS7840_MAX_PORTS 4 + +#define UMCS7840_READ_LENGTH 1 /* bytes */ +#define UMCS7840_CTRL_TIMEOUT 500 /* ms */ + +/* Read/Wrtire registers vendor commands */ +#define MCS7840_RDREQ 0x0d +#define MCS7840_WRREQ 0x0e + +/* Read/Wrtie EEPROM values */ +#define MCS7840_EEPROM_RW_WVALUE 0x0900 + +/* + * All these registers are documented only in full datasheet, + * which can be requested from MosChip tech support. + */ +#define MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */ +#define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1, + * R/W */ +#define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong + * register, R/W */ +#define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong + * register, R/W */ +/* DCRx_1 Registers goes here (see below, they are documented) */ +#define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, + * undocumented, see notes + * below R/W */ +#define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */ +#define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2, + * R/W */ +#define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */ +#define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3, + * R/W */ +#define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */ +#define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4, + * R/W */ +#define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ +#define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ +#define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt + * endpoint control, R/W */ +#define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 & + * 2, R/W */ +#define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 & + * 4, R/W */ +#define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ +/* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ +#define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ +#define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration, + * R/Only */ +#define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap + * configuration for Port 1, + * R/W */ +#define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap + * configuration for Port 2, + * R/W */ +#define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap + * configuration for Port 3, + * R/W */ +#define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap + * configuration for Port 4, + * R/W */ +#define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & + * 2, R/W */ +#define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & + * 4, R/W */ +#define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port + * 1, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port + * 1, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port + * 2, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port + * 2, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port + * 3, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port + * 3, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port + * 4, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port + * 4, contains number of + * availiable bytes, R/Only */ +#define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out + * frames for Port 1, R/W */ +#define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out + * frames for Port 1, R/W */ +#define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out + * frames for Port 1, R/W */ +#define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out + * frames for Port 1, R/W */ +#define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out + * frames, R/W */ +#define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshhold + * value for Bulk-Out for Port + * 1, R/W */ +#define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshhold + * value for Bulk-Out and + * enable flag for Port 1, R/W */ +#define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshhold + * value for Bulk-Out for Port + * 2, R/W */ +#define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshhold + * value for Bulk-Out and + * enable flag for Port 2, R/W */ +#define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshhold + * value for Bulk-Out for Port + * 3, R/W */ +#define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshhold + * value for Bulk-Out and + * enable flag for Port 3, R/W */ +#define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshhold + * value for Bulk-Out for Port + * 4, R/W */ +#define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshhold + * value for Bulk-Out and + * enable flag for Port 4, R/W */ + +/* Bits for SPx registers */ +#define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the + * Bulk-In FIFO, default = 0 */ +#define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART, + * which were recevied with + * errors, default = 0 */ +#define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ +#define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ +#define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK + * source */ +#define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed + * = 115200 bps, default */ +#define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed + * = 230400 bps */ +#define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed + * = 403200 bps */ +#define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed + * = 460800 bps */ +#define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed + * = 806400 bps */ +#define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed + * = 921600 bps */ +#define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed + * = 1.5 Mbps */ +#define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed + * = 3.0 Mbps */ +#define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted + * to get clock value */ +#define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */ + +/* Bits for CONTROLx registers */ +#define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow + * control (when power + * down? It is unclear + * in documents), + * default = 0 */ +#define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */ +#define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are + * translated to MSR, + * default = 0 */ +#define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports + * 2,3,4 */ +#define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is + * finished, USB + * enumeration memory + * can be used as FIFOs */ +#define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input, + * works for IrDA mode + * only, default = 0 */ +#define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic, + * works only for + * RS-232/RS-485 mode, + * default = 0 */ +#define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when + * TX is in progress, + * works for IrDA mode + * only, default = 0 */ +#define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */ + +/* + * Bits for PINPONGx registers + * These registers control how often two input buffers + * for Bulk-In FIFOs are swapped. One of buffers is used + * for USB trnasfer, other for receiving data from UART. + * Exact meaning of 15 bit value in these registers is unknown + */ +#define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW + * register */ +#define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW + * register */ + +/* + * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support + * confirms, that it is register for GPIO_0 and GPIO_1 data input/output. + * Chips has 2 GPIO, but first one (lower bit) MUST be used by device + * authors as "number of port" indicator, grounded (0) for two-port + * devices and pulled-up to 1 for 4-port devices. + */ +#define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports + * configured */ +#define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */ +#define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */ + +/* + * Constants for PLL dividers + * Ouptut frequency of PLL is: + * Fout = (N/M) * Fin. + * Default PLL input frequency Fin is 12Mhz (on-chip). + */ +#define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M + * divider */ +#define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ +#define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is + * forbidden */ +#define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */ +#define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */ +#define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N + * divider */ +#define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ +#define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is + * forbidden */ +#define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */ +#define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */ + +/* Bits for CLOCK_MUX register */ +#define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock + * input */ +#define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ +#define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended) + * PLL input */ +#define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */ +#define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */ +#define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is + * 20MHz-100MHz (default), 1 = + * 100MHz-300MHz range */ +#define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes + * fro Interrupt USB pipe with + * USB FIFOs statuses, default + * = 0 */ +#define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */ +#define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */ +#define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */ +#define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */ + +/* Bits for CLOCK_SELECTxx registers */ +#define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in + * CLOCK_SELECT12 */ +#define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in + * CLOCK_SELECT12 */ +#define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in + * CLOCK_SELECT12 */ +#define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in + * CLOCK_SELECT12 */ +#define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in + * CLOCK_SELECT23 */ +#define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in + * CLOCK_SELECT23 */ +#define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in + * CLOCK_SELECT23 */ +#define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in + * CLOCK_SELECT23 */ +#define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived + * from 96Mhz, default for all + * ports */ +#define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */ +#define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */ +#define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */ +#define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N + * dividers) */ +#define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input + * (device-dependend) */ +#define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */ +#define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */ + +/* Bits for MODE register */ +#define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */ +#define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High + * (default), 1: Reserved (?) */ +#define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use + * hardocded values (default) + * (?) */ +#define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed, + * default = 0 */ +#define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is + * bypassed, default = 0 */ +#define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA + * active, 1: 2 Serial Ports / + * IrDA active */ +#define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled, + * default */ +#define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated + * (could be turned on), + * default */ + +/* Bits for SPx ICG */ +#define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as + * number of BAUD clocks of + * pause */ + +/* + * Bits for RX_SAMPLINGxx registers + * These registers control when bit value will be sampled within + * the baud period. + * 0 is very beginning of period, 15 is very end, 7 is the middle. + */ +#define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in + * RX_SAMPLING12 */ +#define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in + * RX_SAMPLING12 */ +#define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in + * RX_SAMPLING12 */ +#define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in + * RX_SAMPLING12 */ +#define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in + * RX_SAMPLING23 */ +#define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in + * RX_SAMPLING23 */ +#define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in + * RX_SAMPLING23 */ +#define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in + * RX_SAMPLING23 */ +#define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ +#define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX + * Sampling, center of period */ +#define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ + +/* Bits for ZERO_PERIODx */ +#define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests + * befor sending zero-sized + * reply */ + +/* Bits for ZERO_ENABLE */ +#define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending + * zero-sized replies for port + * 1, default */ +#define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending + * zero-sized replies for port + * 2, default */ +#define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending + * zero-sized replies for port + * 3, default */ +#define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending + * zero-sized replies for port + * 4, default */ + +/* Bits for THR_VAL_HIGHx */ +#define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */ +#define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */ +#define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */ +#define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */ + +/* These are documented in "public" datasheet */ +#define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port + * 1, R/W */ +#define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port + * 1, R/W */ +#define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port + * 1, R/W */ +#define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port + * 2, R/W */ +#define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port + * 2, R/W */ +#define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port + * 2, R/W */ +#define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port + * 3, R/W */ +#define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port + * 3, R/W */ +#define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port + * 3, R/W */ +#define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port + * 4, R/W */ +#define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port + * 4, R/W */ +#define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port + * 4, R/W */ + +/* Bits of DCR0 registers, documented in datasheet */ +#define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver + * when USB Suspend is + * engaged, default = 1 */ +#define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */ +#define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS + * ONLY FOR PORT 1 */ +#define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input + * (0b00), WORKS ONLY + * FOR PORT 1 */ +#define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input + * (0b10), WORKS ONLY + * FOR PORT 1 */ +#define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH, + * default = 0 (low) */ +#define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by + * state of TX buffer, + * default = 0 + * (controlled by MCR) */ +#define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */ +#define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */ + +/* Bits of DCR1 registers, documented in datasheet */ +#define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO + * current value, WORKS + * ONLY FOR PORT 1 */ +#define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current + * 6mA, WORKS ONLY FOR + * PORT 1 */ +#define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current + * 8mA, defauilt, WORKS + * ONLY FOR PORT 1 */ +#define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current + * 10mA, WORKS ONLY FOR + * PORT 1 */ +#define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current + * 12mA, WORKS ONLY FOR + * PORT 1 */ +#define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART + * signals current value */ +#define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current + * 6mA */ +#define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current + * 8mA, defauilt */ +#define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current + * 10mA */ +#define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current + * 12mA */ +#define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB + * Wakeup */ +#define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power + * down when not needed, + * WORKS ONLY FOR PORT 1 */ +#define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of + * interrupt data, with + * FIFO statistics, + * WORKS ONLY FOR PORT 1 */ +#define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */ + +/* + * Bits of DCR2 registers, documented in datasheet + * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and + * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled). + */ +#define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change, + * default = 0 */ +#define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change, + * default = 0 */ +#define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change, + * default = 1 */ +#define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change, + * default = 0 */ +#define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change, + * default = 0 */ +#define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME + * signal, DISCONNECT + * otherwise, default = 1 */ +#define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */ +#define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1: + * Pin 12 Active High, default + * = 0 */ + +/* Interrupt endpoint bytes & bits */ +#define MCS7840_IEP_FIFO_STATUS_INDEX 5 +/* + * Thesse can be calculated as "1 << portnumber" for Bulk-out and + * "1 << (portnumber+1)" for Bulk-in + */ +#define MCS7840_IEP_BO_PORT1_HASDATA 0x01 +#define MCS7840_IEP_BI_PORT1_HASDATA 0x02 +#define MCS7840_IEP_BO_PORT2_HASDATA 0x04 +#define MCS7840_IEP_BI_PORT2_HASDATA 0x08 +#define MCS7840_IEP_BO_PORT3_HASDATA 0x10 +#define MCS7840_IEP_BI_PORT3_HASDATA 0x20 +#define MCS7840_IEP_BO_PORT4_HASDATA 0x40 +#define MCS7840_IEP_BI_PORT4_HASDATA 0x80 + +/* Documented UART registers (fully compatible with 16550 UART) */ +#define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding + * Register W/Only */ +#define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register + * R/Only */ +#define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register - + * R/W */ +#define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register - + * W/Only */ +#define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter + * R/Only */ +#define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */ +#define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */ +#define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */ +#define MCS7840_UART_REG_MSR 0x06 /* Modem status register + * R/Only */ +#define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */ + +#define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */ +#define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */ + +/* IER bits */ +#define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */ +#define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */ +#define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */ +#define MCS7840_UART_IER_MODEM 0x08 /* Modem status change + * interrumpt mask */ +#define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */ + +/* FCR bits */ +#define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */ +#define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ +#define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ +#define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR + * Interrupt Trigger level */ +#define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ +#define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ +#define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ +#define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ + +/* ISR bits */ +#define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */ +#define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt + * source */ +#define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */ +#define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */ +#define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */ +#define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */ +#define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */ + +/* LCR bits */ +#define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */ +#define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */ +#define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */ +#define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */ +#define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */ + +#define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */ +#define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */ +#define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on + * data length */ + +#define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */ +#define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ +#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ +#define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */ +#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ +#define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ + +#define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */ +#define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of + * xHR/IER */ + +/* LSR bits */ +#define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */ +#define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ +#define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */ +#define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */ +#define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */ +#define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty, + * ready for transmit */ +#define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */ + +/* MCR bits */ +#define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active + * (low) */ +#define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active + * (low) */ +#define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from + * code, not documented) */ +#define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test + * mode */ +#define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control + * in 550 (FIFO) mode */ +#define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control + * in 550 (FIFO) mode */ +#define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in + * 550 (FIFO) mode */ + +/* MSR bits */ +#define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last + * read */ +#define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last + * read */ +#define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to + * high since last read */ +#define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last + * read */ +#define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */ +#define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */ +#define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */ +#define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */ + +/* SCRATCHPAD bits */ +#define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ +#define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High + * = RX */ +#define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High + * = TX */ + +#define MCS7840_CONFIG_INDEX 0 +#define MCS7840_IFACE_INDEX 0 + +#endif + + diff --git a/sys/dev/usb/usbdevices.config b/sys/dev/usb/usbdevices.config index 3d1ce24b2ab9..16738411cfb5 100644 --- a/sys/dev/usb/usbdevices.config +++ b/sys/dev/usb/usbdevices.config @@ -1,4 +1,4 @@ -# $NetBSD: usbdevices.config,v 1.23 2013/10/26 09:16:20 nonaka Exp $ +# $NetBSD: usbdevices.config,v 1.24 2014/03/16 09:34:45 martin Exp $ # # This file contains all USB related configuration. # It is suitable for inclusion in a kernel config(5) file. @@ -168,8 +168,12 @@ ucom* at uslsa? portno ? uvscom* at uhub? port ? # SUNTAC Slipper U VS-10U serial adapter ucom* at uvscom? portno ? -moscom* at uhub? port ? # Moschip MCS7xxx serial adaapter -ucom* at moscom? portno ? +# All chips supported by this driver are also supported by umcs(4). +# moscom* at uhub? port ? # Moschip MCS7xxx serial adapter +# ucom* at moscom? portno ? + +umcs* at uhub? port ? # Moschip MCS7xxx serial adapter +ucom* at umcs? portno ? # RIM BlackBerry uberry* at uhub? port ?