Add DMA definitions.
Add some sparc32 related comments.
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uwe
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@ -1,4 +1,4 @@
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/* $NetBSD: ebusreg.h,v 1.1 2001/09/07 15:50:49 mrg Exp $ */
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/* $NetBSD: ebusreg.h,v 1.2 2002/02/18 03:43:29 uwe Exp $ */
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/*
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* Copyright (c) 1999 Matthew R. Green
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@ -28,8 +28,8 @@
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* SUCH DAMAGE.
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*/
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#ifndef _SPARC64_DEV_EBUSREG_H_
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#define _SPARC64_DEV_EBUSREG_H_
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#ifndef _DEV_EBUS_EBUSREG_H_
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#define _DEV_EBUS_EBUSREG_H_
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/*
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* SPARC `ebus'
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@ -52,24 +52,44 @@
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* as other UltraSPARC and some SPARC systems), and other various
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* internal devices found on traditional SPARC systems such as the
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* `power', `flashprom', etc., devices. Other machines with this
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* device include the JavaStation10.
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* device include microSPARC-IIep based systems, e.g. JavaStation10.
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*
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* The ebus uses an interrupt mapping scheme similar to PCI, though
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* the actual structures are different.
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*/
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/*
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* ebus PROM structures
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* EBus PROM structures. There's no official OFW binding for EBus,
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* so ms-IIep PROMs deviate from de-facto standard used on Ultra's.
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*
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* EBus address is represented in PROM by 2 cells: bar and offset.
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* "bar" specifies the EBus BAR register used to translate the
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* "offset" into PCI address space.
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*
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* On Ultra the bar is the _offset_ of the BAR in PCI config space but
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* in (some?) ms-IIep systems (e.g. Krups) it's the _number_ of the
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* BAR - e.g. BAR1 is represented by 1 in Krups PROM, while on Ultra
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* it's 0x14.
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*/
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struct ebus_regs {
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u_int32_t hi; /* high bits of physaddr */
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u_int32_t hi; /* high bits of physaddr */
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u_int32_t lo;
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u_int32_t size;
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};
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/*
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* XXX: uwe: on sparc32 it's not really a paddr, so this name is
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* misleading. Since I don't have a sparc64 to test on, I keep this
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* old define here and add what I think is a correct one below.
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* sparc64 code should be switched to use the new one and the old one
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* (and this comment) shall be removed.
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*/
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#define EBUS_PADDR_FROM_REG(reg) ((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo))
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#define EBUS_ADDR_FROM_REG(reg) BUS_ADDR((reg)->hi, (reg)->lo)
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struct ebus_ranges {
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u_int32_t child_hi; /* child high phys addr */
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u_int32_t child_lo; /* child low phys addr */
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@ -79,6 +99,8 @@ struct ebus_ranges {
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u_int32_t size;
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};
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/* NB: ms-IIep PROMs lack these interrupt-related properties */
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struct ebus_interrupt_map {
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u_int32_t hi; /* high phys addr mask */
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u_int32_t lo; /* low phys addr mask */
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@ -93,4 +115,68 @@ struct ebus_interrupt_map_mask {
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u_int32_t intr; /* interrupt */
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};
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#endif /* _SPARC64_DEV_EBUSREG_H_ */
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/*
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* DMA controller registers.
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*
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* The "next" registers are at the same locations.
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* Which one you write to depends on EN_NEXT bit in the DCSR.
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*/
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#define EBUS_DMAC_DCSR 0 /* control/status register */
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#define EBUS_DMAC_DACR 4 /* address count register */
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#define EBUS_DMAC_DNAR 4 /* next address register */
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#define EBUS_DMAC_DBCR 8 /* byte count register */
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#define EBUS_DMAC_DNBR 8 /* next byte register */
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/* same registers as struct */
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struct ebus_dmac_reg {
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u_int32_t dcsr; /* control/status register */
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u_int32_t dacr; /* address count register */
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u_int32_t dbcr; /* byte count register */
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};
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/*
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* DCSR bits (PCIO manual, Table 7-23, pp 134-135)
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*
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* On Reset all the register bits except ID will be 0 and CYC_PENDING
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* will reflect the status of any pending requests.
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*/
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#define EBDMA_INT_PEND 0x00000001 /* interrupt pending */
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#define EBDMA_ERR_PEND 0x00000002 /* error pending */
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#define EBDMA_DRAIN 0x00000004 /* fifo's being drained to memory */
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#define EBDMA_INT_EN 0x00000010 /* enable interrupts */
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#define EBDMA_RESET 0x00000080 /* reset - write 0 to clear */
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#define EBDMA_WRITE 0x00000100 /* 0: mem->dev, 1: dev->mem */
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#define EBDMA_EN_DMA 0x00000200 /* enable DMA */
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#define EBDMA_CYC_PEND 0x00000400 /* DMA cycle pending
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- not safe to clear reset */
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#define EBDMA_DIAG_RD_DONE 0x00000800 /* DIAG mode: DMA read completed */
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#define EBDMA_DIAG_WR_DONE 0x00001000 /* DIAG mode: DMA write completed */
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#define EBDMA_EN_CNT 0x00002000 /* enable byte counter */
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#define EBDMA_TC 0x00004000 /* terminal count
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- write 1 to clear */
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#define EBDMA_DIS_CSR_DRN 0x00010000 /* disable fifo draining
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on slave writes to CSR */
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#define EBDMA_BURST_SIZE_MASK 0x000c0000 /* burst sizes: */
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#define EBDMA_BURST_SIZE_4 0x00000000 /* 00 - 4 words */
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#define EBDMA_BURST_SIZE_8 0x00040000 /* 01 - 8 words */
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#define EBDMA_BURST_SIZE_1 0x00080000 /* 10 - 1 word */
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#define EBDMA_BURST_SIZE_16 0x000c0000 /* 11 - 16 words */
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#define EBDMA_DIAG_EN 0x00100000 /* enable diag mode */
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#define EBDMA_DIS_ERR_PEND 0x00400000 /* disable stop/interrupt
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on error pedning */
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#define EBDMA_TCI_DIS 0x00800000 /* disable interrupt on TC */
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#define EBDMA_EN_NEXT 0x01000000 /* enable next address autoload
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(must set EN_CNT too) */
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#define EBDMA_DMA_ON 0x02000000 /* DMA is able to respond */
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#define EBDMA_A_LOADED 0x04000000 /* DACR loaded
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(directly or from DNAR) */
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#define EBDMA_NA_LOADED 0x08000000 /* DNAR loaded */
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#define EBDMA_ID_MASK 0xf0000000 /* Device ID = 0xC */
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#define EBUS_DCSR_BITS \
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"\20\34NA_LOADED\33A_LOADED\32DMA_ON\31EN_NEXT\30TCI_DIS\27DIS_ERR_PEND" \
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"\25DIAG_EN\21DIS_CSR_DRN\17TC\16EN_CNT\15DIAG_WR_DONE\14DIAG_RD_DONE" \
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"\13CYC_PEND\12EN_DMA\11WRITE\10RESET\6INT_EN\3DRAIN\2ERR_PEND\1INT_PEND"
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#endif /* _DEV_EBUS_EBUSREG_H_ */
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