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Merge forward from matt-nb5-mips64.

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Adapt to new interrupt/spl framework.
This commit is contained in:
matt 2011-02-20 07:51:21 +00:00
parent 5e124f3ab7
commit ea81094378
16 changed files with 129 additions and 265 deletions
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24
sys/arch/algor/algor/algor_p4032_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor_p4032_intr.c,v 1.20 2008/05/26 15:59:29 tsutsui Exp $ */
/* $NetBSD: algor_p4032_intr.c,v 1.21 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -38,9 +38,10 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: algor_p4032_intr.c,v 1.20 2008/05/26 15:59:29 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: algor_p4032_intr.c,v 1.21 2011/02/20 07:51:21 matt Exp $");
#include "opt_ddb.h"
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/queue.h>
@ -99,7 +100,7 @@ struct p4032_irqreg p4032_irqsteer[NSTEERREG] = {
#define IRQMAP_8BITBASE NPCIIRQS
#define NIRQMAPS (IRQMAP_8BITBASE + N8BITIRQS)
const char *p4032_intrnames[NIRQMAPS] = {
const char * const p4032_intrnames[NIRQMAPS] = {
/*
* PCI INTERRUPTS
*/
@ -205,12 +206,12 @@ struct p4032_cpuintr {
};
struct p4032_cpuintr p4032_cpuintrs[NINTRS];
const char *p4032_cpuintrnames[NINTRS] = {
const char * const p4032_cpuintrnames[NINTRS] = {
"int 0 (pci)",
"int 1 (8-bit)",
};
const char *p4032_intrgroups[NINTRS] = {
const char * const p4032_intrgroups[NINTRS] = {
"pci",
"8-bit",
};
@ -226,7 +227,7 @@ void *algor_p4032_pci_intr_establish(void *, pci_intr_handle_t, int,
void algor_p4032_pci_intr_disestablish(void *, void *);
void algor_p4032_pci_conf_interrupt(void *, int, int, int, int, int *);
void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void algor_p4032_iointr(int, vaddr_t, uint32_t);
void
algor_p4032_intr_init(struct p4032_config *acp)
@ -242,7 +243,6 @@ algor_p4032_intr_init(struct p4032_config *acp)
evcnt_attach_dynamic(&p4032_cpuintrs[i].cintr_count,
EVCNT_TYPE_INTR, NULL, "mips", p4032_cpuintrnames[i]);
}
evcnt_attach_static(&mips_int5_evcnt);
for (i = 0; i < NIRQMAPS; i++) {
irqmap = &p4032_irqmap[i];
@ -414,8 +414,7 @@ algor_p4032_intr_disestablish(void *cookie)
}
void
algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
u_int32_t ipending)
algor_p4032_iointr(int ipl, vaddr_t pc, u_int32_t ipending)
{
const struct p4032_irqmap *irqmap;
struct algor_intrhand *ih;
@ -452,9 +451,6 @@ algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
* XXX the floppy interrupt here.
*/
cause &= ~MIPS_INT_MASK_3;
_splset(MIPS_SR_INT_IE |
((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*
@ -481,11 +477,7 @@ algor_p4032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
(*ih->ih_func)(ih->ih_arg);
}
}
cause &= ~(MIPS_INT_MASK_0 << level);
}
/* Re-enable anything that we have processed. */
_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*****************************************************************************

4
sys/arch/algor/algor/algor_p4032var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor_p4032var.h,v 1.5 2008/04/28 20:23:10 martin Exp $ */
/* $NetBSD: algor_p4032var.h,v 1.6 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -72,7 +72,7 @@ void algor_p4032_dma_init(struct p4032_config *);
void algor_p4032_intr_init(struct p4032_config *);
void algor_p4032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void algor_p4032_iointr(int, vaddr_t, uint32_t);
void algor_p4032_cal_timer(bus_space_tag_t, bus_space_handle_t);
#endif /* _KERNEL */

29
sys/arch/algor/algor/algor_p5064_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor_p5064_intr.c,v 1.23 2008/05/26 15:59:29 tsutsui Exp $ */
/* $NetBSD: algor_p5064_intr.c,v 1.24 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -38,9 +38,10 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: algor_p5064_intr.c,v 1.23 2008/05/26 15:59:29 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: algor_p5064_intr.c,v 1.24 2011/02/20 07:51:21 matt Exp $");
#include "opt_ddb.h"
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/queue.h>
@ -68,11 +69,11 @@ __KERNEL_RCSID(0, "$NetBSD: algor_p5064_intr.c,v 1.23 2008/05/26 15:59:29 tsutsu
#include <dev/isa/isavar.h>
#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
struct p5064_irqreg {
bus_addr_t addr;
u_int32_t val;
uint32_t val;
};
#define IRQREG_LOCINT 0
@ -111,7 +112,7 @@ struct p5064_irqreg p5064_irqsteer[NSTEERREG] = {
#define IRQMAP_ISABASE (IRQMAP_LOCBASE + NLOCIRQS)
#define NIRQMAPS (IRQMAP_ISABASE + NISAIRQS)
const char *p5064_intrnames[NIRQMAPS] = {
const char * const p5064_intrnames[NIRQMAPS] = {
/*
* PCI INTERRUPTS
*/
@ -274,13 +275,13 @@ struct p5064_cpuintr {
};
struct p5064_cpuintr p5064_cpuintrs[NINTRS];
const char *p5064_cpuintrnames[NINTRS] = {
const char * const p5064_cpuintrnames[NINTRS] = {
"int 0 (isa)",
"int 1 (pci)",
"int 2 (local)",
};
const char *p5064_intrgroups[NINTRS] = {
const char * const p5064_intrgroups[NINTRS] = {
"isa",
"pci",
"local",
@ -305,7 +306,7 @@ void *algor_p5064_isa_intr_establish(void *, int, int, int,
void algor_p5064_isa_intr_disestablish(void *, void *);
int algor_p5064_isa_intr_alloc(void *, int, int, int *);
void algor_p5064_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void algor_p5064_iointr(int, vaddr_t, uint32_t);
void
algor_p5064_intr_init(struct p5064_config *acp)
@ -321,7 +322,6 @@ algor_p5064_intr_init(struct p5064_config *acp)
evcnt_attach_dynamic(&p5064_cpuintrs[i].cintr_count,
EVCNT_TYPE_INTR, NULL, "mips", p5064_cpuintrnames[i]);
}
evcnt_attach_static(&mips_int5_evcnt);
for (i = 0; i < NIRQMAPS; i++) {
irqmap = &p5064_irqmap[i];
@ -362,7 +362,7 @@ void
algor_p5064_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
{
u_long ctrdiff[4], startctr, endctr, cps;
u_int32_t irr;
uint32_t irr;
int i;
/* Disable interrupts first. */
@ -507,13 +507,12 @@ algor_p5064_intr_disestablish(void *cookie)
}
void
algor_p5064_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
u_int32_t ipending)
algor_p5064_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
const struct p5064_irqmap *irqmap;
struct algor_intrhand *ih;
int level, i;
u_int32_t irr[NIRQREG];
uint32_t irr[NIRQREG];
/* Check for PANIC interrupts. */
if (ipending & MIPS_INT_MASK_4) {
@ -566,11 +565,7 @@ algor_p5064_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
(*ih->ih_func)(ih->ih_arg);
}
}
cause &= ~(MIPS_INT_MASK_0 << level);
}
/* Re-enable anything that we have processed. */
_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*****************************************************************************

4
sys/arch/algor/algor/algor_p5064var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor_p5064var.h,v 1.6 2008/04/28 20:23:10 martin Exp $ */
/* $NetBSD: algor_p5064var.h,v 1.7 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -75,7 +75,7 @@ void algor_p5064_dma_init(struct p5064_config *);
void algor_p5064_intr_init(struct p5064_config *);
void algor_p5064_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void algor_p5064_iointr(int, vaddr_t, uint32_t);
void algor_p5064_cal_timer(bus_space_tag_t, bus_space_handle_t);
#endif /* _KERNEL */

21
sys/arch/algor/algor/algor_p6032_intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: algor_p6032_intr.c,v 1.16 2008/05/26 15:59:29 tsutsui Exp $ */
/* $NetBSD: algor_p6032_intr.c,v 1.17 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -37,9 +37,10 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: algor_p6032_intr.c,v 1.16 2008/05/26 15:59:29 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: algor_p6032_intr.c,v 1.17 2011/02/20 07:51:21 matt Exp $");
#include "opt_ddb.h"
#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/queue.h>
@ -182,7 +183,7 @@ void *algor_p6032_pci_intr_establish(void *, pci_intr_handle_t, int,
void algor_p6032_pci_intr_disestablish(void *, void *);
void algor_p6032_pci_conf_interrupt(void *, int, int, int, int, int *);
void algor_p6032_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void algor_p6032_iointr(int, vaddr_t, uint32_t);
void
algor_p6032_intr_init(struct p6032_config *acp)
@ -196,7 +197,6 @@ algor_p6032_intr_init(struct p6032_config *acp)
evcnt_attach_dynamic(&p6032_cpuintrs[i].cintr_count,
EVCNT_TYPE_INTR, NULL, "mips", p6032_cpuintrnames[i]);
}
evcnt_attach_static(&mips_int5_evcnt);
for (i = 0; i <= NIRQMAPS; i++) {
irqmap = &p6032_irqmap[i];
@ -240,7 +240,7 @@ void
algor_p6032_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
{
u_long ctrdiff[4], startctr, endctr, cps;
u_int8_t regc;
uint8_t regc;
int i;
/* Disable interrupts first. */
@ -371,13 +371,12 @@ algor_p6032_intr_disestablish(void *cookie)
}
void
algor_p6032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
u_int32_t ipending)
algor_p6032_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
const struct p6032_irqmap *irqmap;
struct algor_intrhand *ih;
int level;
u_int32_t isr;
uint32_t isr;
/* Check for DEBUG interrupts. */
if (ipending & MIPS_INT_MASK_3) {
@ -390,8 +389,6 @@ algor_p6032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
printf("Debug switch ignored -- "
"no debugger configured\n");
#endif
cause &= ~MIPS_INT_MASK_3;
}
/*
@ -414,11 +411,7 @@ algor_p6032_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
(*ih->ih_func)(ih->ih_arg);
}
}
cause &= ~(MIPS_INT_MASK_0 << level);
}
/* Re-enable anything that we have processed. */
_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*****************************************************************************

23
sys/arch/algor/algor/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.6 2005/12/11 12:16:08 christos Exp $ */
/* $NetBSD: cpu.c,v 1.7 2011/02/20 07:51:21 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -28,23 +28,24 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.6 2005/12/11 12:16:08 christos Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.7 2011/02/20 07:51:21 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/cpu.h>
#include <machine/autoconf.h>
int cpu_match(struct device *, struct cfdata *, void *);
void cpu_attach(struct device *, struct device *, void *);
static int cpu_match(device_t, cfdata_t, void *);
static void cpu_attach(device_t, device_t, void *);
CFATTACH_DECL(cpu, sizeof(struct device),
CFATTACH_DECL_NEW(cpu, 0,
cpu_match, cpu_attach, NULL, NULL);
extern struct cfdriver cpu_cd;
int
cpu_match(struct device *parent, struct cfdata *cf, void *aux)
cpu_match(device_t parent, cfdata_t cf, void *aux)
{
struct mainbus_attach_args *ma = aux;
@ -55,9 +56,13 @@ cpu_match(struct device *parent, struct cfdata *cf, void *aux)
}
void
cpu_attach(struct device *parent, struct device *dev, void *aux)
cpu_attach(device_t parent, device_t self, void *aux)
{
struct cpu_info * const ci = curcpu();
printf(": ");
cpu_identify();
ci->ci_dev = self;
self->dv_private = ci;
aprint_normal(": ");
cpu_identify(self);
}

95
sys/arch/algor/algor/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.15 2010/12/20 00:25:23 matt Exp $ */
/* $NetBSD: interrupt.c,v 1.16 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -30,8 +30,9 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.15 2010/12/20 00:25:23 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.16 2011/02/20 07:51:21 matt Exp $");
#define __INTR_PRIVATE
#include "opt_algor_p4032.h"
#include "opt_algor_p5064.h"
#include "opt_algor_p6032.h"
@ -62,42 +63,31 @@ __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.15 2010/12/20 00:25:23 matt Exp $");
void *(*algor_intr_establish)(int, int (*)(void *), void *);
void (*algor_intr_disestablish)(void *);
void (*algor_iointr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
u_long cycles_per_hz;
void (*algor_iointr)(int, vaddr_t, uint32_t);
/*
* This is a mask of bits to clear in the SR when we go to a
* given interrupt priority level.
*/
const u_int32_t ipl_sr_bits[_IPL_N] = {
0, /* IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0|
MIPS_INT_MASK_1|
MIPS_INT_MASK_2|
MIPS_INT_MASK_3, /* IPL_VM */
MIPS_SOFT_INT_MASK_0|
MIPS_SOFT_INT_MASK_1|
MIPS_INT_MASK_0|
MIPS_INT_MASK_1|
MIPS_INT_MASK_2|
MIPS_INT_MASK_3|
MIPS_INT_MASK_4|
MIPS_INT_MASK_5, /* IPL_SCHED */
static const struct ipl_sr_map algor_ipl_sr_map = {
.sr_bits = {
[IPL_NONE] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
[IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
[IPL_VM] = MIPS_SOFT_INT_MASK
|MIPS_INT_MASK_0|MIPS_INT_MASK_1
|MIPS_INT_MASK_2|MIPS_INT_MASK_3,
[IPL_SCHED] = MIPS_INT_MASK,
[IPL_HIGH] = MIPS_INT_MASK,
},
};
void
intr_init(void)
{
ipl_sr_map = algor_ipl_sr_map;
#if defined(ALGOR_P4032)
algor_p4032_intr_init(&p4032_configuration);
@ -109,40 +99,29 @@ intr_init(void)
}
void
cpu_intr(u_int32_t status, u_int32_t cause, vaddr_t pc, u_int32_t ipending)
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
struct clockframe cf;
struct cpu_info *ci;
uint32_t pending;
int ipl;
ci = curcpu();
ci->ci_idepth++;
ci->ci_data.cpu_nintr++;
curcpu()->ci_data.cpu_nintr++;
if (ipending & MIPS_INT_MASK_5) {
while (ppl < (ipl = splintr(&pending))) {
splx(ipl);
if (pending & MIPS_INT_MASK_5) {
struct clockframe cf;
cf.pc = pc;
cf.sr = status;
mips3_clockintr(&cf);
cf.pc = pc;
cf.sr = status;
cf.intr = (curcpu()->ci_idepth > 1);
mips3_clockintr(&cf);
}
/* Re-enable clock interrupts. */
cause &= ~MIPS_INT_MASK_5;
_splset(MIPS_SR_INT_IE |
((status & ~cause) & MIPS_HARD_INT_MASK));
if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
/* Process I/O and error interrupts. */
(*algor_iointr)(ipl, pc, pending);
}
(void)splhigh();
}
if (ipending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
/* Process I/O and error interrupts. */
(*algor_iointr)(status, cause, pc, ipending);
}
ci->ci_idepth--;
#ifdef __HAVE_FAST_SOFTINTS
ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
if (ipending == 0)
return;
_clrsoftintr(ipending);
softintr_dispatch(ipending);
#endif
}

90
sys/arch/algor/algor/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.48 2011/02/08 20:20:07 rmind Exp $ */
/* $NetBSD: machdep.c,v 1.49 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.48 2011/02/08 20:20:07 rmind Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.49 2011/02/20 07:51:21 matt Exp $");
#include "opt_algor_p4032.h"
#include "opt_algor_p5064.h"
@ -100,6 +100,8 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.48 2011/02/08 20:20:07 rmind Exp $");
#include <dev/cons.h>
#include <mips/locore.h>
#ifdef DDB
#include <machine/db_machdep.h>
#include <ddb/db_extern.h>
@ -170,15 +172,11 @@ mach_init(int argc, char *argv[], char *envp[])
{
extern char kernel_text[], edata[], end[];
vaddr_t kernstart, kernend;
paddr_t kernstartpfn, kernendpfn, pfn0, pfn1;
vsize_t size;
const char *cp;
char *cp0;
size_t i;
/* Disable interrupts. */
(void) splhigh();
/*
* First, find the start and end of the kernel and clear
* the BSS segment. Account for a bit of space for the
@ -189,15 +187,22 @@ mach_init(int argc, char *argv[], char *envp[])
kernend = (vaddr_t) mips_round_page(end);
memset(edata, 0, kernend - (vaddr_t)edata);
/*
* Copy the exception-dispatch code down to the exception vector.
* Initialize the locore function vector. Clear out the I- and
* D-caches.
*
* We can no longer call into PMON after this.
*/
led_display('v', 'e', 'c', 'i');
mips_vector_init(NULL, false);
/*
* Initialize PAGE_SIZE-dependent variables.
*/
led_display('p', 'g', 's', 'z');
uvm_setpagesize();
kernstartpfn = atop(MIPS_KSEG0_TO_PHYS(kernstart));
kernendpfn = atop(MIPS_KSEG0_TO_PHYS(kernend));
/*
* Initialize bus space tags and bring up the console.
*/
@ -449,73 +454,25 @@ mach_init(int argc, char *argv[], char *envp[])
size - mem_clusters[mem_cluster_cnt].start;
mem_cluster_cnt++;
/*
* Copy the exception-dispatch code down to the exception vector.
* Initialize the locore function vector. Clear out the I- and
* D-caches.
*
* We can no longer call into PMON after this.
*/
led_display('v', 'e', 'c', 'i');
mips_vector_init();
/*
* Load the physical memory clusters into the VM system.
*/
led_display('v', 'm', 'p', 'g');
for (i = 0; i < mem_cluster_cnt; i++) {
physmem += atop(mem_clusters[i].size);
pfn0 = atop(mem_clusters[i].start);
pfn1 = pfn0 + atop(mem_clusters[i].size);
if (pfn0 <= kernstartpfn && kernendpfn <= pfn1) {
/*
* Must compute the location of the kernel
* within the segment.
*/
#if 1
printf("Cluster %zu contains kernel\n", i);
#endif
if (pfn0 < kernstartpfn) {
/*
* There is a chunk before the kernel.
*/
#if 1
printf("Loading chunk before kernel: "
"%#"PRIxPADDR" / %#"PRIxPADDR"\n",
pfn0, kernstartpfn);
#endif
uvm_page_physload(pfn0, kernstartpfn,
pfn0, kernstartpfn, VM_FREELIST_DEFAULT);
}
if (kernendpfn < pfn1) {
/*
* There is a chunk after the kernel.
*/
#if 1
printf("Loading chunk after kernel: "
"%#"PRIxPADDR" / %#"PRIxPADDR"\n",
kernendpfn, pfn1);
#endif
uvm_page_physload(kernendpfn, pfn1,
kernendpfn, pfn1, VM_FREELIST_DEFAULT);
}
} else {
/*
* Just load this cluster as one chunk.
*/
#if 1
printf("Loading cluster %zu: %#"PRIxPADDR
" / %#"PRIxPADDR"\n", i, pfn0, pfn1);
#endif
uvm_page_physload(pfn0, pfn1, pfn0, pfn1,
VM_FREELIST_DEFAULT);
}
}
if (physmem == 0)
panic("can't happen: system seems to have no memory!");
maxmem = physmem;
static const struct mips_vmfreelist isadma = {
.fl_start = 8*1024*1024,
.fl_end = 16*1024*1024,
.fl_freelist = VM_FREELIST_ISADMA,
};
mips_page_physload(kernstart, kernend,
mem_clusters, mem_cluster_cnt, &isadma, 1);
/*
* Initialize message buffer (at end of core).
*/
@ -628,8 +585,7 @@ cpu_reboot(int howto, char *bootstr)
int tmp;
/* Take a snapshot before clobbering any registers. */
if (curlwp)
savectx(curpcb);
savectx(curpcb);
/* If "always halt" was specified as a boot flag, obey. */
if (boothowto & RB_HALT)

6
sys/arch/algor/conf/P4032
View File

@ -1,4 +1,4 @@
# $NetBSD: P4032,v 1.55 2011/01/21 22:37:11 he Exp $
# $NetBSD: P4032,v 1.56 2011/02/20 07:51:21 matt Exp $
#
# Algorithmics P-4032 kernel.
#
@ -7,7 +7,7 @@ include "arch/algor/conf/std.algor"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
#ident "P4032-$Revision: 1.55 $"
#ident "P4032-$Revision: 1.56 $"
maxusers 32
@ -30,7 +30,7 @@ options DIAGNOSTIC # Cheap kernel consistency checks
options DDB # kernel debugger
makeoptions DEBUG="-g"
#makeoptions DEBUGLIST="pattern1 pattern2 ..."
options SYMTAB_SPACE=350000
options SYMTAB_SPACE=400000
# File systems
file-system FFS # Fast file system

6
sys/arch/algor/conf/P5064
View File

@ -1,4 +1,4 @@
# $NetBSD: P5064,v 1.61 2010/11/23 11:13:53 hannken Exp $
# $NetBSD: P5064,v 1.62 2011/02/20 07:51:21 matt Exp $
#
# Algorithmics P-5064 kernel.
#
@ -7,7 +7,7 @@ include "arch/algor/conf/std.algor"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
#ident "P5064-$Revision: 1.61 $"
#ident "P5064-$Revision: 1.62 $"
maxusers 32
@ -25,7 +25,7 @@ options DIAGNOSTIC # Cheap kernel consistency checks
options DDB # kernel debugger
makeoptions DEBUG="-g"
#makeoptions DEBUGLIST="pattern1 pattern2 ..."
options SYMTAB_SPACE=400000
options SYMTAB_SPACE=450000
# File systems
file-system FFS # Fast file system

6
sys/arch/algor/conf/P5064-64
View File

@ -1,4 +1,4 @@
# $NetBSD: P5064-64,v 1.2 2009/12/14 00:46:00 matt Exp $
# $NetBSD: P5064-64,v 1.3 2011/02/20 07:51:21 matt Exp $
#
# Algorithmics P-5064 kernel (64-bit).
#
@ -8,5 +8,5 @@ include "arch/algor/conf/P5064"
include "arch/algor/conf/std.algor64"
no options SYMTAB_SPACE
options SYMTAB_SPACE=510000
#ident "P5064-64-$Revision: 1.2 $"
options SYMTAB_SPACE=600000
#ident "P5064-64-$Revision: 1.3 $"

3
sys/arch/algor/conf/files.algor
View File

@ -1,4 +1,4 @@
# $NetBSD: files.algor,v 1.26 2009/08/21 03:45:10 thorpej Exp $
# $NetBSD: files.algor,v 1.27 2011/02/20 07:51:21 matt Exp $
# Algorithmics evaluation board specific configuration info.
@ -41,7 +41,6 @@ file arch/algor/algor/led.c
file arch/algor/algor/machdep.c
file arch/algor/algor/pmon.c
file arch/mips/mips/softintr.c
file arch/mips/mips/mips3_clock.c
file arch/mips/mips/mips3_clockintr.c

6
sys/arch/algor/dev/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.20 2008/04/28 20:23:10 martin Exp $ */
/* $NetBSD: mainbus.c,v 1.21 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.20 2008/04/28 20:23:10 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.21 2011/02/20 07:51:21 matt Exp $");
#include "opt_algor_p4032.h"
#include "opt_algor_p5064.h"
@ -194,7 +194,7 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
#endif
#endif /* ALGOR_P4032 || ALGOR_P5064 || ALGOR_P6032 */
pci_configure_bus(pc, ioext, memext, NULL, 0, mips_dcache_align);
pci_configure_bus(pc, ioext, memext, NULL, 0, mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);

8
sys/arch/algor/include/autoconf.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: autoconf.h,v 1.4 2003/03/22 14:26:41 simonb Exp $ */
/* $NetBSD: autoconf.h,v 1.5 2011/02/20 07:51:21 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@ -44,12 +44,10 @@ struct mainbus_attach_args {
#ifdef _KERNEL
extern char algor_ethaddr[];
extern u_long cycles_per_hz;
extern u_int delay_divisor;
void (*algor_iointr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void (*algor_iointr)(int, vaddr_t, uint32_t);
void led_display(u_int8_t, u_int8_t, u_int8_t, u_int8_t);
void led_display(uint8_t, uint8_t, uint8_t, uint8_t);
#endif /* _KERNEL */
#endif /* !_ALGOR_AUTOCONF_H_ */

57
sys/arch/algor/include/intr.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.13 2008/04/28 20:23:10 martin Exp $ */
/* $NetBSD: intr.h,v 1.14 2011/02/20 07:51:21 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@ -35,69 +35,18 @@
#include <sys/evcnt.h>
#include <sys/queue.h>
#define IPL_NONE 0 /* disable only this interrupt */
#define IPL_SOFTCLOCK 1 /* generic software interrupts (SI 0) */
#define IPL_SOFTBIO 1 /* clock software interrupts (SI 0) */
#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
#define IPL_VM 3
#define IPL_SCHED 4
#define IPL_HIGH 4 /* disable all interrupts */
#define _IPL_N 5
#define _IPL_SI0_FIRST IPL_SOFTCLOCK
#define _IPL_SI0_LAST IPL_SOFTBIO
#define _IPL_SI1_FIRST IPL_SOFTNET
#define _IPL_SI1_LAST IPL_SOFTSERIAL
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#include <mips/intr.h>
#ifdef _KERNEL
#include <mips/locore.h>
extern const u_int32_t ipl_sr_bits[_IPL_N];
#define spl0() (void) _spllower(0)
#define splx(s) (void) _splset(s)
typedef int ipl_t;
typedef struct {
ipl_t _sr;
} ipl_cookie_t;
static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
}
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return _splraise(icookie._sr);
}
#include <sys/spl.h>
struct algor_intrhand {
LIST_ENTRY(algor_intrhand) ih_q;
const void *ih_irqmap;
int (*ih_func)(void *);
void *ih_arg;
int ih_irq; /* mostly for ISA */
const void *ih_irqmap;
};
#include <mips/softintr.h>
extern struct evcnt mips_int5_evcnt;
void intr_init(void);

12
sys/arch/algor/isa/isadma_bounce.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: isadma_bounce.c,v 1.8 2008/04/28 20:23:10 martin Exp $ */
/* $NetBSD: isadma_bounce.c,v 1.9 2011/02/20 07:51:22 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: isadma_bounce.c,v 1.8 2008/04/28 20:23:10 martin Exp $");
__KERNEL_RCSID(0, "$NetBSD: isadma_bounce.c,v 1.9 2011/02/20 07:51:22 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -52,8 +52,6 @@ __KERNEL_RCSID(0, "$NetBSD: isadma_bounce.c,v 1.8 2008/04/28 20:23:10 martin Exp
#include <uvm/uvm_extern.h>
extern paddr_t avail_end;
/*
* Cookie used by bouncing ISA DMA. A pointer to one of these is stashed
* in the DMA map.
@ -138,7 +136,7 @@ isadma_bounce_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments,
* ISA DMA controller), we may have to bounce it as well.
*/
cookieflags = 0;
if (avail_end > (t->_wbase + t->_wsize) ||
if (mips_avail_end > (t->_wbase + t->_wsize) ||
((map->_dm_size / PAGE_SIZE) + 1) > map->_dm_segcnt) {
cookieflags |= ID_MIGHT_NEED_BOUNCE;
cookiesize += (sizeof(bus_dma_segment_t) *
@ -540,10 +538,10 @@ isadma_bounce_dmamem_alloc(bus_dma_tag_t t, bus_size_t size,
{
paddr_t high;
if (avail_end > ISA_DMA_BOUNCE_THRESHOLD)
if (mips_avail_end > ISA_DMA_BOUNCE_THRESHOLD)
high = trunc_page(ISA_DMA_BOUNCE_THRESHOLD);
else
high = trunc_page(avail_end);
high = trunc_page(mips_avail_end);
return (_bus_dmamem_alloc_range(t, size, alignment, boundary,
segs, nsegs, rsegs, flags, 0, high));