From ea4f35dcd0453b0138c75b6e4bd3c61fbec11bbc Mon Sep 17 00:00:00 2001 From: bouyer Date: Sun, 17 Dec 2006 23:02:06 +0000 Subject: [PATCH] Add bnx(4), a driver for Broadcom NetXtreme II 10/100/1000 Ethernet device. Ported from OpenBSD by cube@, with some bus_dma fixes by me. Tested on i386 and amd64. --- distrib/sets/lists/man/mi | 4 +- share/man/man4/Makefile | 4 +- share/man/man4/bnx.4 | 148 + sys/arch/amd64/conf/GENERIC | 5 +- sys/arch/amd64/conf/INSTALL | 5 +- sys/arch/i386/conf/ALL | 5 +- sys/arch/i386/conf/GENERIC | 5 +- sys/arch/i386/conf/GENERIC_LAPTOP | 5 +- sys/arch/i386/conf/INSTALL | 3 +- sys/arch/i386/conf/INSTALL_LAPTOP | 3 +- sys/arch/i386/conf/XEN2_DOM0 | 3 +- sys/dev/microcode/bnx/bnxfw.h | 3510 ++++++++++++++++++ sys/dev/pci/files.pci | 7 +- sys/dev/pci/if_bnx.c | 5735 +++++++++++++++++++++++++++++ sys/dev/pci/if_bnxreg.h | 4848 ++++++++++++++++++++++++ 15 files changed, 14273 insertions(+), 17 deletions(-) create mode 100644 share/man/man4/bnx.4 create mode 100644 sys/dev/microcode/bnx/bnxfw.h create mode 100644 sys/dev/pci/if_bnx.c create mode 100644 sys/dev/pci/if_bnxreg.h diff --git a/distrib/sets/lists/man/mi b/distrib/sets/lists/man/mi index 3f49ddf5d52a..d7c186ce03e9 100644 --- a/distrib/sets/lists/man/mi +++ b/distrib/sets/lists/man/mi @@ -1,4 +1,4 @@ -# $NetBSD: mi,v 1.958 2006/12/17 22:57:14 bouyer Exp $ +# $NetBSD: mi,v 1.959 2006/12/17 23:02:06 bouyer Exp $ ./etc/mtree/set.man man-sys-root ./usr/share/info/am-utils.info man-amd-info info ./usr/share/info/as.info man-computil-info bfd,info @@ -721,6 +721,7 @@ ./usr/share/man/cat4/bktr.0 man-sys-catman .cat ./usr/share/man/cat4/bluetooth.0 man-sys-catman .cat ./usr/share/man/cat4/bmtphy.0 man-sys-catman .cat +./usr/share/man/cat4/bnx.0 man-sys-catman .cat ./usr/share/man/cat4/boca.0 man-sys-catman .cat ./usr/share/man/cat4/bpf.0 man-sys-catman .cat ./usr/share/man/cat4/brgphy.0 man-sys-catman .cat @@ -3122,6 +3123,7 @@ ./usr/share/man/man4/bktr.4 man-sys-man .man ./usr/share/man/man4/bluetooth.4 man-sys-man .man ./usr/share/man/man4/bmtphy.4 man-sys-man .man +./usr/share/man/man4/bnx.4 man-sys-man .man ./usr/share/man/man4/boca.4 man-sys-man .man ./usr/share/man/man4/bpf.4 man-sys-man .man ./usr/share/man/man4/brgphy.4 man-sys-man .man diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 83fa8fbb4535..5aa6d9159fb6 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.416 2006/12/17 22:57:14 bouyer Exp $ +# $NetBSD: Makefile,v 1.417 2006/12/17 23:02:06 bouyer Exp $ # @(#)Makefile 8.1 (Berkeley) 6/18/93 MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 adc.4 adt7467c.4 adv.4 \ @@ -7,7 +7,7 @@ MAN= aac.4 ac97.4 acardide.4 aceride.4 acphy.4 adc.4 adt7467c.4 adv.4 \ ath.4 atppc.4 attimer.4 atw.4 \ auacer.4 audio.4 audiocs.4 auich.4 \ auixp.4 autri.4 auvia.4 awi.4 azalia.4 \ - bba.4 bce.4 be.4 bge.4 bha.4 bktr.4 bluetooth.4 bmtphy.4 \ + bba.4 bce.4 be.4 bge.4 bnx.4 bha.4 bktr.4 bluetooth.4 bmtphy.4 \ bpf.4 brgphy.4 bridge.4 bthidev.4 bthub.4 btkbd.4 btms.4 btsco.4 \ cac.4 cardbus.4 carp.4 ccd.4 cd.4 \ cec.4 cgd.4 cfb.4 ch.4 ciphy.4 ciss.4 clcs.4 clct.4 clnp.4 \ diff --git a/share/man/man4/bnx.4 b/share/man/man4/bnx.4 new file mode 100644 index 000000000000..cc26628fa6a6 --- /dev/null +++ b/share/man/man4/bnx.4 @@ -0,0 +1,148 @@ +.\" $NetBSD: bnx.4,v 1.1 2006/12/17 23:02:06 bouyer Exp $ +.\" $OpenBSD: bnx.4,v 1.13 2006/12/15 16:12:52 reyk Exp $ +.\" +.\" Copyright (c) 2006 Broadcom Corporation +.\" David Christensen . All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. Neither the name of Broadcom Corporation nor the name of its contributors +.\" may be used to endorse or promote products derived from this software +.\" without specific prior written consent. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS `AS IS' +.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" +.\" $FreeBSD: /repoman/r/ncvs/src/share/man/man4/bce.4,v 1.2 2006/04/10 20:12:17 brueffer Exp $ +.\" +.Dd December 17, 2006 +.Dt BNX 4 +.Os +.Sh NAME +.Nm bnx +.Nd Broadcom NetXtreme II 10/100/1000 Ethernet device +.Sh SYNOPSIS +.Cd "bnx* at pci?" +.Cd "brgphy* at mii?" +.Sh DESCRIPTION +The +.Nm +driver supports Broadcom's NetXtreme II product family, such as the +BCM5706 PCI-X and BCM5708 PCI Express Ethernet controllers, which +includes the following: +.Pp +.Bl -bullet -compact +.It +Dell PowerEdge 1950 integrated BCM5708 NIC (10/100/1000baseT) +.It +Dell PowerEdge 2950 integrated BCM5708 NIC (10/100/1000baseT) +.It +HP NC370F PCI-X Multifunction Gigabit server adapter (1000baseSX) +.It +HP NC370T PCI-X Multifunction Gigabit server adapter (10/100/1000baseT) +.It +HP NC373F PCI Express Multifunction Gigabit server adapter (1000baseSX) +.It +HP NC373i PCI Express Multifunction Gigabit embedded server adapter (10/100/1000baseT) +.It +HP NC380T PCI Express Dual Port Multifunction Gigabit server adapter (10/100/1000baseT) +.It +IBM xSeries 3550 integrated BCM5708 NIC (10/100/1000baseT) +.It +IBM xSeries 3650 integrated BCM5708 NIC (10/100/1000baseT) +.El +.Pp +The NetXtreme II product family is composed of various Converged NIC (or CNIC) +Ethernet controllers which support a TCP Offload Engine (TOE), +Remote DMA (RDMA), and iSCSI acceleration, +in addition to standard L2 Ethernet traffic, +all on the same controller. +The following features are supported in the +.Nm +driver under +.Ox : +.Bd -literal -offset indent +IPv4 receive IP/TCP/UDP checksum offload +Jumbo frames (up to 9022 bytes) +VLAN tag insertion +Interrupt coalescing +10/100/1000Mbps operation in full-duplex mode +10/100Mbps operation in half-duplex mode +.Ed +.Pp +The +.Nm +driver supports the following media types: +.Bl -tag -width ".Cm 10baseT/UTP" +.It Cm autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode via +.Xr ifconfig 8 . +.It Cm 10baseT/UTP +Set 10Mbps operation. +The +.Xr ifconfig 8 +.Ic mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 100baseTX +Set 100Mbps (Fast Ethernet) operation. +The +.Xr ifconfig 8 +.Ic mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 1000baseTX +Set 1000baseTX operation over twisted pair. +Only +.Cm full-duplex +mode is supported. +.El +.Pp +The +.Nm +driver supports the following media options: +.Bl -tag -width ".Cm full-duplex" +.It Cm full-duplex +Force full duplex operation. +.It Cm half-duplex +Force half duplex operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh SEE ALSO +.Xr arp 4 , +.Xr brgphy 4 , +.Xr ifmedia 4 , +.Xr intro 4 , +.Xr mii 4 , +.Xr netintro 4 , +.Xr pci 4 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Nx 4.0 . diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC index 302f5f2c8283..b4e196a28b87 100644 --- a/sys/arch/amd64/conf/GENERIC +++ b/sys/arch/amd64/conf/GENERIC @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC,v 1.122 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: GENERIC,v 1.123 2006/12/17 23:02:06 bouyer Exp $ # # GENERIC machine description file # @@ -22,7 +22,7 @@ include "arch/amd64/conf/std.amd64" options INCLUDE_CONFIG_FILE # embed config file in kernel binary -#ident "GENERIC-$Revision: 1.122 $" +#ident "GENERIC-$Revision: 1.123 $" maxusers 32 # estimated number of users @@ -523,6 +523,7 @@ an* at pci? dev ? function ? # Aironet PC4500/PC4800 (802.11) ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 bce* at pci? dev ? function ? # Broadcom 440x 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet dge* at pci? dev ? function ? # Intel 82597 10GbE LR en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x diff --git a/sys/arch/amd64/conf/INSTALL b/sys/arch/amd64/conf/INSTALL index d34b21152d3d..af1f901721b4 100644 --- a/sys/arch/amd64/conf/INSTALL +++ b/sys/arch/amd64/conf/INSTALL @@ -1,4 +1,4 @@ -# $NetBSD: INSTALL,v 1.61 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: INSTALL,v 1.62 2006/12/17 23:02:06 bouyer Exp $ # # GENERIC machine description file # @@ -20,7 +20,7 @@ include "arch/amd64/conf/std.amd64" -#ident "INSTALL-$Revision: 1.61 $" +#ident "INSTALL-$Revision: 1.62 $" maxusers 32 # estimated number of users @@ -414,6 +414,7 @@ an* at pci? dev ? function ? # Aironet PC4500/PC4800 (802.11) ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x epic* at pci? dev ? function ? # SMC EPIC/100 Ethernet diff --git a/sys/arch/i386/conf/ALL b/sys/arch/i386/conf/ALL index 36a7cf6500f8..931a7f2ef2ac 100644 --- a/sys/arch/i386/conf/ALL +++ b/sys/arch/i386/conf/ALL @@ -1,4 +1,4 @@ -# $NetBSD: ALL,v 1.75 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: ALL,v 1.76 2006/12/17 23:02:06 bouyer Exp $ # From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp # # ALL machine description file @@ -17,7 +17,7 @@ include "arch/i386/conf/std.i386" options INCLUDE_CONFIG_FILE # embed config file in kernel binary -#ident "ALL-$Revision: 1.75 $" +#ident "ALL-$Revision: 1.76 $" maxusers 32 # estimated number of users @@ -812,6 +812,7 @@ ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 atw* at pci? dev ? function ? # ADMtek ADM8211 (802.11) bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet dge* at pci? dev ? function ? # Intel 82597 10GbE LR en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC index 36ef4ea75497..1b7a18827d0a 100644 --- a/sys/arch/i386/conf/GENERIC +++ b/sys/arch/i386/conf/GENERIC @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC,v 1.802 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: GENERIC,v 1.803 2006/12/17 23:02:06 bouyer Exp $ # # GENERIC machine description file # @@ -22,7 +22,7 @@ include "arch/i386/conf/std.i386" options INCLUDE_CONFIG_FILE # embed config file in kernel binary -#ident "GENERIC-$Revision: 1.802 $" +#ident "GENERIC-$Revision: 1.803 $" maxusers 32 # estimated number of users @@ -834,6 +834,7 @@ ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 atw* at pci? dev ? function ? # ADMtek ADM8211 (802.11) bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet dge* at pci? dev ? function ? # Intel 82597 10GbE LR en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x diff --git a/sys/arch/i386/conf/GENERIC_LAPTOP b/sys/arch/i386/conf/GENERIC_LAPTOP index 586a39557f0e..9397ffc7eda3 100644 --- a/sys/arch/i386/conf/GENERIC_LAPTOP +++ b/sys/arch/i386/conf/GENERIC_LAPTOP @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC_LAPTOP,v 1.217 2006/11/30 21:01:16 bouyer Exp $ +# $NetBSD: GENERIC_LAPTOP,v 1.218 2006/12/17 23:02:06 bouyer Exp $ # From: NetBSD: GENERIC,v 1.414 2001/07/30 19:59:05 ad Exp # # GENERIC_LAPTOP -- GENERIC with cardbus and some USB devices enabled @@ -8,7 +8,7 @@ include "arch/i386/conf/std.i386" options INCLUDE_CONFIG_FILE # embed config file in kernel binary -#ident "GENERIC-$Revision: 1.217 $" +#ident "GENERIC-$Revision: 1.218 $" maxusers 32 # estimated number of users @@ -601,6 +601,7 @@ fd* at fdc? drive ? # the drives themselves ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet ex* at pci? dev ? function ? # 3Com 90x[BC] fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100 diff --git a/sys/arch/i386/conf/INSTALL b/sys/arch/i386/conf/INSTALL index a5d64ed8e1c4..27dbcf13d67c 100644 --- a/sys/arch/i386/conf/INSTALL +++ b/sys/arch/i386/conf/INSTALL @@ -1,4 +1,4 @@ -# $NetBSD: INSTALL,v 1.298 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: INSTALL,v 1.299 2006/12/17 23:02:06 bouyer Exp $ # # INSTALL - Installation kernel. # @@ -512,6 +512,7 @@ ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 atw* at pci? dev ? function ? # ADMtek ADM8211 (802.11) bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x Gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet #en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x ex* at pci? dev ? function ? # 3Com 90x[BC] diff --git a/sys/arch/i386/conf/INSTALL_LAPTOP b/sys/arch/i386/conf/INSTALL_LAPTOP index 5060e10a1951..b88ed4a13bad 100644 --- a/sys/arch/i386/conf/INSTALL_LAPTOP +++ b/sys/arch/i386/conf/INSTALL_LAPTOP @@ -1,4 +1,4 @@ -# $NetBSD: INSTALL_LAPTOP,v 1.111 2006/11/30 21:01:16 bouyer Exp $ +# $NetBSD: INSTALL_LAPTOP,v 1.112 2006/12/17 23:02:06 bouyer Exp $ # # INSTALL - Installation kernel. # @@ -432,6 +432,7 @@ fd* at fdc? drive ? # the drives themselves ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet ex* at pci? dev ? function ? # 3Com 90x[BC] fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B ipw* at pci? dev ? function ? # Intel PRO/Wireless 2100 diff --git a/sys/arch/i386/conf/XEN2_DOM0 b/sys/arch/i386/conf/XEN2_DOM0 index 89a3c450d8cf..425021576159 100644 --- a/sys/arch/i386/conf/XEN2_DOM0 +++ b/sys/arch/i386/conf/XEN2_DOM0 @@ -1,4 +1,4 @@ -# $NetBSD: XEN2_DOM0,v 1.19 2006/12/17 22:57:15 bouyer Exp $ +# $NetBSD: XEN2_DOM0,v 1.20 2006/12/17 23:02:06 bouyer Exp $ include "arch/xen/conf/std.xen" @@ -264,6 +264,7 @@ ath* at pci? dev ? function ? # Atheros 5210/5211/5212 802.11 atw* at pci? dev ? function ? # ADMtek ADM8211 (802.11) bce* at pci? dev ? function ? # Broadcom 4401 10/100 Ethernet bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet +bnx* at pci? dev ? function ? # Broadcom NetXtremeII gigabit Ethernet dge* at pci? dev ? function ? # Intel 82597 10GbE LR en* at pci? dev ? function ? # ENI/Adaptec ATM ep* at pci? dev ? function ? # 3Com 3c59x diff --git a/sys/dev/microcode/bnx/bnxfw.h b/sys/dev/microcode/bnx/bnxfw.h new file mode 100644 index 000000000000..233fb548ce88 --- /dev/null +++ b/sys/dev/microcode/bnx/bnxfw.h @@ -0,0 +1,3510 @@ +/* $OpenBSD: bnxfw.h,v 1.2 2006/08/10 04:01:52 brad Exp $ */ + +/*- + * Copyright (c) 2006 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bce/if_bcefw.h,v 1.1 2006/04/10 19:55:23 ps Exp $ + */ + +/* + * This file contains firmware data derived from proprietary unpublished + * source code, Copyright (c) 2004, 2005 Broadcom Corporation. + * + * Permission is hereby granted for the distribution of this firmware data + * in hexadecimal or equivalent format, provided this copyright notice is + * accompanying it. + */ + +static int bnx_COM_b06FwReleaseMajor = 0x1; +static int bnx_COM_b06FwReleaseMinor = 0x0; +static int bnx_COM_b06FwReleaseFix = 0x0; +static u_int32_t bnx_COM_b06FwStartAddr = 0x080008b4; +static u_int32_t bnx_COM_b06FwTextAddr = 0x08000000; +static int bnx_COM_b06FwTextLen = 0x57bc; +static u_int32_t bnx_COM_b06FwDataAddr = 0x08005840; +static int bnx_COM_b06FwDataLen = 0x0; +static u_int32_t bnx_COM_b06FwRodataAddr = 0x080057c0; +static int bnx_COM_b06FwRodataLen = 0x58; +static u_int32_t bnx_COM_b06FwBssAddr = 0x08005860; +static int bnx_COM_b06FwBssLen = 0x88; +static u_int32_t bnx_COM_b06FwSbssAddr = 0x08005840; +static int bnx_COM_b06FwSbssLen = 0x1c; +static u_int32_t bnx_COM_b06FwText[(0x57bc/4) + 1] = { + 0x0a00022d, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x322e352e, + 0x38000000, 0x02050802, 0x00000000, 0x00000003, 0x00000014, 0x00000032, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000010, 0x000003e8, 0x0000ea60, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000002, 0x00000020, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 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0x8f420000, 0x30420010, 0x1040fffd, 0x262258c0, + 0x9444000a, 0x94430018, 0xaf800010, 0xaf850018, 0x14830012, 0x262758c0, + 0x0e00155a, 0x00000000, 0x1600000e, 0x262758c0, 0x0e00148e, 0x00000000, + 0x0a001517, 0x262758c0, 0x00041c00, 0x00031c03, 0x00051400, 0x00021403, + 0x00621823, 0x18600002, 0x3c026000, 0xac400808, 0x262758c0, 0x94e2000e, + 0x94e3000c, 0x24420001, 0xa4e2000e, 0x3042ffff, 0x50430001, 0xa4e0000e, + 0x12000005, 0x3c02000a, 0x94e2000a, 0xa74200a2, 0x0a001554, 0x02401021, + 0x03421821, 0x94640006, 0x94e2000a, 0x00441023, 0x00021400, 0x00021c03, + 0x04610006, 0xa4e40006, 0x0000000d, 0x00000000, 0x2400005a, 0x0a001536, + 0x24020001, 0x8f820014, 0x0062102b, 0x14400002, 0x00001021, 0x24020001, + 0x304200ff, 0x1040001b, 0x3c020800, 0x3c06000a, 0x244558c0, 0x94a8000a, + 0x8f870014, 0x03461021, 0x94430006, 0x00402021, 0xa4a30006, 0x94820006, + 0xa4a20006, 0x01021023, 0x00021400, 0x00021403, 0x04410006, 0x0047102b, + 0x0000000d, 0x00000000, 0x2400005a, 0x0a001550, 0x24020001, 0x14400002, + 0x00001021, 0x24020001, 0x304200ff, 0x1440ffec, 0x03461021, 0x02401021, + 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, + 0x3c020800, 0x244558c0, 0x94a3001a, 0x8ca40024, 0x00403021, 0x000318c0, + 0x00832021, 0xaf44003c, 0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, + 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, + 0x1040fffd, 0x00000000, 0x8f430400, 0x24c658c0, 0xacc30010, 0x8f420404, + 0x3c030020, 0xacc20014, 0xaf430030, 0x94c40018, 0x94c3001c, 0x94c2001a, + 0x94c5001e, 0x00832021, 0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, + 0xa4c40018, 0xa4c0001a, 0x03e00008, 0x00000000, 0x8f820010, 0x3c030006, + 0x00021140, 0x00431025, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, + 0x27430400, 0x8f420000, 0x30420010, 0x1040fffd, 0x00000000, 0xaf800010, + 0xaf830018, 0x03e00008, 0x00000000, 0x27bdffe8, 0xafb00010, 0x3c100800, + 0x261058c0, 0x3c05000a, 0x02002021, 0x03452821, 0xafbf0014, 0x0e0015b0, + 0x2406000a, 0x96020002, 0x9603001e, 0x3042000f, 0x24420003, 0x00431804, + 0x24027fff, 0x0043102b, 0xaf830014, 0x10400004, 0x00000000, 0x0000000d, + 0x00000000, 0x24000043, 0x0e00155a, 0x00000000, 0x8fbf0014, 0x8fb00010, + 0x03e00008, 0x27bd0018, 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, + 0x24a50004, 0xac820000, 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, + 0x0a0015c1, 0x00a01021, 0xac860000, 0x00000000, 0x00000000, 0x24840004, + 0x00a01021, 0x1440fffa, 0x24a5ffff, 0x03e00008, 0x00000000, 0x3c036000, + 0x8c642b7c, 0x3c036010, 0x8c6553fc, 0x00041582, 0x00042302, 0x308403ff, + 0x00052d82, 0x00441026, 0x0002102b, 0x0005282b, 0x00451025, 0x1440000d, + 0x3c020050, 0x34420004, 0xaf400038, 0xaf40003c, 0xaf420030, 0x00000000, + 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, 0x3c020020, 0xaf420030, + 0x0000000d, 0x03e00008, 0x00000000, 0x3c020050, 0x34420004, 0xaf440038, + 0xaf45003c, 0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, + 0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008, 0x00000000, 0x00000000}; + +static u_int32_t bnx_COM_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_COM_b06FwRodata[(0x58/4) + 1] = { + 0x08002428, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, + 0x08002380, 0x0800245c, 0x080023e4, 0x0800245c, 0x0800231c, 0x0800245c, + 0x0800245c, 0x0800245c, 0x08002328, 0x00000000, 0x08003240, 0x08003270, + 0x080032a0, 0x080032d0, 0x08003300, 0x00000000, 0x00000000 }; +static u_int32_t bnx_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; +static u_int32_t bnx_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; + +static int bnx_RXP_b06FwReleaseMajor = 0x1; +static int bnx_RXP_b06FwReleaseMinor = 0x0; +static int bnx_RXP_b06FwReleaseFix = 0x0; +static u_int32_t bnx_RXP_b06FwStartAddr = 0x08003184; +static u_int32_t bnx_RXP_b06FwTextAddr = 0x08000000; +static int bnx_RXP_b06FwTextLen = 0x588c; +static u_int32_t bnx_RXP_b06FwDataAddr = 0x080058e0; +static int bnx_RXP_b06FwDataLen = 0x0; +static u_int32_t bnx_RXP_b06FwRodataAddr = 0x08005890; +static int bnx_RXP_b06FwRodataLen = 0x28; +static u_int32_t bnx_RXP_b06FwBssAddr = 0x08005900; +static int bnx_RXP_b06FwBssLen = 0x13a4; +static u_int32_t bnx_RXP_b06FwSbssAddr = 0x080058e0; +static int bnx_RXP_b06FwSbssLen = 0x1c; +static u_int32_t bnx_RXP_b06FwText[(0x588c/4) + 1] = { + 0x0a000c61, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x322e362e, + 0x31000000, 0x02060103, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 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0x8f420148, 0x24030002, + 0x3044ffff, 0x00021402, 0x305000ff, 0x1203000c, 0x27510180, 0x2a020003, + 0x10400005, 0x24020003, 0x0600001d, 0x36053000, 0x0a001027, 0x3c038000, + 0x12020007, 0x00000000, 0x0a001034, 0x00000000, 0x0e00112c, 0x00000000, + 0x0a001025, 0x00402021, 0x0e00113e, 0x00000000, 0x00402021, 0x36053000, + 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0xa6250008, + 0xa222000b, 0xa6240010, 0x8f420144, 0x3c031000, 0xae220024, 0xaf4301b8, + 0x0a001040, 0x3c024000, 0x0000000d, 0x00000000, 0x240002bf, 0x0a001040, + 0x3c024000, 0x0e001441, 0x00000000, 0x0a001040, 0x3c024000, 0x0e0015ea, + 0x00000000, 0x3c024000, 0xaf420178, 0x00000000, 0x8fbf0018, 0x8fb10014, + 0x8fb00010, 0x03e00008, 0x27bd0020, 0x24020800, 0x03e00008, 0xaf4201b8, + 0x27bdffe8, 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, + 0x2403ff7f, 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, + 0x3c020008, 0xaf430008, 0x8e040808, 0x0342d825, 0x8e020808, 0x3c030800, + 0xac600020, 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0x32e20020, 0x10400011, 0x00000000, 0x96c20012, 0x0052102b, + 0x10400008, 0x97a20020, 0x96d20012, 0x12400003, 0x02721021, 0x0a0012f2, + 0x2451ffff, 0x02608821, 0x97a20020, 0x93a3001a, 0x34420008, 0x34630004, + 0xa7a20020, 0xa3a3001a, 0x8f420104, 0x3c030080, 0x00431024, 0x10400037, + 0x3a03000a, 0x0e001151, 0x02c02021, 0x24030002, 0x1443002b, 0x3c030800, + 0x27a60010, 0x97a20020, 0x27450180, 0x3c038000, 0xafb40028, 0x34420001, + 0xa7a20020, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x00000000, 0x8f420128, + 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, 0xaca30018, 0x90c4000a, + 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, 0xa4a20010, 0x90c30012, + 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, 0xaca30014, 0x8cc20024, + 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc4002c, 0x24020001, 0x3c031000, + 0xaca4002c, 0xaf4301b8, 0xaf400044, 0xaf400050, 0x0a001436, 0x8fbf006c, + 0x8c626c98, 0x30420100, 0x10400003, 0x24636c98, 0x8c620004, 0xaf62017c, + 0x3a03000a, 0x2c630001, 0x3a02000c, 0x2c420001, 0x00621825, 0x14600003, + 0x2402000e, 0x56020030, 0x00009021, 0x52400008, 0x96c4000e, 0x12400004, + 0xa7b20040, 0x02721021, 0x0a001343, 0x2451ffff, 0x02608821, 0x96c4000e, + 0x93630035, 0x8f62004c, 0x00642004, 0x00952021, 0x00821023, 0x18400015, + 0x00000000, 0x8f620018, 0x02621023, 0x1c400015, 0x97a20020, 0x8f620018, + 0x1662001c, 0x00000000, 0x8f62001c, 0x02a21023, 0x1c40000e, 0x97a20020, + 0x8f62001c, 0x16a20015, 0x00000000, 0x8f620058, 0x00821023, 0x18400011, + 0x97a20020, 0x0a001364, 0xafb10028, 0x8f620058, 0x00821023, 0x0441000b, + 0x97a20020, 0xafb10028, 0xafb30034, 0xafb50038, 0xafa4003c, 0x34420020, + 0x0a00136d, 0xa7a20020, 0x02809821, 0x02608821, 0x8f640058, 0x8f62004c, + 0x02a21023, 0x18400009, 0x00000000, 0x8f620054, 0x02a21023, 0x1c400005, + 0x97a20020, 0xafb10028, 0xafb50024, 0x0a001385, 0x34420040, 0x9742011a, + 0x1440000c, 0x24020014, 0x8f620058, 0x14820009, 0x24020014, 0x8f63004c, + 0x8f620054, 0x10620004, 0x97a20020, 0xafb10028, 0x34420080, 0xa7a20020, + 0x24020014, 0x1202000a, 0x2a020015, 0x10400005, 0x2402000c, 0x12020006, + 0x32e20001, 0x0a0013c6, 0x00000000, 0x24020016, 0x16020035, 0x32e20001, + 0x8f620084, 0x24420001, 0x16a20031, 0x32e20001, 0x24020014, 0x12020021, + 0x2a020015, 0x10400005, 0x2402000c, 0x12020008, 0x32e20001, 0x0a0013c6, + 0x00000000, 0x24020016, 0x1202000c, 0x32e20001, 0x0a0013c6, 0x00000000, + 0x97a30020, 0x2402000e, 0xafb10028, 0xa3b00022, 0xa3a20023, 0xafb50024, + 0x34630054, 0x0a0013c5, 0xa7a30020, 0x97a20020, 0x93a4001a, 0x24030010, + 0xafb10028, 0xa3b00022, 0xa3a30023, 0xafb50024, 0x3442005d, 0x34840002, + 0xa7a20020, 0x0a0013c5, 0xa3a4001a, 0x97a20020, 0x24030012, 0xa3a30023, + 0x93a3001a, 0xafb10028, 0xa3b00022, 0xafb50024, 0x3042fffe, 0x3442005c, + 0x34630002, 0xa7a20020, 0xa3a3001a, 0x32e20001, 0x10400030, 0x2402000c, + 0x12020013, 0x2a02000d, 0x10400005, 0x2402000a, 0x12020008, 0x97a20020, + 0x0a0013f8, 0x32e20009, 0x2402000e, 0x1202001b, 0x32e20009, 0x0a0013f9, + 0x0002102b, 0x93a4001a, 0x24030008, 0xafb10028, 0xa3b00022, 0xa3a30023, + 0x0a0013f4, 0x34420013, 0x97a30020, 0x30620004, 0x14400005, 0x93a2001a, + 0x3463001b, 0xa7a30020, 0x0a0013e7, 0x24030016, 0x3463001b, 0xa7a30020, + 0x24030010, 0xafb10028, 0xa3b00022, 0xa3a30023, 0x34420002, 0x0a0013f7, + 0xa3a2001a, 0x97a20020, 0x93a4001a, 0x24030010, 0xafb10028, 0xa3b00022, + 0xa3a30023, 0x3442001b, 0x34840002, 0xa7a20020, 0xa3a4001a, 0x32e20009, + 0x0002102b, 0x00021023, 0x30420007, 0x12400015, 0x34450003, 0x8f820018, + 0x24030800, 0x27440180, 0x24420001, 0xaf820018, 0x24020004, 0xaf4301b8, + 0xa4850008, 0xa082000b, 0x93430120, 0x00003021, 0x3c021000, 0xa492000e, + 0xac950024, 0xac930028, 0x007e1821, 0xa483000c, 0xaf4201b8, 0x0a001413, + 0x97a20020, 0x24060001, 0x97a20020, 0x10400020, 0x27450180, 0x3c038000, + 0x8f4201b8, 0x00431024, 0x1440fffd, 0x00000000, 0x8f420128, 0xaca20000, + 0x8fa30028, 0x240240c1, 0xa4a20008, 0xaca30018, 0x93a4001a, 0x24020002, + 0xa0a2000b, 0xa0a4000a, 0x97a20020, 0xa4a20010, 0x93a30022, 0xa0a30012, + 0x93a20023, 0xa0a20013, 0x8fa30024, 0xaca30014, 0x8fa20034, 0xaca20024, + 0x8fa30038, 0xaca30028, 0x8fa2003c, 0x3c031000, 0xaca2002c, 0xaf4301b8, + 0x00c01021, 0x8fbf006c, 0x8fbe0068, 0x8fb70064, 0x8fb60060, 0x8fb5005c, + 0x8fb40058, 0x8fb30054, 0x8fb20050, 0x8fb1004c, 0x8fb00048, 0x03e00008, + 0x27bd0070, 0x8f470140, 0x8f460148, 0x3c028000, 0x00c24024, 0x00062c02, + 0x30a300ff, 0x24020019, 0x106200e7, 0x27440180, 0x2862001a, 0x1040001f, + 0x24020008, 0x106200be, 0x28620009, 0x1040000d, 0x24020001, 0x10620046, + 0x28620002, 0x50400005, 0x24020006, 0x1060002e, 0x00a01821, 0x0a00155e, + 0x00000000, 0x1062005b, 0x00a01821, 0x0a00155e, 0x00000000, 0x2402000b, + 0x10620084, 0x2862000c, 0x10400005, 0x24020009, 0x106200bc, 0x00061c02, + 0x0a00155e, 0x00000000, 0x2402000e, 0x106200b7, 0x00061c02, 0x0a00155e, + 0x00000000, 0x28620021, 0x10400009, 0x2862001f, 0x104000c1, 0x2402001b, + 0x106200bf, 0x2402001c, 0x1062009a, 0x00061c02, 0x0a00155e, 0x00000000, + 0x240200c2, 0x106200ca, 0x286200c3, 0x10400005, 0x24020080, 0x1062005a, + 0x00a01821, 0x0a00155e, 0x00000000, 0x240200c9, 0x106200cd, 0x30c5ffff, + 0x0a00155e, 0x00000000, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, + 0x24020001, 0xa4830008, 0x24030002, 0xac870000, 0xac800004, 0xa082000a, + 0xa083000b, 0xa4860010, 0x8f430144, 0x3c021000, 0xac800028, 0xac830024, + 0x3c036000, 0xaf4201b8, 0x03e00008, 0xac600808, 0x11000009, 0x00a01821, + 0x3c020800, 0x24030002, 0xa0436c88, 0x24426c88, 0xac470008, 0x8f430144, + 0x03e00008, 0xac430004, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, + 0x24020002, 0xac800000, 0xac870004, 0xa4830008, 0xa082000a, 0xa082000b, + 0xa4860010, 0xac800024, 0x8f420144, 0x3c031000, 0xac820028, 0x3c026000, + 0xaf4301b8, 0x03e00008, 0xac400808, 0x3c080800, 0x3c058000, 0x8f4201b8, + 0x00451024, 0x1440fffd, 0x00000000, 0xac870000, 0x91026c88, 0x00002821, + 0x10400002, 0x25076c88, 0x8ce50008, 0xac850004, 0xa4830008, 0x91036c88, + 0x24020002, 0xa082000b, 0xa4860010, 0x34630001, 0xa083000a, 0x8f420144, + 0xac820024, 0x91036c88, 0x10600002, 0x00001021, 0x8ce20004, 0xac820028, + 0x3c021000, 0xaf4201b8, 0x3c026000, 0xa1006c88, 0x03e00008, 0xac400808, + 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xa082000b, + 0xa4830008, 0xa4860010, 0x8f420144, 0x3c031000, 0xa4820012, 0x03e00008, + 0xaf4301b8, 0x30c2ffff, 0x14400028, 0x00061c02, 0x93620005, 0x30420004, + 0x14400020, 0x3c029000, 0x34420001, 0x00e21025, 0xaf420020, 0x3c038000, + 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, + 0x34630001, 0x00e31825, 0x34420004, 0xa3620005, 0xaf430020, 0x93620005, + 0x30420004, 0x14400003, 0x3c038000, 0x0000000d, 0x3c038000, 0x8f4201b8, + 0x00431024, 0x1440fffd, 0x24020005, 0x3c031000, 0xac870000, 0xa082000b, + 0xaf4301b8, 0x0a00150d, 0x00061c02, 0x0000000d, 0x03e00008, 0x00000000, + 0x00061c02, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, + 0xa4830008, 0x24030002, 0xac870000, 0xac800004, 0xa082000a, 0xa083000b, + 0xa4860010, 0x8f430144, 0x3c021000, 0xac800028, 0xac830024, 0x03e00008, + 0xaf4201b8, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, + 0xac800000, 0xac870004, 0xa4830008, 0xa082000a, 0xa082000b, 0xa4860010, + 0xac800024, 0x8f420144, 0x3c031000, 0xac820028, 0x03e00008, 0xaf4301b8, + 0x00061c02, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, + 0xa4830008, 0x24030002, 0xa082000a, 0x3c021000, 0xac870000, 0xac800004, + 0xa083000b, 0xa4860010, 0xac800024, 0xac800028, 0x03e00008, 0xaf4201b8, + 0x00a01821, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, + 0xac870000, 0xac800004, 0xa4830008, 0xa080000a, 0x0a001518, 0xa082000b, + 0x8f440144, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, + 0x240340c9, 0xaf470180, 0xa342018b, 0x3c021000, 0xa7430188, 0xaf4401a4, + 0xaf4501a8, 0xaf4001ac, 0x03e00008, 0xaf4201b8, 0x0000000d, 0x03e00008, + 0x00000000, 0x03e00008, 0x00000000, 0x8f420100, 0x3042003e, 0x14400011, + 0x24020001, 0xaf400048, 0x8f420100, 0x304207c0, 0x10400005, 0x00000000, + 0xaf40004c, 0xaf400050, 0x03e00008, 0x24020001, 0xaf400054, 0xaf400040, + 0x8f420100, 0x30423800, 0x54400001, 0xaf400044, 0x24020001, 0x03e00008, + 0x00000000, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, + 0x240340c9, 0xaf440180, 0xa342018b, 0x3c021000, 0xa7430188, 0xaf4501a4, + 0xaf4601a8, 0xaf4701ac, 0x03e00008, 0xaf4201b8, 0x3c029000, 0x34420001, + 0x00822025, 0xaf440020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, + 0x00000000, 0x03e00008, 0x00000000, 0x3c028000, 0x34420001, 0x00822025, + 0x03e00008, 0xaf440020, 0x308600ff, 0x27450180, 0x3c038000, 0x8f4201b8, + 0x00431024, 0x1440fffd, 0x00000000, 0x8f420128, 0xaca20000, 0x8f640040, + 0x24030008, 0x240240c1, 0xa4a20008, 0x24020002, 0xa0a2000b, 0x3c021000, + 0xa0a6000a, 0xa4a30010, 0xa0a00012, 0xa0a00013, 0xaca00014, 0xaca00024, + 0xaca00028, 0xaca0002c, 0xaca40018, 0x03e00008, 0xaf4201b8, 0x24020001, + 0xacc40000, 0x03e00008, 0xa4e50000, 0x24020001, 0xaf400044, 0x03e00008, + 0xaf400050, 0x00803021, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, + 0x1440fffd, 0x00000000, 0x8f420128, 0xaca20000, 0x8cc30018, 0x240240c1, + 0xa4a20008, 0xaca30018, 0x90c4000a, 0x24020002, 0xa0a2000b, 0xa0a4000a, + 0x94c20010, 0xa4a20010, 0x90c30012, 0xa0a30012, 0x90c20013, 0xa0a20013, + 0x8cc30014, 0xaca30014, 0x8cc20024, 0xaca20024, 0x8cc30028, 0xaca30028, + 0x8cc2002c, 0x3c031000, 0xaca2002c, 0x24020001, 0xaf4301b8, 0xaf400044, + 0x03e00008, 0xaf400050, 0x27bdffe8, 0xafbf0010, 0x0e001047, 0x00000000, + 0x00002021, 0x0e000c78, 0xaf400180, 0x8fbf0010, 0x03e00008, 0x27bd0018, + 0x8f460148, 0x27450180, 0x3c038000, 0x00061402, 0x304700ff, 0x8f4201b8, + 0x00431024, 0x1440fffd, 0x00000000, 0x8f440140, 0x00061202, 0x304200ff, + 0x00061c02, 0xaca20004, 0x24020002, 0xa4a30008, 0x30c300ff, 0xa0a2000b, + 0xaca30024, 0x10e0000a, 0xaca40000, 0x28e20004, 0x14400005, 0x24020001, + 0x24020005, 0x54e20005, 0xa0a0000a, 0x24020001, 0x0a001609, 0xa0a2000a, + 0xa0a0000a, 0x3c021000, 0x03e00008, 0xaf4201b8, 0x03e00008, 0x00001021, + 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, + 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a00161f, 0x00a01021, + 0xac860000, 0x00000000, 0x00000000, 0x24840004, 0x00a01021, 0x1440fffa, + 0x24a5ffff, 0x03e00008, 0x00000000, 0x00000000 }; + +static u_int32_t bnx_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_RXP_b06FwRodata[(0x28/4) + 1] = { + 0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680, + 0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 }; +static u_int32_t bnx_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 }; +static u_int32_t bnx_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; + +static u_int32_t bnx_rv2p_proc1[] = { + 0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x203f0146, + 0x00000010, 0x213f0003, 0x00000010, 0x20bf002b, 0x00000018, 0x8000fffd, + 0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002, + 0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002, + 0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004, + 0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9, + 0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030, + 0x00000018, 0x00040000, 0x00000018, 0x80000016, 0x00000018, 0x80000018, + 0x00000018, 0x8000001c, 0x00000018, 0x8000004d, 0x00000018, 0x8000008d, + 0x00000018, 0x80000010, 0x00000018, 0x8000000f, 0x00000018, 0x8000000e, + 0x00000018, 0x8000000d, 0x00000018, 0x800000c3, 0x00000018, 0x8000000b, + 0x00000018, 0x8000000a, 0x00000018, 0x80000009, 0x00000018, 0x800000fe, + 0x00000018, 0x80000007, 0x00000018, 0x80000006, 0x00000018, 0x80000100, + 0x00000018, 0x80000105, 0x00000018, 0x80000003, 0x00000018, 0x80000099, + 0x00000018, 0x80000123, 0x00000018, 0x80000000, 0x0000000c, 0x1f800001, + 0x00000000, 0x00000000, 0x00000018, 0x8000ffb9, 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, + 0x00000018, 0x8000ffb4, 0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, + 0x00000018, 0x80000013, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, + 0x00000000, 0x31040000, 0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, 0x00000010, 0x00220002, 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, 0x00000008, 0x22000001, 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, 0x00000008, 0x2a000003, 0x00000018, 0x8000ff82, + 0x00000010, 0xb1a0b01d, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800150, 0x00000000, 0x00000000, 0x00000010, 0x205f0000, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, + 0x00000000, 0x060e0000, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, 0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, + 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400, 0x00000010, 0xb1963220, + 0x00000008, 0x0f800000, 0x00000018, 0x8000001e, 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, + 0x00000010, 0x91d40000, 0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, 0x00000000, 0x02630000, 0x0000000f, 0x47620010, + 0x00000000, 0x0ce71800, 0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, + 0x00000000, 0x31840000, 0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, + 0x00000001, 0x31620800, 0x0000000f, 0x020e0010, 0x00000002, 0x31620800, + 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, + 0x00000008, 0x0f800000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x0000000c, 0x61420006, 0x00000008, 0x22000008, 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000004, 0x00000018, 0x8000ff41, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, + 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x00000008, 0xac000001, 0x00000018, 0x8000000e, + 0x00000000, 0x0380b000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d800101, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, 0x00000018, 0x8000ff26, 0x00000010, 0xb1a0b016, + 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, 0x00000000, 0x2c200000, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800150, 0x00000000, 0x00000000, 0x00000010, 0x205f0000, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, + 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, + 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000, 0x00000018, 0x8000ff10, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800108, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, + 0x00000018, 0x8000ff06, 0x00000000, 0x82265600, 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, 0x00000008, 0x070e0008, 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, 0x00000008, 0x82850001, 0x00000000, 0x02840a00, + 0x00000007, 0x42851c00, 0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, + 0x00000010, 0x001f0000, 0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, + 0x00000000, 0x00000000, 0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, 0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, 0x00000010, 0xb1963202, 0x00000008, 0x0f800005, + 0x00000010, 0x00220020, 0x00000000, 0x02a70000, 0x00000010, 0xb1850002, + 0x00000008, 0x82850200, 0x00000000, 0x02000000, 0x00000000, 0x03a60000, + 0x00000018, 0x80000053, 0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, + 0x00000000, 0x870e1e00, 0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, + 0x00000010, 0xb18e0003, 0x00000018, 0x8000004c, 0x00000018, 0x8000fffa, + 0x00000010, 0x918c0003, 0x00000010, 0xb1870002, 0x00000018, 0x80000048, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x00000000, 0x2a860000, + 0x00000000, 0x230c0000, 0x00000000, 0x2b070000, 0x00000010, 0xb187000e, + 0x00000008, 0x2a000008, 0x00000018, 0x80000040, 0x00000010, 0x91d40000, + 0x00000000, 0x28d18c00, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, + 0x00000000, 0x2b070000, 0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, 0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, + 0x00000000, 0x2b000000, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, + 0x00000018, 0x8000fec7, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, 0x00000008, 0x2a000009, 0x00000018, 0x8000fec2, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000000, 0x29420000, 0x00000008, 0x2a000002, 0x00000018, 0x8000febc, + 0x00000018, 0x8000febb, 0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, 0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001, + 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, + 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, 0x00000018, 0x8000fea5, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, + 0x0000000c, 0x29800000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, 0x00000008, 0x2a000006, 0x00000018, 0x8000fe9b, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000008, 0x2a00000b, 0x00000018, 0x8000fe96, 0x00000008, 0x03050004, + 0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00, + 0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800, + 0x00000000, 0x83871800, 0x00000018, 0x00020000 +}; + +static u_int32_t bnx_rv2p_proc2[] = { + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, 0x00000008, 0x02540003, 0x00000018, 0x00040000, + 0x00000018, 0x8000000b, 0x00000018, 0x8000000b, 0x00000018, 0x8000000f, + 0x00000018, 0x8000004c, 0x00000018, 0x800001bd, 0x00000018, 0x800001e5, + 0x00000018, 0x8000019f, 0x00000018, 0x800001fd, 0x00000018, 0x800001a3, + 0x00000018, 0x800001aa, 0x00000018, 0x8000022f, 0x00000018, 0x80000000, + 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, 0x00000018, 0x8000ffed, 0x0000000c, 0x29800001, + 0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000, + 0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000, + 0x00000008, 0x02040012, 0x00000010, 0xb906082c, 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, + 0x00000000, 0x0c000000, 0x00000000, 0x0b800000, 0x00000008, 0x0cc60012, + 0x00000008, 0x0f800003, 0x00000000, 0x00000000, 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, 0x00000000, 0x66900000, 0x00000008, 0xa31b0012, + 0x00000010, 0xb197320d, 0x00000000, 0x25960000, 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0x009f0000, 0x00000000, 0x27002200, + 0x00000000, 0x26802000, 0x00000000, 0x231b0000, 0x0000000c, 0x69520001, + 0x00000018, 0x8000fff4, 0x00000010, 0x01130002, 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, 0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, + 0x00000000, 0x25960000, 0x0000000c, 0x29800000, 0x00000000, 0x32140000, + 0x00000000, 0x32950000, 0x00000000, 0x33160000, 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, 0x00000010, 0x20530000, 0x00000018, 0x8000ffb6, + 0x00000000, 0x23000000, 0x00000000, 0x25e60000, 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000018, 0x8000ffaf, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, + 0x00000009, 0x076000ff, 0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, + 0x00000008, 0x2d000064, 0x00000008, 0x2d80011c, 0x00000009, 0x06420002, + 0x0000000c, 0x61420001, 0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, + 0x00000000, 0x23000000, 0x00000004, 0x826da000, 0x00000000, 0x8304a000, + 0x00000000, 0x22c50c00, 0x00000000, 0x03760000, 0x00000004, 0x83860a00, + 0x00000000, 0x83870c00, 0x00000010, 0x91de0000, 0x00000000, 0x037c0000, + 0x00000000, 0x837b0c00, 0x00000001, 0x83060e00, 0x00000000, 0x83870c00, + 0x00000000, 0x82850e00, 0x00000010, 0xb1860016, 0x0000000f, 0x47610018, + 0x00000000, 0x068e0000, 0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, + 0x00000000, 0x870e1e00, 0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, + 0x00000008, 0x22000009, 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, 0x0000000c, 0x29800000, 0x00000000, 0x37ed0000, + 0x0000000c, 0x73e7001a, 0x00000010, 0x20530000, 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, 0x00000000, 0x02f60000, 0x00000004, 0x82840a00, + 0x00000010, 0xb1840a2b, 0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, + 0x00000004, 0xb6ed0a00, 0x00000000, 0x37ed0000, 0x00000018, 0x80000029, + 0x0000000c, 0x61420000, 0x00000000, 0x37040000, 0x00000000, 0x37850000, + 0x0000000c, 0x33e7001a, 0x00000018, 0x80000024, 0x00000010, 0xb96d0809, + 0x00000004, 0xb6ed0a00, 0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, + 0x00000010, 0x91ee0c1f, 0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, + 0x00000000, 0x37ed0000, 0x00000018, 0x8000001b, 0x0000000c, 0x61420000, + 0x00000010, 0xb7ee0a05, 0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, + 0x00000004, 0xb7ef0a00, 0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, + 0x00000008, 0x22000009, 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000008, 0x22000008, 0x0000000c, 0x61420004, 0x00000000, 0x37040000, + 0x00000000, 0x37850000, 0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, + 0x00000018, 0x80000004, 0x00000000, 0x02840000, 0x00000002, 0x21421800, + 0x0000000c, 0x61420000, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, 0x00000000, 0x23000000, 0x00000010, 0xb1840a40, + 0x00000010, 0x01420002, 0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, + 0x00000010, 0xb8040c3c, 0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, + 0x00000000, 0x0be60000, 0x00000000, 0x0c840000, 0x00000010, 0xb197320b, + 0x00000008, 0x0f800002, 0x00000018, 0x80000009, 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, 0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, + 0x00000000, 0x0be90000, 0x00000000, 0x0c840000, 0x00000010, 0xb1973202, + 0x00000008, 0x0f800002, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000, + 0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, 0x00000010, 0xb1973212, 0x00000000, 0x231b0000, + 0x00000000, 0x28840000, 0x00000000, 0x02043600, 0x00000003, 0x8384a000, + 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, 0x0000000c, 0x29000000, 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, 0x00000000, 0x06980000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003, + 0x00000018, 0x8000ffee, 0x00000000, 0x02043600, 0x00000000, 0x231b0000, + 0x00000000, 0x03840000, 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, + 0x00000002, 0x21421800, 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000, + 0x0000000c, 0x29000000, 0x00000000, 0x32140000, 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, 0x00000005, 0x74683000, 0x00000000, 0x33170000, + 0x00000018, 0x80000146, 0x00000010, 0x91c60005, 0x00000008, 0x07000004, + 0x00000010, 0xb1c41c03, 0x00000010, 0x91840a06, 0x00000000, 0x28840000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0xb1840a97, 0x0000000c, 0x21420006, + 0x00000010, 0x0ce7001d, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00, + 0x00000010, 0x91870856, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c54, + 0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00, + 0x00000000, 0x28840000, 0x00000000, 0x02048c00, 0x00000008, 0x22000008, + 0x00000000, 0x03840000, 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, + 0x00000002, 0x21421800, 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00, 0x00000000, 0x66f40000, + 0x0000000c, 0x29000000, 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, + 0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe2, 0x00000000, 0x39760000, + 0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000000, 0x031e0000, + 0x00000009, 0x076000ff, 0x00000010, 0x001f0000, 0x0000000f, 0x0f0e0007, + 0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000, + 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000, + 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, + 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, + 0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, 0x00000008, 0x22000006, 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, 0x00000000, 0x241b0000, 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, 0x00000002, 0x21421800, + 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, 0x00000000, 0x26900000, 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000018, 0x8000ffa6, 0x00000000, 0x031e0000, + 0x00000000, 0x83850800, 0x00000009, 0x076000ff, 0x00000010, 0x001f0000, + 0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000, + 0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, + 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, + 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, + 0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800, + 0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, 0x00000008, 0x22000007, 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, 0x00000000, 0x241b0000, 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, 0x00000002, 0x21421800, + 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, 0x00000000, 0x26900000, 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000018, 0x8000ff6a, 0x00000010, 0x0ce70005, + 0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x80000121, + 0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, + 0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, + 0x00000018, 0x8000fe59, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007, + 0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4b, + 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001, + 0x00000018, 0x80000105, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4, + 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800, + 0x00000010, 0x91de0000, 0x00000018, 0x8000fe3d, 0x0000000c, 0x29800001, + 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, + 0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, + 0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000, + 0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x8000006c, + 0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, 0x00000018, 0x800000e9, 0x00000008, 0x2c8000b8, + 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005, + 0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048, + 0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04, + 0x00000008, 0x2200000d, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000018, 0x8000fe14, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, + 0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000, + 0x0000000c, 0x73e7001c, 0x00000018, 0x80000043, 0x00000008, 0x02000004, + 0x00000010, 0x91c40802, 0x0000000c, 0x29800000, 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, + 0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfa, + 0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000, + 0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007, + 0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200, + 0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800, + 0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001, + 0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b, + 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, 0x00000000, 0x02180000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a, + 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804, + 0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008, + 0x00000010, 0x20530000, 0x00000018, 0x8000fdc5, 0x0000000c, 0x29800001, + 0x00000000, 0x2a000000, 0x00000018, 0x8000fdc2, 0x00000000, 0x06820000, + 0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000, + 0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224, + 0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000, + 0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000, + 0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019, + 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x29800000, + 0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000, + 0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000, + 0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f, + 0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000, + 0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00, + 0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00, + 0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000, + 0x00000010, 0xb1e9a056, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, + 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, 0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, + 0x0000000c, 0x09800002, 0x00000010, 0x009f0000, 0x00000010, 0xb8173209, + 0x00000000, 0x35140000, 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, + 0x00000000, 0x34970000, 0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, 0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, + 0x00000010, 0xb8f6a01a, 0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, + 0x00000000, 0x83973200, 0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, + 0x00000000, 0x37d00000, 0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, + 0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, + 0x00000000, 0x33190000, 0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, + 0x00000008, 0x22000009, 0x00000000, 0x07520000, 0x00000000, 0x29000000, + 0x0000000c, 0x73e70019, 0x0000000f, 0x65680010, 0x0000000c, 0x21420004, + 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x0000000c, 0x61420004, + 0x00000000, 0x290e0000, 0x00000018, 0x80000002, 0x00000010, 0x91973206, + 0x00000000, 0x35140000, 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, + 0x00000000, 0x34990000, 0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, + 0x00000010, 0xb1860013, 0x00000000, 0x28e90000, 0x00000008, 0x22000004, + 0x00000000, 0x23ec0000, 0x00000000, 0x03690000, 0x00000010, 0xb8660c07, + 0x00000009, 0x036cffff, 0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, + 0x00000005, 0x73e70c00, 0x00000000, 0x33690000, 0x00000005, 0x74680000, + 0x0000000c, 0x73e7001c, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, + 0x00000010, 0xb1d00c11, 0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, + 0x00000018, 0x8000000e, 0x00000010, 0x2e67000d, 0x00000000, 0x03690000, + 0x00000010, 0xb1f60c0b, 0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, + 0x00000008, 0x2200000c, 0x00000000, 0x07520000, 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, 0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, + 0x00000000, 0x22060000, 0x00000000, 0x290e0000, 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, 0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, + 0x00000000, 0x27f20000, 0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, + 0x00000009, 0x0361ffff, 0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, + 0x0000000f, 0x65680010, 0x00000000, 0x29000000, 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001b, 0x00000010, 0x20530000, 0x00000018, 0x000d0000 +}; + +static int bnx_TPAT_b06FwReleaseMajor = 0x1; +static int bnx_TPAT_b06FwReleaseMinor = 0x0; +static int bnx_TPAT_b06FwReleaseFix = 0x0; +static u_int32_t bnx_TPAT_b06FwStartAddr = 0x08000860; +static u_int32_t bnx_TPAT_b06FwTextAddr = 0x08000800; +static int bnx_TPAT_b06FwTextLen = 0x122c; +static u_int32_t bnx_TPAT_b06FwDataAddr = 0x08001a60; +static int bnx_TPAT_b06FwDataLen = 0x0; +static u_int32_t bnx_TPAT_b06FwRodataAddr = 0x00000000; +static int bnx_TPAT_b06FwRodataLen = 0x0; +static u_int32_t bnx_TPAT_b06FwBssAddr = 0x08001aa0; +static int bnx_TPAT_b06FwBssLen = 0x250; +static u_int32_t bnx_TPAT_b06FwSbssAddr = 0x08001a60; +static int bnx_TPAT_b06FwSbssLen = 0x34; +static u_int32_t bnx_TPAT_b06FwText[(0x122c/4) + 1] = { + 0x0a000218, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20322e36, + 0x2e320000, 0x02060201, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, + 0x24421a60, 0x3c030800, 0x24631cf0, 0xac400000, 0x0043202b, 0x1480fffd, + 0x24420004, 0x3c1d0800, 0x37bd2ffc, 0x03a0f021, 0x3c100800, 0x26100860, + 0x3c1c0800, 0x279c1a60, 0x0e000546, 0x00000000, 0x0000000d, 0x8f820010, + 0x8c450008, 0x24030800, 0xaf430178, 0x97430104, 0x3c020008, 0xaf420140, + 0x8f820024, 0x30420001, 0x10400007, 0x3069ffff, 0x24020002, 0x2523fffe, + 0xa7420146, 0xa7430148, 0x0a000242, 0x3c020800, 0xa7400146, 0x3c020800, + 0x8c43083c, 0x1460000e, 0x24020f00, 0x8f820024, 0x30430020, 0x0003182b, + 0x00031823, 0x30650009, 0x30420c00, 0x24030400, 0x14430002, 0x34a40001, + 0x34a40005, 0xa744014a, 0x0a000264, 0x3c020800, 0x8f830014, 0x14620008, + 0x00000000, 0x8f820024, 0x30420020, 0x0002102b, 0x00021023, 0x3042000d, + 0x0a000262, 0x34420005, 0x8f820024, 0x30420020, 0x0002102b, 0x00021023, + 0x30420009, 0x34420001, 0xa742014a, 0x3c020800, 0x8c430820, 0x8f840024, + 0x3c020048, 0x00621825, 0x30840006, 0x24020002, 0x1082000d, 0x2c820003, + 0x50400005, 0x24020004, 0x10800012, 0x3c020001, 0x0a000284, 0x00000000, + 0x10820007, 0x24020006, 0x1482000f, 0x3c020111, 0x0a00027c, 0x00621025, + 0x0a00027b, 0x3c020101, 0x3c020011, 0x00621025, 0x24030001, 0xaf421000, + 0xaf830020, 0x0a000284, 0x00000000, 0x00621025, 0xaf421000, 0xaf800020, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8f830020, 0x1060003f, + 0x3c048000, 0x8f421000, 0x00441024, 0x1040fffd, 0x00000000, 0x10600039, + 0x00000000, 0x8f421000, 0x3c030020, 0x00431024, 0x10400034, 0x00000000, + 0x97421014, 0x14400031, 0x00000000, 0x97421008, 0x8f840010, 0x24420006, + 0x00024082, 0x00081880, 0x00643821, 0x8ce50000, 0x30430003, 0x30420001, + 0x10400004, 0x00000000, 0x0000000d, 0x0a0002c3, 0x00081080, 0x5460000f, + 0x30a5ffff, 0x3c06ffff, 0x00a62824, 0x0005182b, 0x00a61026, 0x0002102b, + 0x00621824, 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x240001fb, + 0x8ce20000, 0x0a0002c2, 0x00462825, 0x0005182b, 0x38a2ffff, 0x0002102b, + 0x00621824, 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x24000205, + 0x8ce20000, 0x3445ffff, 0x00081080, 0x00441021, 0x3c030800, 0xac450000, + 0x8c620830, 0x24420001, 0xac620830, 0x8f840018, 0x01202821, 0x24820008, + 0x30421fff, 0x24434000, 0x0343d821, 0x30a30007, 0xaf84000c, 0xaf820018, + 0xaf420084, 0x10600002, 0x24a20007, 0x3045fff8, 0x8f820030, 0x8f840000, + 0x00451821, 0xaf82001c, 0x0064102b, 0xaf830030, 0x14400002, 0x00641023, + 0xaf820030, 0x8f840030, 0x34028000, 0x00821021, 0x03421821, 0x3c021000, + 0xaf830010, 0xaf440080, 0x03e00008, 0xaf420178, 0x8f830024, 0x27bdffe0, + 0xafbf0018, 0xafb10014, 0x30620200, 0x14400004, 0xafb00010, 0x0000000d, + 0x00000000, 0x24000242, 0x00031a82, 0x30630003, 0x000310c0, 0x00431021, + 0x00021080, 0x00431021, 0x00021080, 0x3c030800, 0x24631aa0, 0x00438821, + 0x8e240000, 0x10800004, 0x00000000, 0x0000000d, 0x00000000, 0x2400024d, + 0x8f850010, 0x24020001, 0xae220000, 0x8ca70008, 0xa2200007, 0x8f620004, + 0x26300014, 0x02002021, 0x00021402, 0xa2220004, 0x304600ff, 0x24c60005, + 0x0e000673, 0x00063082, 0x8f620004, 0xa6220008, 0x8f430108, 0x3c021000, + 0x00621824, 0x10600008, 0x00000000, 0x97420104, 0x92230007, 0x2442ffec, + 0x3045ffff, 0x34630002, 0x0a000321, 0xa2230007, 0x97420104, 0x2442fff0, + 0x3045ffff, 0x8f620004, 0x3042ffff, 0x2c420013, 0x54400005, 0x92230007, + 0x92220007, 0x34420001, 0xa2220007, 0x92230007, 0x24020001, 0x10620009, + 0x28620002, 0x14400014, 0x24020002, 0x10620012, 0x24020003, 0x1062000a, + 0x00000000, 0x0a000342, 0x00000000, 0x8f820010, 0x8c43000c, 0x3c04ffff, + 0x00641824, 0x00651825, 0x0a000342, 0xac43000c, 0x8f820010, 0x8c430010, + 0x3c04ffff, 0x00641824, 0x00651825, 0xac430010, 0x8f620004, 0x3042ffff, + 0x24420002, 0x00021083, 0xa2220005, 0x304500ff, 0x8f820010, 0x3c04ffff, + 0x00052880, 0x00a22821, 0x8ca70000, 0x96220008, 0x97430104, 0x00e42024, + 0x24420002, 0x00621823, 0x00833825, 0xaca70000, 0x92240005, 0x00041080, + 0x02021021, 0x90430000, 0x3c05fff6, 0x34a5ffff, 0x3063000f, 0x00832021, + 0xa2240006, 0x308200ff, 0x24420003, 0x00021080, 0x02021021, 0x8c460000, + 0x308300ff, 0x8f820010, 0x3c04ff7f, 0x00031880, 0x00c53824, 0x00621821, + 0xae26000c, 0xac67000c, 0x8e22000c, 0x92230006, 0x3484ffff, 0x00441024, + 0x24630003, 0x00031880, 0x02031821, 0x00e42024, 0xae22000c, 0xac640000, + 0x92220006, 0x24420004, 0x00021080, 0x02021021, 0x94470002, 0xac470000, + 0x92230006, 0x8f820010, 0x00031880, 0x00621821, 0x24020010, 0xac670010, + 0x24030002, 0xa7420140, 0xa7400142, 0xa7400144, 0xa7430146, 0x97420104, + 0x24030001, 0x2442fffe, 0xa7420148, 0xa743014a, 0x8f820024, 0x24030002, + 0x30440006, 0x1083000d, 0x2c820003, 0x10400005, 0x24020004, 0x10800011, + 0x3c020009, 0x0a0003a5, 0x00000000, 0x10820007, 0x24020006, 0x1482000d, + 0x3c020119, 0x0a00039f, 0x24030001, 0x0a00039e, 0x3c020109, 0x3c020019, + 0x24030001, 0xaf421000, 0xaf830020, 0x0a0003a5, 0x00000000, 0xaf421000, + 0xaf800020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x92220004, + 0x24030008, 0x8f840020, 0x24420002, 0x30420007, 0x00621823, 0x30630007, + 0x10800006, 0xae230010, 0x3c038000, 0x8f421000, 0x00431024, 0x1040fffd, + 0x00000000, 0x8f820018, 0xaf82000c, 0x24420010, 0x30421fff, 0xaf820018, + 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff, 0x30620007, + 0x10400002, 0x24620007, 0x3043fff8, 0x8f820030, 0x8f840000, 0x00431821, + 0xaf82001c, 0x0064102b, 0xaf830030, 0x14400002, 0x00641023, 0xaf820030, + 0x8f840030, 0x34028000, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x00821021, + 0x03421821, 0x3c021000, 0xaf830010, 0xaf440080, 0xaf420178, 0x03e00008, + 0x27bd0020, 0x8f830024, 0x27bdffe0, 0xafbf0018, 0xafb10014, 0x30620200, + 0x14400004, 0xafb00010, 0x0000000d, 0x00000000, 0x240002e9, 0x00031a82, + 0x30630003, 0x000310c0, 0x00431021, 0x00021080, 0x00431021, 0x00021080, + 0x3c030800, 0x24631aa0, 0x00438021, 0x8e040000, 0x14800004, 0x00000000, + 0x0000000d, 0x00000000, 0x240002ee, 0x8f620004, 0x04410008, 0x26050014, + 0x92020006, 0x8e03000c, 0x24420003, 0x00021080, 0x00a21021, 0xac430000, + 0xae000000, 0x92020005, 0x24420001, 0x00021080, 0x00a21021, 0x8c430000, + 0x3c040001, 0x00641821, 0xac430000, 0x92060004, 0x27710008, 0x02202021, + 0x24c60005, 0x0e000673, 0x00063082, 0x92040006, 0x3c057fff, 0x8f620004, + 0x00042080, 0x00912021, 0x8c830004, 0x34a5ffff, 0x00451024, 0x00621821, + 0xac830004, 0x92050005, 0x3c07ffff, 0x92040004, 0x00052880, 0x00b12821, + 0x8ca30000, 0x97420104, 0x96060008, 0x00671824, 0x00441021, 0x00461023, + 0x3042ffff, 0x00621825, 0xaca30000, 0x92030007, 0x24020001, 0x1062000a, + 0x28620002, 0x1440001d, 0x2402000a, 0x24020002, 0x10620019, 0x24020003, + 0x1062000e, 0x2402000a, 0x0a000447, 0x00000000, 0x92020004, 0x97430104, + 0x8e24000c, 0x00621821, 0x2463fff2, 0x3063ffff, 0x00872024, 0x00832025, + 0xae24000c, 0x0a000447, 0x2402000a, 0x92020004, 0x97430104, 0x8e240010, + 0x00621821, 0x2463ffee, 0x3063ffff, 0x00872024, 0x00832025, 0xae240010, + 0x2402000a, 0xa7420140, 0x96030012, 0x8f840024, 0xa7430142, 0x92020004, + 0xa7420144, 0xa7400146, 0x97430104, 0x30840006, 0x24020001, 0xa7430148, + 0xa742014a, 0x24020002, 0x1082000d, 0x2c820003, 0x10400005, 0x24020004, + 0x10800011, 0x3c020041, 0x0a00046c, 0x00000000, 0x10820007, 0x24020006, + 0x1482000d, 0x3c020151, 0x0a000466, 0x24030001, 0x0a000465, 0x3c020141, + 0x3c020051, 0x24030001, 0xaf421000, 0xaf830020, 0x0a00046c, 0x00000000, + 0xaf421000, 0xaf800020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x8f820020, 0x8f840018, 0x10400006, 0x92030004, 0x3c058000, 0x8f421000, + 0x00451024, 0x1040fffd, 0x00000000, 0x2463000a, 0x30620007, 0x10400002, + 0x24620007, 0x304303f8, 0x00831021, 0x30421fff, 0xaf84000c, 0xaf820018, + 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff, 0x30620007, + 0x10400002, 0x24620007, 0x3043fff8, 0x8f820030, 0x8f840000, 0x00431821, + 0xaf82001c, 0x0064102b, 0xaf830030, 0x14400002, 0x00641023, 0xaf820030, + 0x8f840030, 0x34028000, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x00821021, + 0x03421821, 0x3c021000, 0xaf830010, 0xaf440080, 0xaf420178, 0x03e00008, + 0x27bd0020, 0x8f620000, 0x97430104, 0x3c048000, 0x3045ffff, 0x3066ffff, + 0x8f420178, 0x00441024, 0x1440fffd, 0x2402000a, 0x30a30007, 0xa7420140, + 0x24020008, 0x00431023, 0x30420007, 0x24a3fffe, 0xa7420142, 0xa7430144, + 0xa7400146, 0xa7460148, 0x8f420108, 0x8f830024, 0x30420020, 0x0002102b, + 0x00021023, 0x30420009, 0x34420001, 0x30630006, 0xa742014a, 0x24020002, + 0x1062000d, 0x2c620003, 0x10400005, 0x24020004, 0x10600011, 0x3c020041, + 0x0a0004d6, 0x00000000, 0x10620007, 0x24020006, 0x1462000d, 0x3c020151, + 0x0a0004d0, 0x24030001, 0x0a0004cf, 0x3c020141, 0x3c020051, 0x24030001, + 0xaf421000, 0xaf830020, 0x0a0004d6, 0x00000000, 0xaf421000, 0xaf800020, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8f820020, 0x24a30008, + 0x8f850018, 0x10400006, 0x30c6ffff, 0x3c048000, 0x8f421000, 0x00441024, + 0x1040fffd, 0x00000000, 0x3063ffff, 0x30620007, 0x10400002, 0x24620007, + 0x3043fff8, 0x00a31021, 0x30421fff, 0x24434000, 0x0343d821, 0x00c02021, + 0x30830007, 0xaf85000c, 0xaf820018, 0xaf420084, 0x10600002, 0x24820007, + 0x3044fff8, 0x8f820030, 0x8f850000, 0x00441821, 0xaf82001c, 0x0065102b, + 0xaf830030, 0x14400002, 0x00651023, 0xaf820030, 0x8f840030, 0x34028000, + 0x3c030800, 0x8c650834, 0x00821021, 0x03421821, 0xaf830010, 0xaf440080, + 0x10a00006, 0x2402000e, 0x9383002f, 0x14620004, 0x3c021000, 0x2402043f, + 0xa7420148, 0x3c021000, 0x03e00008, 0xaf420178, 0x8f820024, 0x30424000, + 0x10400005, 0x24020800, 0x0000000d, 0x00000000, 0x24000413, 0x24020800, + 0xaf420178, 0x97440104, 0x3c030008, 0xaf430140, 0x8f820024, 0x30420001, + 0x10400006, 0x3085ffff, 0x24020002, 0x24a3fffe, 0xa7420146, 0x0a000526, + 0xa7430148, 0xa7400146, 0x8f840018, 0x2402000d, 0xa742014a, 0x24830008, + 0x30631fff, 0x24624000, 0x0342d821, 0x30a20007, 0xaf84000c, 0xaf830018, + 0xaf430084, 0x10400002, 0x24a20007, 0x3045fff8, 0x8f820030, 0x8f840000, + 0x00451821, 0xaf82001c, 0x0064102b, 0xaf830030, 0x14400002, 0x00641023, + 0xaf820030, 0x8f840030, 0x34028000, 0x00821021, 0x03421821, 0x3c021000, + 0xaf830010, 0xaf440080, 0x03e00008, 0xaf420178, 0x27bdffe8, 0x3c046008, + 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f, 0x375b4000, + 0x00431024, 0x3442380c, 0xac825000, 0x8f430008, 0x3c100800, 0x37428000, + 0x34630001, 0xaf430008, 0xaf820010, 0x3c02601c, 0xaf800018, 0xaf400080, + 0xaf400084, 0x8c450008, 0x3c036000, 0x8c620808, 0x3c040800, 0x3c030080, + 0xac830820, 0x3042fff0, 0x38420010, 0x2c420001, 0xaf850000, 0xaf820004, + 0x0e000658, 0x00000000, 0x8f420000, 0x30420001, 0x1040fffb, 0x00000000, + 0x8f430108, 0x8f440100, 0x30622000, 0xaf830024, 0xaf840014, 0x10400004, + 0x8e02082c, 0x24420001, 0x0a0005c6, 0xae02082c, 0x30620200, 0x14400003, + 0x24020f00, 0x14820027, 0x24020d00, 0x97420104, 0x1040001c, 0x30624000, + 0x14400005, 0x00000000, 0x0e00022f, 0x00000000, 0x0a0005bb, 0x00000000, + 0x8f620008, 0x8f630000, 0x24020030, 0x00031e02, 0x306300f0, 0x10620007, + 0x28620031, 0x1440002f, 0x24020040, 0x10620007, 0x00000000, 0x0a0005bb, + 0x00000000, 0x0e0002e8, 0x00000000, 0x0a0005bb, 0x00000000, 0x0e0003db, + 0x00000000, 0x0a0005bb, 0x00000000, 0x30620040, 0x1440002b, 0x00000000, + 0x0000000d, 0x00000000, 0x240004b7, 0x0a0005c6, 0x00000000, 0x1482000f, + 0x30620006, 0x97420104, 0x10400005, 0x30620040, 0x0e000510, 0x00000000, + 0x0a0005bb, 0x00000000, 0x1440001b, 0x00000000, 0x0000000d, 0x00000000, + 0x240004c9, 0x0a0005c6, 0x00000000, 0x1040000e, 0x30621000, 0x10400005, + 0x00000000, 0x0e000688, 0x00000000, 0x0a0005bb, 0x00000000, 0x0e0004a1, + 0x00000000, 0x8f82002c, 0x24420001, 0xaf82002c, 0x0a0005c6, 0x00000000, + 0x30620040, 0x14400004, 0x00000000, 0x0000000d, 0x00000000, 0x240004e0, + 0x8f420138, 0x3c034000, 0x00431025, 0xaf420138, 0x0a000566, 0x00000000, + 0x3c046008, 0x8c835000, 0x3c1a8000, 0x2402ff7f, 0x375b4000, 0x00621824, + 0x3463380c, 0xac835000, 0x8f420008, 0x3c056000, 0x3c03601c, 0x34420001, + 0xaf420008, 0x37428000, 0xaf800018, 0xaf820010, 0xaf400080, 0xaf400084, + 0x8c660008, 0x8ca20808, 0x3c040800, 0x3c030080, 0xac830820, 0x3042fff0, + 0x38420010, 0x2c420001, 0xaf860000, 0xaf820004, 0x03e00008, 0x00000000, + 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, 0x3044fff8, 0x8f820018, + 0x00441821, 0x30631fff, 0x24644000, 0x0344d821, 0xaf82000c, 0xaf830018, + 0x03e00008, 0xaf430084, 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, + 0x3044fff8, 0x8f820030, 0x8f830000, 0x00442021, 0xaf82001c, 0x0083102b, + 0xaf840030, 0x14400002, 0x00831023, 0xaf820030, 0x8f820030, 0x34038000, + 0x00431821, 0x03432021, 0xaf840010, 0x03e00008, 0xaf420080, 0x8f830024, + 0x24020002, 0x30630006, 0x1062000d, 0x2c620003, 0x50400005, 0x24020004, + 0x10600012, 0x3c020001, 0x0a00062a, 0x00000000, 0x10620007, 0x24020006, + 0x1462000f, 0x3c020111, 0x0a000622, 0x00821025, 0x0a000621, 0x3c020101, + 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830020, 0x0a00062a, + 0x00000000, 0x00821025, 0xaf421000, 0xaf800020, 0x00000000, 0x00000000, + 0x00000000, 0x03e00008, 0x00000000, 0x8f820020, 0x10400005, 0x3c038000, + 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x03e00008, 0x00000000, + 0x8f820024, 0x27bdffe8, 0x30424000, 0x14400005, 0xafbf0010, 0x0e00022f, + 0x00000000, 0x0a000656, 0x8fbf0010, 0x8f620008, 0x8f630000, 0x24020030, + 0x00031e02, 0x306300f0, 0x10620008, 0x28620031, 0x1440000d, 0x8fbf0010, + 0x24020040, 0x10620007, 0x00000000, 0x0a000656, 0x00000000, 0x0e0002e8, + 0x00000000, 0x0a000656, 0x8fbf0010, 0x0e0003db, 0x00000000, 0x8fbf0010, + 0x03e00008, 0x27bd0018, 0x8f840028, 0x1080000f, 0x3c026000, 0x8c430c3c, + 0x30630fff, 0xaf830008, 0x14600011, 0x3082000f, 0x10400005, 0x308200f0, + 0x10400003, 0x30820f00, 0x14400006, 0x00000000, 0x0000000d, 0x00000000, + 0x2400051f, 0x03e00008, 0x00000000, 0x0000000d, 0x00000000, 0x24000524, + 0x03e00008, 0x00000000, 0xaf830028, 0x03e00008, 0x00000000, 0x10c00007, + 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb, + 0x24840004, 0x03e00008, 0x00000000, 0x0a000684, 0x00a01021, 0xac860000, + 0x00000000, 0x00000000, 0x24840004, 0x00a01021, 0x1440fffa, 0x24a5ffff, + 0x03e00008, 0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x00000000}; + +static u_int32_t bnx_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 }; +static u_int32_t bnx_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 }; + +static int bnx_TXP_b06FwReleaseMajor = 0x1; +static int bnx_TXP_b06FwReleaseMinor = 0x0; +static int bnx_TXP_b06FwReleaseFix = 0x0; +static u_int32_t bnx_TXP_b06FwStartAddr = 0x080034b0; +static u_int32_t bnx_TXP_b06FwTextAddr = 0x08000000; +static int bnx_TXP_b06FwTextLen = 0x5748; +static u_int32_t bnx_TXP_b06FwDataAddr = 0x08005760; +static int bnx_TXP_b06FwDataLen = 0x0; +static u_int32_t bnx_TXP_b06FwRodataAddr = 0x00000000; +static int bnx_TXP_b06FwRodataLen = 0x0; +static u_int32_t bnx_TXP_b06FwBssAddr = 0x080057a0; +static int bnx_TXP_b06FwBssLen = 0x1c4; +static u_int32_t bnx_TXP_b06FwSbssAddr = 0x08005760; +static int bnx_TXP_b06FwSbssLen = 0x38; +static u_int32_t bnx_TXP_b06FwText[(0x5748/4) + 1] = { + 0x0a000d2c, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x322e352e, + 0x38000000, 0x02050800, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 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0x8f830000, 0x90620005, 0x34420008, 0xa0620005, + 0x8f840000, 0x8c820074, 0x3c038000, 0x00431025, 0xac820074, 0x90830000, + 0x24020020, 0x10620004, 0x00000000, 0x0000000d, 0x00000000, 0x2400040b, + 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, 0x9084007b, + 0x9342010a, 0x14820028, 0x3c030800, 0x00003821, 0x24052000, 0x3c090800, + 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec258b0, 0x26c458b0, + 0x2484ffd0, 0xaf420144, 0x8c820034, 0x3c030100, 0xaf420148, 0x24020046, + 0xaf43014c, 0xa3420152, 0x8d230030, 0x3c021000, 0xa7470158, 0xaf450154, + 0xaf420178, 0x8c860034, 0x24630001, 0xad230030, 0x9342010a, 0x3c030046, + 0xafa50014, 0x00021600, 0x00431025, 0x00471025, 0xafa20010, 0x9343010b, + 0xafa30018, 0x8f440100, 0x8f450104, 0x0e00159b, 0x3c070100, 0x3c030800, + 0x24625880, 0x0a001250, 0x8c430020, 0x93420108, 0x30420010, 0x50400056, + 0x9343093f, 0x8f860000, 0x90c2007f, 0x8cc30178, 0x304800ff, 0x15030004, + 0x00000000, 0x0000000d, 0x00000000, 0x24000425, 0x90c2007e, 0x90c40080, + 0x00081c00, 0x00021600, 0x00431025, 0x00042200, 0x90c3007a, 0x90c5000a, + 0x00441025, 0x11050028, 0x00623825, 0xa0c8000a, 0x00004021, 0x24056000, + 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec258b0, + 0x26c458b0, 0x2484ffd0, 0xaf420144, 0x8c820034, 0xaf420148, 0x24020052, + 0xaf47014c, 0xa3420152, 0x8d230030, 0x3c021000, 0xa7480158, 0xaf450154, + 0xaf420178, 0x8c860034, 0x24630001, 0xad230030, 0x9342010a, 0x3c030052, + 0xafa50014, 0x00021600, 0x00431025, 0x00481025, 0xafa20010, 0x9343010b, + 0xafa30018, 0x8f440100, 0x0e00159b, 0x8f450104, 0x0a00124a, 0x00000000, + 0x3c026000, 0x24030100, 0xac43081c, 0x3c030001, 0xac43081c, 0x0000000d, + 0x00000000, 0x2400043e, 0x16800009, 0x3c050800, 0x3c040800, 0x24825880, + 0x8c430020, 0x32530040, 0x2404ffbf, 0x00641824, 0x0a001493, 0xac430020, + 0x8ca25880, 0x10400005, 0x3c030800, 0x8c620034, 0xaca05880, 0x24420001, + 0xac620034, 0x9343093f, 0x24020012, 0x5462000e, 0x97420908, 0x32820038, + 0x14400009, 0x3c030800, 0x8f830000, 0x8c62004c, 0xac62005c, 0x3c020800, + 0x24445880, 0x8c820020, 0x0a001285, 0x32530040, 0xac605880, 0x97420908, + 0x5440001c, 0x97420908, 0x3c039000, 0x34630001, 0x8f820008, 0x32530040, + 0x3c048000, 0x00431025, 0xaf420020, 0x8f420020, 0x00441024, 0x1440fffd, + 0x3c028000, 0x8f840000, 0x8f850008, 0x8c830050, 0x34420001, 0x00a22825, + 0xaf830020, 0xac830070, 0xac83005c, 0xaf450020, 0x3c050800, 0x24a45880, + 0x8c820020, 0x2403ffbf, 0x00431024, 0x0a001493, 0xac820020, 0x000211c0, + 0xaf420024, 0x97420908, 0x3c030080, 0x34630003, 0x000211c0, 0xaf42080c, + 0xaf43081c, 0x974209ec, 0x8f4309a4, 0xa782002c, 0x3c020800, 0x24445880, + 0xac83002c, 0x93420937, 0x93430934, 0x00021080, 0x00621821, 0xa4830018, + 0x934209d8, 0x32850038, 0xafa50028, 0x00621821, 0xa483001a, 0x934209d8, + 0x93430934, 0x3c1e0800, 0x00809821, 0x00431021, 0x24420010, 0xa4820016, + 0x24020006, 0xae620020, 0x8fa20028, 0x10400003, 0x0000a821, 0x0a0012f0, + 0x24120008, 0x8f420958, 0x8f830020, 0x8f840030, 0x00431023, 0x00832023, + 0x04800003, 0xae620004, 0x04410003, 0x0082102b, 0x0a0012bc, 0xae600004, + 0x54400001, 0xae640004, 0x8ee20000, 0x0040f809, 0x00000000, 0x00409021, + 0x32420001, 0x5440001e, 0x8ee20004, 0x8e630008, 0x1060002b, 0x3c02c000, + 0x00621025, 0xaf420e00, 0x8f420000, 0x30420008, 0x1040fffd, 0x00000000, + 0x97420e08, 0xa7820010, 0x8f430e04, 0x8e620008, 0xaf830004, 0x8f840004, + 0x0044102b, 0x1040000b, 0x24150001, 0x24020100, 0x3c016000, 0xac22081c, + 0x3c020001, 0x3c016000, 0xac22081c, 0x0000000d, 0x00000000, 0x240004cd, + 0x24150001, 0x8ee20004, 0x0040f809, 0x00000000, 0x02429025, 0x32420002, + 0x5040001d, 0x8f470940, 0x12a00006, 0x8ec258b0, 0x8f830000, 0xac6200a8, + 0x8f840000, 0x8e620034, 0xac8200ac, 0x32420004, 0x50400013, 0x8f470940, + 0x3c020800, 0x3283007d, 0x10600110, 0x24575920, 0x32820001, 0x50400006, + 0x36520002, 0x8f830034, 0x8f420940, 0x10620109, 0x00000000, 0x36520002, + 0x24020008, 0xa6600010, 0xa6620012, 0xae600008, 0xa2600024, 0x8f470940, + 0x3c030800, 0x24685880, 0x8d02002c, 0x8d050008, 0x95040010, 0x9506000a, + 0x95030026, 0x00451021, 0x00862021, 0x00641821, 0xaf870034, 0xad02002c, + 0x32820030, 0x10400008, 0xa5030014, 0x91020024, 0x32910040, 0x34420004, + 0xa1020024, 0xaf400048, 0x0a001345, 0x3c040800, 0x93420923, 0x30420002, + 0x10400029, 0x32910040, 0x8f830000, 0x8f840020, 0x8c620084, 0x00441023, + 0x0442000a, 0x3c039000, 0x95020014, 0x8c630084, 0x00821021, 0x00621823, + 0x1c600004, 0x3c039000, 0x91020024, 0x34420001, 0xa1020024, 0x34630001, + 0x8f820008, 0x32910040, 0x3c048000, 0x00431025, 0xaf420020, 0x8f420020, + 0x00441024, 0x1440fffd, 0x00000000, 0x8f840000, 0x9083003f, 0x2402000a, + 0x10620005, 0x2402000c, 0x9083003f, 0x24020008, 0x14620002, 0x24020014, + 0xa082003f, 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, + 0x3c040800, 0x24865880, 0x94c20010, 0x94c3001a, 0x8cc40008, 0x00432821, + 0x14800006, 0xa4c5001c, 0x3c020800, 0x8c430048, 0x10600002, 0x24a20040, + 0xa4c2001c, 0x27d05880, 0x9604001c, 0x96020012, 0x00822021, 0x24840002, + 0x0e000faf, 0x3084ffff, 0x8f850018, 0x00a01821, 0xa2030025, 0x8ee60008, + 0x00402021, 0x24a50001, 0xaf850018, 0x00c0f809, 0x00000000, 0x00402021, + 0x0e001026, 0x02202821, 0x8ee3000c, 0x0060f809, 0x00402021, 0x9604001c, + 0x96020012, 0x00822021, 0x24840002, 0x0e000fc5, 0x3084ffff, 0x8fc25880, + 0x8e030008, 0x00431023, 0x14400012, 0xafc25880, 0x54600006, 0x8e020020, + 0x3243004a, 0x24020002, 0x14620005, 0x00000000, 0x8e020020, 0x34420040, + 0x0a001382, 0xae020020, 0x52a00006, 0x36520002, 0x8e020030, 0xaf420e10, + 0x8e030034, 0xaf430e18, 0x36520002, 0x52a00008, 0x96670014, 0x8f830000, + 0x8f420e10, 0xac6200a8, 0x8f840000, 0x8f420e18, 0xac8200ac, 0x96670014, + 0x92680024, 0x24020040, 0xaf420814, 0x8f830020, 0x8f82001c, 0x00671821, + 0x00621023, 0xaf830020, 0x18400008, 0x00000000, 0x8f820000, 0xaf83001c, + 0xac430054, 0x54e00005, 0xaf400040, 0x0a0013a0, 0x8f42095c, 0x54e00001, + 0xaf400044, 0x8f42095c, 0x31030008, 0xaf820030, 0x1060001a, 0x00000000, + 0x8f840000, 0x90820120, 0x90830121, 0x304600ff, 0x00c31823, 0x30630007, + 0x24020007, 0x1062000e, 0x00000000, 0x90820122, 0x304200fe, 0xa0820122, + 0x8f850000, 0x00061880, 0x8f840020, 0x24a20100, 0x00431021, 0x24c30001, + 0x30630007, 0xac440000, 0x0a0013bd, 0xa0a30120, 0x90820122, 0x34420001, + 0xa0820122, 0x14e00003, 0x31020001, 0x10400031, 0x32510002, 0x8f820000, + 0x8c43000c, 0x30630001, 0x1060002c, 0x32510002, 0x3c029000, 0x8f830008, + 0x34420001, 0x3c048000, 0x00621825, 0xaf430020, 0x8f420020, 0x00441024, + 0x1440fffd, 0x00000000, 0x8f870000, 0x8ce2000c, 0x30420001, 0x10400018, + 0x00000000, 0x94e2006a, 0x00022880, 0x50a00001, 0x24050001, 0x94e30068, + 0x90e40081, 0x3c020800, 0x8c460024, 0x00652821, 0x00852804, 0x00c5102b, + 0x54400001, 0x00a03021, 0x3c020800, 0x8c440028, 0x00c4182b, 0x54600001, + 0x00c02021, 0x8f430074, 0x2402fffe, 0x00822824, 0x00a31821, 0xace3000c, + 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, 0x8f820020, + 0x3c050800, 0x24b05880, 0xae020028, 0x8ee30010, 0x0060f809, 0x00000000, + 0x8f820028, 0x24420001, 0xaf820028, 0x12a00005, 0xaf40004c, 0x8f420e10, + 0xae020030, 0x8f430e18, 0xae030034, 0x1220fea7, 0x24020006, 0x8f870024, + 0x9786002c, 0x8f830000, 0x8f820034, 0x8f840020, 0x8f85001c, 0x32530040, + 0xa4e6002c, 0xac620044, 0x32420008, 0xac640050, 0xac650054, 0x1040007a, + 0x32820020, 0x10400027, 0x32910010, 0x00003821, 0x24052000, 0x3c090800, + 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec258b0, 0x26c458b0, + 0x2484ffd0, 0xaf420144, 0x8c820034, 0x3c030400, 0xaf420148, 0x24020041, + 0xaf43014c, 0xa3420152, 0x8d230030, 0x3c021000, 0xa7470158, 0xaf450154, + 0xaf420178, 0x8c860034, 0x24630001, 0xad230030, 0x9342010a, 0x3c030041, + 0xafa50014, 0x00021600, 0x00431025, 0x00471025, 0xafa20010, 0x9343010b, + 0xafa30018, 0x8f440100, 0x8f450104, 0x0e00159b, 0x3c070400, 0x12200028, + 0x00003821, 0x24052000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, + 0x1440fffd, 0x8ec258b0, 0x26c458b0, 0x2484ffd0, 0xaf420144, 0x8c820034, + 0x3c030300, 0xaf420148, 0x2402004e, 0xaf43014c, 0xa3420152, 0x8d230030, + 0x3c021000, 0xa7470158, 0xaf450154, 0xaf420178, 0x8c860034, 0x24630001, + 0xad230030, 0x9342010a, 0x3c03004e, 0xafa50014, 0x00021600, 0x00431025, + 0x00471025, 0xafa20010, 0x9343010b, 0xafa30018, 0x8f440100, 0x8f450104, + 0x0e00159b, 0x3c070300, 0x0a00148b, 0x8fa20024, 0x32820008, 0x10400026, + 0x24052000, 0x00003821, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, + 0x1440fffd, 0x8ec258b0, 0x26c458b0, 0x2484ffd0, 0xaf420144, 0x8c820034, + 0x3c030200, 0xaf420148, 0x2402004b, 0xaf43014c, 0xa3420152, 0x8d230030, + 0x3c021000, 0xa7470158, 0xaf450154, 0xaf420178, 0x8c860034, 0x24630001, + 0xad230030, 0x9342010a, 0x3c03004b, 0xafa50014, 0x00021600, 0x00431025, + 0x00471025, 0xafa20010, 0x9343010b, 0xafa30018, 0x8f440100, 0x8f450104, + 0x0e00159b, 0x3c070200, 0x8fa20024, 0x14400004, 0x8fa30020, 0x32420010, + 0x10400004, 0x00000000, 0x8c620004, 0x0040f809, 0x00000000, 0x12600006, + 0x8fa40020, 0x8c820008, 0x0040f809, 0x00000000, 0x0a0014c1, 0x8fbf0054, + 0x3c030800, 0x8c6258a0, 0x30420040, 0x14400023, 0x8fbf0054, 0x00002821, + 0x24040040, 0x8f870020, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, + 0x8ec258b0, 0x26c358b0, 0x2463ffd0, 0xaf420144, 0x8c620034, 0xaf420148, + 0x24020049, 0xaf47014c, 0xa3420152, 0x3c021000, 0xa7450158, 0xaf440154, + 0xaf420178, 0x8c660034, 0x9342010a, 0x3c030049, 0xafa40014, 0x00021600, + 0x00431025, 0x00451025, 0xafa20010, 0x9343010b, 0xafa30018, 0x8f440100, + 0x0e00159b, 0x8f450104, 0x8fbf0054, 0x8fbe0050, 0x8fb7004c, 0x8fb60048, + 0x8fb50044, 0x8fb40040, 0x8fb3003c, 0x8fb20038, 0x8fb10034, 0x8fb00030, + 0x03e00008, 0x27bd0058, 0x03e00008, 0x00001021, 0x3c020800, 0x24435880, + 0x8c650004, 0x8c445880, 0x0085182b, 0x10600002, 0x00403021, 0x00802821, + 0x9744093c, 0x00a4102b, 0x54400001, 0x00a02021, 0x93420923, 0x0004182b, + 0x00021042, 0x30420001, 0x00431024, 0x1040000d, 0x24c25880, 0x8f850000, + 0x8f830020, 0x8ca20084, 0x00431023, 0x04420007, 0x24c25880, 0x8ca20084, + 0x00641821, 0x00431023, 0x28420001, 0x00822023, 0x24c25880, 0xac440008, + 0xa4400026, 0x03e00008, 0x00001021, 0x8f850004, 0x97840010, 0x3c030800, + 0x24635880, 0x24020008, 0xa4620012, 0x8f820004, 0xa4600010, 0x000420c2, + 0x30840008, 0x2c420001, 0x00021023, 0x30420006, 0xac650008, 0x03e00008, + 0xa0640024, 0x3c020800, 0x24425880, 0x90450025, 0x9443001c, 0x3c021100, + 0xac800004, 0x00052c00, 0x24630002, 0x00621825, 0x00a32825, 0x24820008, + 0x03e00008, 0xac850000, 0x27bdffd8, 0x3c020800, 0x24425880, 0xafbf0020, + 0x90480025, 0x8c440008, 0x8c460020, 0x8f870020, 0x3c030800, 0x3c058000, + 0x8f420178, 0x00451024, 0x1440fffd, 0x8c6258b0, 0x246358b0, 0x2469ffd0, + 0xaf420144, 0x8d220034, 0x30c32000, 0xaf420148, 0x3c021000, 0xaf47014c, + 0xa3480152, 0xa7440158, 0xaf460154, 0xaf420178, 0x10600004, 0x3c030800, + 0x8c620030, 0x24420001, 0xac620030, 0x9342010a, 0x00081c00, 0x3084ffff, + 0xafa60014, 0x00021600, 0x00431025, 0x00441025, 0xafa20010, 0x9343010b, + 0xafa30018, 0x8f440100, 0x8f450104, 0x0e00159b, 0x8d260034, 0x8fbf0020, + 0x03e00008, 0x27bd0028, 0x0000000d, 0x00000000, 0x2400019d, 0x03e00008, + 0x00000000, 0x0000000d, 0x00000000, 0x240001a9, 0x03e00008, 0x00000000, + 0x03e00008, 0x00000000, 0x3c020800, 0x24425880, 0xac400008, 0xa4400026, + 0x03e00008, 0x24020001, 0x3c020800, 0x24425880, 0x24030008, 0xac400008, + 0xa4400010, 0xa4430012, 0xa0400024, 0x03e00008, 0x24020004, 0x03e00008, + 0x00001021, 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, + 0xac820000, 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a00156c, + 0x00a01021, 0xac860000, 0x00000000, 0x00000000, 0x24840004, 0x00a01021, + 0x1440fffa, 0x24a5ffff, 0x03e00008, 0x00000000, 0x3c0a0800, 0x8d490068, + 0x3c050800, 0x24a52098, 0x00093140, 0x00c51021, 0xac440000, 0x8f440e04, + 0x00a61021, 0xac440004, 0x97430e08, 0x97420e0c, 0x00a62021, 0x00031c00, + 0x00431025, 0xac820008, 0x8f430e10, 0x00801021, 0xac43000c, 0x8f440e14, + 0xac440010, 0x8f430e18, 0x3c0800ff, 0xac430014, 0x8f470e1c, 0x3508ffff, + 0x25290001, 0xac470018, 0x3c070800, 0x8ce3006c, 0x9344010a, 0x3c026000, + 0x24630001, 0xace3006c, 0x8c434448, 0x3129007f, 0x00a62821, 0xad490068, + 0x00042600, 0x00681824, 0x00832025, 0x03e00008, 0xaca4001c, 0x8fac0010, + 0x8fad0014, 0x8fae0018, 0x3c0b0800, 0x8d6a0060, 0x3c080800, 0x25080080, + 0x000a4940, 0x01281021, 0x01091821, 0xac440000, 0x00601021, 0xac650004, + 0xac460008, 0xac67000c, 0xac4c0010, 0xac6d0014, 0x3c036000, 0xac4e0018, + 0x8c654448, 0x3c040800, 0x8c820064, 0x254a0001, 0x314a00ff, 0x01094021, + 0xad6a0060, 0x24420001, 0xac820064, 0x03e00008, 0xad05001c, 0x3c030800, + 0x3c090800, 0x8d250070, 0x246330b0, 0x8f460100, 0x00053900, 0x00e31021, + 0xac460000, 0x8f440104, 0x00671021, 0xac440004, 0x8f460108, 0x8f840014, + 0x24a50001, 0xac460008, 0x8c880074, 0x3c060800, 0x8cc20074, 0x30a5003f, + 0x00671821, 0xad250070, 0x24420001, 0xacc20074, 0x03e00008, 0xac68000c, + 0x00000000 }; + +static u_int32_t bnx_TXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +static u_int32_t bnx_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 }; +static u_int32_t bnx_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 }; diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index ce41d0439bdf..cc7cc8bae512 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $NetBSD: files.pci,v 1.274 2006/12/17 22:57:16 bouyer Exp $ +# $NetBSD: files.pci,v 1.275 2006/12/17 23:02:06 bouyer Exp $ # # Config file and device description for machine-independent PCI code. # Included by ports that need it. Requires that the SCSI files be @@ -611,6 +611,11 @@ device bge: ether, ifnet, arp, mii, mii_bitbang attach bge at pci file dev/pci/if_bge.c bge +# Broadcom NetXtreme II +device bnx: ether, ifnet, arp, mii +attach bnx at pci +file dev/pci/if_bnx.c bnx + # Realtek 8129/8139 Ethernet controllers attach rtk at pci with rtk_pci file dev/pci/if_rtk_pci.c rtk_pci diff --git a/sys/dev/pci/if_bnx.c b/sys/dev/pci/if_bnx.c new file mode 100644 index 000000000000..3c0dc55e6608 --- /dev/null +++ b/sys/dev/pci/if_bnx.c @@ -0,0 +1,5735 @@ +/* $NetBSD: if_bnx.c,v 1.1 2006/12/17 23:02:06 bouyer Exp $ */ +/* $OpenBSD: if_bnx.c,v 1.21 2006/08/21 03:32:11 brad Exp $ */ + +/*- + * Copyright (c) 2006 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#if 0 +__FBSDID("$FreeBSD: src/sys/dev/bce/if_bce.c,v 1.3 2006/04/13 14:12:26 ru Exp $"); +#endif +__KERNEL_RCSID(0, "$NetBSD: if_bnx.c,v 1.1 2006/12/17 23:02:06 bouyer Exp $"); + +/* + * The following controllers are supported by this driver: + * BCM5706C A2, A3 + * BCM5708C B1 + * + * The following controllers are not supported by this driver: + * (These are not "Production" versions of the controller.) + * + * BCM5706C A0, A1 + * BCM5706S A0, A1, A2, A3 + * BCM5708C A0, B0 + * BCM5708S A0, B0, B1 + */ + +#include + +#include +#include + +/****************************************************************************/ +/* BNX Driver Version */ +/****************************************************************************/ +const char bnx_driver_version[] = "v0.9.6"; + +/****************************************************************************/ +/* BNX Debug Options */ +/****************************************************************************/ +#ifdef BNX_DEBUG + u_int32_t bnx_debug = /*BNX_WARN*/ BNX_VERBOSE_SEND; + + /* 0 = Never */ + /* 1 = 1 in 2,147,483,648 */ + /* 256 = 1 in 8,388,608 */ + /* 2048 = 1 in 1,048,576 */ + /* 65536 = 1 in 32,768 */ + /* 1048576 = 1 in 2,048 */ + /* 268435456 = 1 in 8 */ + /* 536870912 = 1 in 4 */ + /* 1073741824 = 1 in 2 */ + + /* Controls how often the l2_fhdr frame error check will fail. */ + int bnx_debug_l2fhdr_status_check = 0; + + /* Controls how often the unexpected attention check will fail. */ + int bnx_debug_unexpected_attention = 0; + + /* Controls how often to simulate an mbuf allocation failure. */ + int bnx_debug_mbuf_allocation_failure = 0; + + /* Controls how often to simulate a DMA mapping failure. */ + int bnx_debug_dma_map_addr_failure = 0; + + /* Controls how often to simulate a bootcode failure. */ + int bnx_debug_bootcode_running_failure = 0; +#endif + +/****************************************************************************/ +/* PCI Device ID Table */ +/* */ +/* Used by bnx_probe() to identify the devices supported by this driver. */ +/****************************************************************************/ +static const struct bnx_product { + pci_vendor_id_t bp_vendor; + pci_product_id_t bp_product; + pci_vendor_id_t bp_subvendor; + pci_product_id_t bp_subproduct; + const char *bp_name; +} bnx_devices[] = { +#ifdef PCI_SUBPRODUCT_HP_NC370T + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, + PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370T, + "HP NC370T Multifunction Gigabit Server Adapter" + }, +#endif +#ifdef PCI_SUBPRODUCT_HP_NC370i + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, + PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370i, + "HP NC370i Multifunction Gigabit Server Adapter" + }, +#endif + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706, + 0, 0, + "Broadcom NetXtreme II BCM5706 1000Base-T" + }, +#ifdef PCI_SUBPRODUCT_HP_NC370F + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, + PCI_VENDOR_HP, PCI_SUBPRODUCT_HP_NC370F, + "HP NC370F Multifunction Gigabit Server Adapter" + }, +#endif + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5706S, + 0, 0, + "Broadcom NetXtreme II BCM5706 1000Base-SX" + }, + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708, + 0, 0, + "Broadcom NetXtreme II BCM5708 1000Base-T" + }, + { + PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5708S, + 0, 0, + "Broadcom NetXtreme II BCM5708 1000Base-SX" + }, +}; + +/****************************************************************************/ +/* Supported Flash NVRAM device data. */ +/****************************************************************************/ +static struct flash_spec flash_table[] = +{ + /* Slow EEPROM */ + {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - slow"}, + /* Expansion entry 0001 */ + {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0001"}, + /* Saifun SA25F010 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, + "Non-buffered flash (128kB)"}, + /* Saifun SA25F020 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, + "Non-buffered flash (256kB)"}, + /* Expansion entry 0100 */ + {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0100"}, + /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, + "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, + /* Entry 0110: ST M45PE20 (non-buffered flash)*/ + {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, + "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, + /* Saifun SA25F005 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, + "Non-buffered flash (64kB)"}, + /* Fast EEPROM */ + {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - fast"}, + /* Expansion entry 1001 */ + {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1001"}, + /* Expansion entry 1010 */ + {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1010"}, + /* ATMEL AT45DB011B (buffered flash) */ + {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, + "Buffered flash (128kB)"}, + /* Expansion entry 1100 */ + {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1100"}, + /* Expansion entry 1101 */ + {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1101"}, + /* Ateml Expansion entry 1110 */ + {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1110 (Atmel)"}, + /* ATMEL AT45DB021B (buffered flash) */ + {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, + "Buffered flash (256kB)"}, +}; + +/****************************************************************************/ +/* OpenBSD device entry points. */ +/****************************************************************************/ +static int bnx_probe(device_t, cfdata_t, void *); +void bnx_attach(struct device *, struct device *, void *); +#if 0 +void bnx_detach(void *); +#endif +void bnx_shutdown(void *); + +/****************************************************************************/ +/* BNX Debug Data Structure Dump Routines */ +/****************************************************************************/ +#ifdef BNX_DEBUG +void bnx_dump_mbuf(struct bnx_softc *, struct mbuf *); +void bnx_dump_tx_mbuf_chain(struct bnx_softc *, int, int); +void bnx_dump_rx_mbuf_chain(struct bnx_softc *, int, int); +void bnx_dump_txbd(struct bnx_softc *, int, struct tx_bd *); +void bnx_dump_rxbd(struct bnx_softc *, int, struct rx_bd *); +void bnx_dump_l2fhdr(struct bnx_softc *, int, struct l2_fhdr *); +void bnx_dump_tx_chain(struct bnx_softc *, int, int); +void bnx_dump_rx_chain(struct bnx_softc *, int, int); +void bnx_dump_status_block(struct bnx_softc *); +void bnx_dump_stats_block(struct bnx_softc *); +void bnx_dump_driver_state(struct bnx_softc *); +void bnx_dump_hw_state(struct bnx_softc *); +void bnx_breakpoint(struct bnx_softc *); +#endif + +/****************************************************************************/ +/* BNX Register/Memory Access Routines */ +/****************************************************************************/ +u_int32_t bnx_reg_rd_ind(struct bnx_softc *, u_int32_t); +void bnx_reg_wr_ind(struct bnx_softc *, u_int32_t, u_int32_t); +void bnx_ctx_wr(struct bnx_softc *, u_int32_t, u_int32_t, u_int32_t); +int bnx_miibus_read_reg(struct device *, int, int); +void bnx_miibus_write_reg(struct device *, int, int, int); +void bnx_miibus_statchg(struct device *); + +/****************************************************************************/ +/* BNX NVRAM Access Routines */ +/****************************************************************************/ +int bnx_acquire_nvram_lock(struct bnx_softc *); +int bnx_release_nvram_lock(struct bnx_softc *); +void bnx_enable_nvram_access(struct bnx_softc *); +void bnx_disable_nvram_access(struct bnx_softc *); +int bnx_nvram_read_dword(struct bnx_softc *, u_int32_t, u_int8_t *, + u_int32_t); +int bnx_init_nvram(struct bnx_softc *); +int bnx_nvram_read(struct bnx_softc *, u_int32_t, u_int8_t *, int); +int bnx_nvram_test(struct bnx_softc *); +#ifdef BNX_NVRAM_WRITE_SUPPORT +int bnx_enable_nvram_write(struct bnx_softc *); +void bnx_disable_nvram_write(struct bnx_softc *); +int bnx_nvram_erase_page(struct bnx_softc *, u_int32_t); +int bnx_nvram_write_dword(struct bnx_softc *, u_int32_t, u_int8_t *, + u_int32_t); +int bnx_nvram_write(struct bnx_softc *, u_int32_t, u_int8_t *, int); +#endif + +/****************************************************************************/ +/* */ +/****************************************************************************/ +int bnx_dma_alloc(struct bnx_softc *); +void bnx_dma_free(struct bnx_softc *); +void bnx_release_resources(struct bnx_softc *); +void bnx_dma_map_tx_desc(void *, bus_dmamap_t); + +/****************************************************************************/ +/* BNX Firmware Synchronization and Load */ +/****************************************************************************/ +int bnx_fw_sync(struct bnx_softc *, u_int32_t); +void bnx_load_rv2p_fw(struct bnx_softc *, u_int32_t *, u_int32_t, + u_int32_t); +void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *, + struct fw_info *); +void bnx_init_cpus(struct bnx_softc *); + +void bnx_stop(struct bnx_softc *); +int bnx_reset(struct bnx_softc *, u_int32_t); +int bnx_chipinit(struct bnx_softc *); +int bnx_blockinit(struct bnx_softc *); +int bnx_get_buf(struct bnx_softc *, struct mbuf *, u_int16_t *, + u_int16_t *, u_int32_t *); + +int bnx_init_tx_chain(struct bnx_softc *); +int bnx_init_rx_chain(struct bnx_softc *); +void bnx_free_rx_chain(struct bnx_softc *); +void bnx_free_tx_chain(struct bnx_softc *); + +int bnx_tx_encap(struct bnx_softc *, struct mbuf *, u_int16_t *, + u_int16_t *, u_int32_t *); +void bnx_start(struct ifnet *); +int bnx_ioctl(struct ifnet *, u_long, caddr_t); +void bnx_watchdog(struct ifnet *); +int bnx_ifmedia_upd(struct ifnet *); +void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *); +int bnx_init(struct ifnet *); + +void bnx_init_context(struct bnx_softc *); +void bnx_get_mac_addr(struct bnx_softc *); +void bnx_set_mac_addr(struct bnx_softc *); +void bnx_phy_intr(struct bnx_softc *); +void bnx_rx_intr(struct bnx_softc *); +void bnx_tx_intr(struct bnx_softc *); +void bnx_disable_intr(struct bnx_softc *); +void bnx_enable_intr(struct bnx_softc *); + +int bnx_intr(void *); +void bnx_set_rx_mode(struct bnx_softc *); +void bnx_stats_update(struct bnx_softc *); +void bnx_tick(void *); + +/****************************************************************************/ +/* OpenBSD device dispatch table. */ +/****************************************************************************/ +CFATTACH_DECL(bnx, sizeof(struct bnx_softc), + bnx_probe, bnx_attach, NULL, NULL); + +/****************************************************************************/ +/* Device probe function. */ +/* */ +/* Compares the device to the driver's list of supported devices and */ +/* reports back to the OS whether this is the right driver for the device. */ +/* */ +/* Returns: */ +/* BUS_PROBE_DEFAULT on success, positive value on failure. */ +/****************************************************************************/ +static const struct bnx_product * +bnx_lookup(const struct pci_attach_args *pa) +{ + int i; + pcireg_t subid; + + for (i = 0; i < sizeof(bnx_devices)/sizeof(struct bnx_product); i++) { + if (PCI_VENDOR(pa->pa_id) != bnx_devices[i].bp_vendor || + PCI_PRODUCT(pa->pa_id) != bnx_devices[i].bp_product) + continue; + if (!bnx_devices[i].bp_subvendor) + return &bnx_devices[i]; + subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); + if (PCI_VENDOR(subid) == bnx_devices[i].bp_subvendor && + PCI_PRODUCT(subid) == bnx_devices[i].bp_subproduct) + return &bnx_devices[i]; + } + + return NULL; +} +static int +bnx_probe(device_t parent, cfdata_t match, void *aux) +{ + struct pci_attach_args *pa = (struct pci_attach_args *)aux; + + if (bnx_lookup(pa) != NULL) + return (1); + + return (0); +} + +/****************************************************************************/ +/* Device attach function. */ +/* */ +/* Allocates device resources, performs secondary chip identification, */ +/* resets and initializes the hardware, and initializes driver instance */ +/* variables. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +void +bnx_attach(struct device *parent, struct device *self, void *aux) +{ + const struct bnx_product *bp; + struct bnx_softc *sc = (struct bnx_softc *)self; + struct pci_attach_args *pa = aux; + pci_chipset_tag_t pc = pa->pa_pc; + pci_intr_handle_t ih; + const char *intrstr = NULL; + u_int32_t command; + struct ifnet *ifp; + u_int32_t val; + pcireg_t memtype; + + bp = bnx_lookup(pa); + if (bp == NULL) + panic("unknown device"); + + aprint_naive("\n"); + aprint_normal(": %s", bp->bp_name); + + sc->bnx_pa = *pa; + + /* + * Map control/status registers. + */ + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; + pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); + command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); + + if (!(command & PCI_COMMAND_MEM_ENABLE)) { + aprint_error("%s: failed to enable memory mapping!\n", + sc->bnx_dev.dv_xname); + return; + } + + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); + switch (memtype) { + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: + if (pci_mapreg_map(pa, BNX_PCI_BAR0, + memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, + NULL, &sc->bnx_size) == 0) + break; + default: + aprint_error("%s: can't find mem space\n", + sc->bnx_dev.dv_xname); + return; + } + + if (pci_intr_map(pa, &ih)) { + aprint_error("%s: couldn't map interrupt\n", + sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + intrstr = pci_intr_string(pc, ih); + + /* + * Configure byte swap and enable indirect register access. + * Rely on CPU to do target byte swapping on big endian systems. + * Access to registers outside of PCI configurtion space are not + * valid until this is done. + */ + pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_MISC_CONFIG, + BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); + + /* Save ASIC revsion info. */ + sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID); + + /* Weed out any non-production controller revisions. */ + switch(BNX_CHIP_ID(sc)) { + case BNX_CHIP_ID_5706_A0: + case BNX_CHIP_ID_5706_A1: + case BNX_CHIP_ID_5708_A0: + case BNX_CHIP_ID_5708_B0: + aprint_error("%s: unsupported controller revision (%c%d)!\n", + sc->bnx_dev.dv_xname, + ((PCI_REVISION(pa->pa_class) & 0xf0) >> 4) + 'A', + PCI_REVISION(pa->pa_class) & 0x0f); + goto bnx_attach_fail; + } + + if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { + aprint_error("%s: SerDes controllers are not supported!\n", + sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + /* + * Find the base address for shared memory access. + * Newer versions of bootcode use a signature and offset + * while older versions use a fixed address. + */ + val = REG_RD_IND(sc, BNX_SHM_HDR_SIGNATURE); + if ((val & BNX_SHM_HDR_SIGNATURE_SIG_MASK) == BNX_SHM_HDR_SIGNATURE_SIG) + sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0); + else + sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE; + + DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base); + + /* Set initial device and PHY flags */ + sc->bnx_flags = 0; + sc->bnx_phy_flags = 0; + + /* Get PCI bus information (speed and type). */ + val = REG_RD(sc, BNX_PCICFG_MISC_STATUS); + if (val & BNX_PCICFG_MISC_STATUS_PCIX_DET) { + u_int32_t clkreg; + + sc->bnx_flags |= BNX_PCIX_FLAG; + + clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS); + + clkreg &= BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; + switch (clkreg) { + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + sc->bus_speed_mhz = 133; + break; + + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + sc->bus_speed_mhz = 100; + break; + + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + sc->bus_speed_mhz = 66; + break; + + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + sc->bus_speed_mhz = 50; + break; + + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + sc->bus_speed_mhz = 33; + break; + } + } else if (val & BNX_PCICFG_MISC_STATUS_M66EN) + sc->bus_speed_mhz = 66; + else + sc->bus_speed_mhz = 33; + + if (val & BNX_PCICFG_MISC_STATUS_32BIT_DET) + sc->bnx_flags |= BNX_PCI_32BIT_FLAG; + + /* Reset the controller. */ + if (bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) + goto bnx_attach_fail; + + /* Initialize the controller. */ + if (bnx_chipinit(sc)) { + aprint_error("%s: Controller initialization failed!\n", + sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + /* Perform NVRAM test. */ + if (bnx_nvram_test(sc)) { + aprint_error("%s: NVRAM test failed!\n", sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + /* Fetch the permanent Ethernet MAC address. */ + bnx_get_mac_addr(sc); + aprint_normal("%s: Ethernet address %s\n", sc->bnx_dev.dv_xname, + ether_sprintf(sc->eaddr)); + + /* + * Trip points control how many BDs + * should be ready before generating an + * interrupt while ticks control how long + * a BD can sit in the chain before + * generating an interrupt. Set the default + * values for the RX and TX rings. + */ + +#ifdef BNX_DEBUG + /* Force more frequent interrupts. */ + sc->bnx_tx_quick_cons_trip_int = 1; + sc->bnx_tx_quick_cons_trip = 1; + sc->bnx_tx_ticks_int = 0; + sc->bnx_tx_ticks = 0; + + sc->bnx_rx_quick_cons_trip_int = 1; + sc->bnx_rx_quick_cons_trip = 1; + sc->bnx_rx_ticks_int = 0; + sc->bnx_rx_ticks = 0; +#else + sc->bnx_tx_quick_cons_trip_int = 20; + sc->bnx_tx_quick_cons_trip = 20; + sc->bnx_tx_ticks_int = 80; + sc->bnx_tx_ticks = 80; + + sc->bnx_rx_quick_cons_trip_int = 6; + sc->bnx_rx_quick_cons_trip = 6; + sc->bnx_rx_ticks_int = 18; + sc->bnx_rx_ticks = 18; +#endif + + /* Update statistics once every second. */ + sc->bnx_stats_ticks = 1000000 & 0xffff00; + + /* + * The copper based NetXtreme II controllers + * use an integrated PHY at address 1 while + * the SerDes controllers use a PHY at + * address 2. + */ + sc->bnx_phy_addr = 1; + + if (BNX_CHIP_BOND_ID(sc) & BNX_CHIP_BOND_ID_SERDES_BIT) { + sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; + sc->bnx_flags |= BNX_NO_WOL_FLAG; + if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5708) { + sc->bnx_phy_addr = 2; + val = REG_RD_IND(sc, sc->bnx_shmem_base + + BNX_SHARED_HW_CFG_CONFIG); + if (val & BNX_SHARED_HW_CFG_PHY_2_5G) + sc->bnx_phy_flags |= BNX_PHY_2_5G_CAPABLE_FLAG; + } + } + + if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { + aprint_error("%s: SerDes is not supported by this driver!\n", + sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + /* Allocate DMA memory resources. */ + sc->bnx_dmatag = pa->pa_dmat; + if (bnx_dma_alloc(sc)) { + aprint_error("%s: DMA resource allocation failed!\n", + sc->bnx_dev.dv_xname); + goto bnx_attach_fail; + } + + /* Initialize the ifnet interface. */ + ifp = &sc->ethercom.ec_if; + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bnx_ioctl; + ifp->if_start = bnx_start; + ifp->if_init = bnx_init; + ifp->if_timer = 0; + ifp->if_watchdog = bnx_watchdog; + if (sc->bnx_phy_flags & BNX_PHY_2_5G_CAPABLE_FLAG) + ifp->if_baudrate = IF_Gbps(2.5); + else + ifp->if_baudrate = IF_Gbps(1); + IFQ_SET_MAXLEN(&ifp->if_snd, USABLE_TX_BD); + IFQ_SET_READY(&ifp->if_snd); + bcopy(sc->bnx_dev.dv_xname, ifp->if_xname, IFNAMSIZ); + + sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU | + ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; + + ifp->if_capabilities |= + IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | + IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | + IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; + + sc->mbuf_alloc_size = BNX_MAX_MRU; + + /* Hookup IRQ last. */ + sc->bnx_intrhand = pci_intr_establish(pc, ih, IPL_NET, bnx_intr, sc); + if (sc->bnx_intrhand == NULL) { + aprint_error("%s: couldn't establish interrupt", + sc->bnx_dev.dv_xname); + if (intrstr != NULL) + aprint_error(" at %s", intrstr); + aprint_error("\n"); + goto bnx_attach_fail; + } + + sc->bnx_mii.mii_ifp = ifp; + sc->bnx_mii.mii_readreg = bnx_miibus_read_reg; + sc->bnx_mii.mii_writereg = bnx_miibus_write_reg; + sc->bnx_mii.mii_statchg = bnx_miibus_statchg; + + /* Look for our PHY. */ + ifmedia_init(&sc->bnx_mii.mii_media, 0, bnx_ifmedia_upd, + bnx_ifmedia_sts); + mii_attach(&sc->bnx_dev, &sc->bnx_mii, 0xffffffff, + MII_PHY_ANY, MII_OFFSET_ANY, 0); + + if (LIST_FIRST(&sc->bnx_mii.mii_phys) == NULL) { + aprint_error("%s: no PHY found!\n", sc->bnx_dev.dv_xname); + ifmedia_add(&sc->bnx_mii.mii_media, + IFM_ETHER|IFM_MANUAL, 0, NULL); + ifmedia_set(&sc->bnx_mii.mii_media, + IFM_ETHER|IFM_MANUAL); + } else { + ifmedia_set(&sc->bnx_mii.mii_media, + IFM_ETHER|IFM_AUTO); + } + + /* Attach to the Ethernet interface list. */ + if_attach(ifp); + ether_ifattach(ifp,sc->eaddr); + + callout_init(&sc->bnx_timeout); + + /* Print some important debugging info. */ + DBRUN(BNX_INFO, bnx_dump_driver_state(sc)); + + goto bnx_attach_exit; + +bnx_attach_fail: + bnx_release_resources(sc); + +bnx_attach_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); +} + +/****************************************************************************/ +/* Device detach function. */ +/* */ +/* Stops the controller, resets the controller, and releases resources. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +#if 0 +void +bnx_detach(void *xsc) +{ + struct bnx_softc *sc; + struct ifnet *ifp = &sc->arpcom.ac_if; + + sc = device_get_softc(dev); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Stop and reset the controller. */ + bnx_stop(sc); + bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); + + ether_ifdetach(ifp); + + /* If we have a child device on the MII bus remove it too. */ + if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) { + ifmedia_removeall(&sc->bnx_ifmedia); + } else { + bus_generic_detach(dev); + device_delete_child(dev, sc->bnx_mii); + } + + /* Release all remaining resources. */ + bnx_release_resources(sc); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return(0); +} +#endif + +/****************************************************************************/ +/* Device shutdown function. */ +/* */ +/* Stops and resets the controller. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +void +bnx_shutdown(void *xsc) +{ + struct bnx_softc *sc = (struct bnx_softc *)xsc; + + bnx_stop(sc); + bnx_reset(sc, BNX_DRV_MSG_CODE_RESET); +} + +/****************************************************************************/ +/* Indirect register read. */ +/* */ +/* Reads NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* reads but is much slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +u_int32_t +bnx_reg_rd_ind(struct bnx_softc *sc, u_int32_t offset) +{ + struct pci_attach_args *pa = &(sc->bnx_pa); + + pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, + offset); +#ifdef BNX_DEBUG + { + u_int32_t val; + val = pci_conf_read(pa->pa_pc, pa->pa_tag, + BNX_PCICFG_REG_WINDOW); + DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, " + "val = 0x%08X\n", __FUNCTION__, offset, val); + return (val); + } +#else + return pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW); +#endif +} + +/****************************************************************************/ +/* Indirect register write. */ +/* */ +/* Writes NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* writes but is muchh slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_reg_wr_ind(struct bnx_softc *sc, u_int32_t offset, u_int32_t val) +{ + struct pci_attach_args *pa = &(sc->bnx_pa); + + DBPRINT(sc, BNX_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", + __FUNCTION__, offset, val); + + pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW_ADDRESS, + offset); + pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCICFG_REG_WINDOW, val); +} + +/****************************************************************************/ +/* Context memory write. */ +/* */ +/* The NetXtreme II controller uses context memory to track connection */ +/* information for L2 and higher network protocols. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_ctx_wr(struct bnx_softc *sc, u_int32_t cid_addr, u_int32_t offset, + u_int32_t val) +{ + + DBPRINT(sc, BNX_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " + "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); + + offset += cid_addr; + REG_WR(sc, BNX_CTX_DATA_ADR, offset); + REG_WR(sc, BNX_CTX_DATA, val); +} + +/****************************************************************************/ +/* PHY register read. */ +/* */ +/* Implements register reads on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +int +bnx_miibus_read_reg(struct device *dev, int phy, int reg) +{ + struct bnx_softc *sc = (struct bnx_softc *)dev; + u_int32_t val; + int i; + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bnx_phy_addr) { + DBPRINT(sc, BNX_VERBOSE, + "Invalid PHY address %d for PHY read!\n", phy); + return(0); + } + + if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BNX_EMAC_MDIO_MODE); + val &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BNX_EMAC_MDIO_MODE, val); + REG_RD(sc, BNX_EMAC_MDIO_MODE); + + DELAY(40); + } + + val = BNX_MIPHY(phy) | BNX_MIREG(reg) | + BNX_EMAC_MDIO_COMM_COMMAND_READ | BNX_EMAC_MDIO_COMM_DISEXT | + BNX_EMAC_MDIO_COMM_START_BUSY; + REG_WR(sc, BNX_EMAC_MDIO_COMM, val); + + for (i = 0; i < BNX_PHY_TIMEOUT; i++) { + DELAY(10); + + val = REG_RD(sc, BNX_EMAC_MDIO_COMM); + if (!(val & BNX_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + + val = REG_RD(sc, BNX_EMAC_MDIO_COMM); + val &= BNX_EMAC_MDIO_COMM_DATA; + + break; + } + } + + if (val & BNX_EMAC_MDIO_COMM_START_BUSY) { + BNX_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, " + "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); + val = 0x0; + } else + val = REG_RD(sc, BNX_EMAC_MDIO_COMM); + + DBPRINT(sc, BNX_EXCESSIVE, + "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", __FUNCTION__, phy, + (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); + + if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BNX_EMAC_MDIO_MODE); + val |= BNX_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BNX_EMAC_MDIO_MODE, val); + REG_RD(sc, BNX_EMAC_MDIO_MODE); + + DELAY(40); + } + + return (val & 0xffff); +} + +/****************************************************************************/ +/* PHY register write. */ +/* */ +/* Implements register writes on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +void +bnx_miibus_write_reg(struct device *dev, int phy, int reg, int val) +{ + struct bnx_softc *sc = (struct bnx_softc *)dev; + u_int32_t val1; + int i; + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bnx_phy_addr) { + DBPRINT(sc, BNX_WARN, "Invalid PHY address %d for PHY write!\n", + phy); + return; + } + + DBPRINT(sc, BNX_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, " + "val = 0x%04X\n", __FUNCTION__, + phy, (u_int16_t) reg & 0xffff, (u_int16_t) val & 0xffff); + + if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); + val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); + REG_RD(sc, BNX_EMAC_MDIO_MODE); + + DELAY(40); + } + + val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val | + BNX_EMAC_MDIO_COMM_COMMAND_WRITE | + BNX_EMAC_MDIO_COMM_START_BUSY | BNX_EMAC_MDIO_COMM_DISEXT; + REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); + + for (i = 0; i < BNX_PHY_TIMEOUT; i++) { + DELAY(10); + + val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM); + if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + + if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) { + BNX_PRINTF(sc, "%s(%d): PHY write timeout!\n", __FILE__, + __LINE__); + } + + if (sc->bnx_phy_flags & BNX_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE); + val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); + REG_RD(sc, BNX_EMAC_MDIO_MODE); + + DELAY(40); + } +} + +/****************************************************************************/ +/* MII bus status change. */ +/* */ +/* Called by the MII bus driver when the PHY establishes link to set the */ +/* MAC interface registers. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_miibus_statchg(struct device *dev) +{ + struct bnx_softc *sc = (struct bnx_softc *)dev; + struct mii_data *mii = &sc->bnx_mii; + + BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT); + + /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { + DBPRINT(sc, BNX_INFO, "Setting GMII interface.\n"); + BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_GMII); + } else { + DBPRINT(sc, BNX_INFO, "Setting MII interface.\n"); + BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_PORT_MII); + } + + /* Set half or full duplex based on the duplicity + * negotiated by the PHY. + */ + if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { + DBPRINT(sc, BNX_INFO, "Setting Full-Duplex interface.\n"); + BNX_CLRBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); + } else { + DBPRINT(sc, BNX_INFO, "Setting Half-Duplex interface.\n"); + BNX_SETBIT(sc, BNX_EMAC_MODE, BNX_EMAC_MODE_HALF_DUPLEX); + } +} + +/****************************************************************************/ +/* Acquire NVRAM lock. */ +/* */ +/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_acquire_nvram_lock(struct bnx_softc *sc) +{ + u_int32_t val; + int j; + + DBPRINT(sc, BNX_VERBOSE, "Acquiring NVRAM lock.\n"); + + /* Request access to the flash interface. */ + REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BNX_NVM_SW_ARB); + if (val & BNX_NVM_SW_ARB_ARB_ARB2) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BNX_WARN, "Timeout acquiring NVRAM lock!\n"); + return (EBUSY); + } + + return (0); +} + +/****************************************************************************/ +/* Release NVRAM lock. */ +/* */ +/* When the caller is finished accessing NVRAM the lock must be released. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_release_nvram_lock(struct bnx_softc *sc) +{ + int j; + u_int32_t val; + + DBPRINT(sc, BNX_VERBOSE, "Releasing NVRAM lock.\n"); + + /* Relinquish nvram interface. */ + REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BNX_NVM_SW_ARB); + if (!(val & BNX_NVM_SW_ARB_ARB_ARB2)) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BNX_WARN, "Timeout reeasing NVRAM lock!\n"); + return (EBUSY); + } + + return (0); +} + +#ifdef BNX_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Enable NVRAM write access. */ +/* */ +/* Before writing to NVRAM the caller must enable NVRAM writes. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_enable_nvram_write(struct bnx_softc *sc) +{ + u_int32_t val; + + DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM write.\n"); + + val = REG_RD(sc, BNX_MISC_CFG); + REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); + + if (!sc->bnx_flash_info->buffered) { + int j; + + REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); + REG_WR(sc, BNX_NVM_COMMAND, + BNX_NVM_COMMAND_WREN | BNX_NVM_COMMAND_DOIT); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + val = REG_RD(sc, BNX_NVM_COMMAND); + if (val & BNX_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BNX_WARN, "Timeout writing NVRAM!\n"); + return (EBUSY); + } + } + + return (0); +} + +/****************************************************************************/ +/* Disable NVRAM write access. */ +/* */ +/* When the caller is finished writing to NVRAM write access must be */ +/* disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_disable_nvram_write(struct bnx_softc *sc) +{ + u_int32_t val; + + DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM write.\n"); + + val = REG_RD(sc, BNX_MISC_CFG); + REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); +} +#endif + +/****************************************************************************/ +/* Enable NVRAM access. */ +/* */ +/* Before accessing NVRAM for read or write operations the caller must */ +/* enabled NVRAM access. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_enable_nvram_access(struct bnx_softc *sc) +{ + u_int32_t val; + + DBPRINT(sc, BNX_VERBOSE, "Enabling NVRAM access.\n"); + + val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); + /* Enable both bits, even on read. */ + REG_WR(sc, BNX_NVM_ACCESS_ENABLE, + val | BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN); +} + +/****************************************************************************/ +/* Disable NVRAM access. */ +/* */ +/* When the caller is finished accessing NVRAM access must be disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_disable_nvram_access(struct bnx_softc *sc) +{ + u_int32_t val; + + DBPRINT(sc, BNX_VERBOSE, "Disabling NVRAM access.\n"); + + val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE); + + /* Disable both bits, even after read. */ + REG_WR(sc, BNX_NVM_ACCESS_ENABLE, + val & ~(BNX_NVM_ACCESS_ENABLE_EN | BNX_NVM_ACCESS_ENABLE_WR_EN)); +} + +#ifdef BNX_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Erase NVRAM page before writing. */ +/* */ +/* Non-buffered flash parts require that a page be erased before it is */ +/* written. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_erase_page(struct bnx_softc *sc, u_int32_t offset) +{ + u_int32_t cmd; + int j; + + /* Buffered flash doesn't require an erase. */ + if (sc->bnx_flash_info->buffered) + return (0); + + DBPRINT(sc, BNX_VERBOSE, "Erasing NVRAM page.\n"); + + /* Build an erase command. */ + cmd = BNX_NVM_COMMAND_ERASE | BNX_NVM_COMMAND_WR | + BNX_NVM_COMMAND_DOIT; + + /* + * Clear the DONE bit separately, set the NVRAM adress to erase, + * and issue the erase command. + */ + REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); + REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BNX_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + u_int32_t val; + + DELAY(5); + + val = REG_RD(sc, BNX_NVM_COMMAND); + if (val & BNX_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BNX_WARN, "Timeout erasing NVRAM.\n"); + return (EBUSY); + } + + return (0); +} +#endif /* BNX_NVRAM_WRITE_SUPPORT */ + +/****************************************************************************/ +/* Read a dword (32 bits) from NVRAM. */ +/* */ +/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ +/* */ +/* Returns: */ +/* 0 on success and the 32 bit value read, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_read_dword(struct bnx_softc *sc, u_int32_t offset, + u_int8_t *ret_val, u_int32_t cmd_flags) +{ + u_int32_t cmd; + int i, rc = 0; + + /* Build the command word. */ + cmd = BNX_NVM_COMMAND_DOIT | cmd_flags; + + /* Calculate the offset for buffered flash. */ + if (sc->bnx_flash_info->buffered) + offset = ((offset / sc->bnx_flash_info->page_size) << + sc->bnx_flash_info->page_bits) + + (offset % sc->bnx_flash_info->page_size); + + /* + * Clear the DONE bit separately, set the address to read, + * and issue the read. + */ + REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); + REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BNX_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { + u_int32_t val; + + DELAY(5); + + val = REG_RD(sc, BNX_NVM_COMMAND); + if (val & BNX_NVM_COMMAND_DONE) { + val = REG_RD(sc, BNX_NVM_READ); + + val = bnx_be32toh(val); + memcpy(ret_val, &val, 4); + break; + } + } + + /* Check for errors. */ + if (i >= NVRAM_TIMEOUT_COUNT) { + BNX_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at " + "offset 0x%08X!\n", __FILE__, __LINE__, offset); + rc = EBUSY; + } + + return(rc); +} + +#ifdef BNX_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write a dword (32 bits) to NVRAM. */ +/* */ +/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ +/* enabled NVRAM write access. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_write_dword(struct bnx_softc *sc, u_int32_t offset, u_int8_t *val, + u_int32_t cmd_flags) +{ + u_int32_t cmd, val32; + int j; + + /* Build the command word. */ + cmd = BNX_NVM_COMMAND_DOIT | BNX_NVM_COMMAND_WR | cmd_flags; + + /* Calculate the offset for buffered flash. */ + if (sc->bnx_flash_info->buffered) + offset = ((offset / sc->bnx_flash_info->page_size) << + sc->bnx_flash_info->page_bits) + + (offset % sc->bnx_flash_info->page_size); + + /* + * Clear the DONE bit separately, convert NVRAM data to big-endian, + * set the NVRAM address to write, and issue the write command + */ + REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); + memcpy(&val32, val, 4); + val32 = htobe32(val32); + REG_WR(sc, BNX_NVM_WRITE, val32); + REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BNX_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE) + break; + } + if (j >= NVRAM_TIMEOUT_COUNT) { + BNX_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at " + "offset 0x%08X\n", __FILE__, __LINE__, offset); + return (EBUSY); + } + + return (0); +} +#endif /* BNX_NVRAM_WRITE_SUPPORT */ + +/****************************************************************************/ +/* Initialize NVRAM access. */ +/* */ +/* Identify the NVRAM device in use and prepare the NVRAM interface to */ +/* access that device. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_init_nvram(struct bnx_softc *sc) +{ + u_int32_t val; + int j, entry_count, rc; + struct flash_spec *flash; + + DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Determine the selected interface. */ + val = REG_RD(sc, BNX_NVM_CFG1); + + entry_count = sizeof(flash_table) / sizeof(struct flash_spec); + + rc = 0; + + /* + * Flash reconfiguration is required to support additional + * NVRAM devices not directly supported in hardware. + * Check if the flash interface was reconfigured + * by the bootcode. + */ + + if (val & 0x40000000) { + /* Flash interface reconfigured by bootcode. */ + + DBPRINT(sc,BNX_INFO_LOAD, + "bnx_init_nvram(): Flash WAS reconfigured.\n"); + + for (j = 0, flash = &flash_table[0]; j < entry_count; + j++, flash++) { + if ((val & FLASH_BACKUP_STRAP_MASK) == + (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { + sc->bnx_flash_info = flash; + break; + } + } + } else { + /* Flash interface not yet reconfigured. */ + u_int32_t mask; + + DBPRINT(sc,BNX_INFO_LOAD, + "bnx_init_nvram(): Flash was NOT reconfigured.\n"); + + if (val & (1 << 23)) + mask = FLASH_BACKUP_STRAP_MASK; + else + mask = FLASH_STRAP_MASK; + + /* Look for the matching NVRAM device configuration data. */ + for (j = 0, flash = &flash_table[0]; j < entry_count; + j++, flash++) { + /* Check if the dev matches any of the known devices. */ + if ((val & mask) == (flash->strapping & mask)) { + /* Found a device match. */ + sc->bnx_flash_info = flash; + + /* Request access to the flash interface. */ + if ((rc = bnx_acquire_nvram_lock(sc)) != 0) + return (rc); + + /* Reconfigure the flash interface. */ + bnx_enable_nvram_access(sc); + REG_WR(sc, BNX_NVM_CFG1, flash->config1); + REG_WR(sc, BNX_NVM_CFG2, flash->config2); + REG_WR(sc, BNX_NVM_CFG3, flash->config3); + REG_WR(sc, BNX_NVM_WRITE1, flash->write1); + bnx_disable_nvram_access(sc); + bnx_release_nvram_lock(sc); + + break; + } + } + } + + /* Check if a matching device was found. */ + if (j == entry_count) { + sc->bnx_flash_info = NULL; + BNX_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", + __FILE__, __LINE__); + rc = ENODEV; + } + + /* Write the flash config data to the shared memory interface. */ + val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2); + val &= BNX_SHARED_HW_CFG2_NVM_SIZE_MASK; + if (val) + sc->bnx_flash_size = val; + else + sc->bnx_flash_size = sc->bnx_flash_info->total_size; + + DBPRINT(sc, BNX_INFO_LOAD, "bnx_init_nvram() flash->total_size = " + "0x%08X\n", sc->bnx_flash_info->total_size); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return (rc); +} + +/****************************************************************************/ +/* Read an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for access and reads the requested data */ +/* into the supplied buffer. */ +/* */ +/* Returns: */ +/* 0 on success and the data read, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_read(struct bnx_softc *sc, u_int32_t offset, u_int8_t *ret_buf, + int buf_size) +{ + int rc = 0; + u_int32_t cmd_flags, offset32, len32, extra; + + if (buf_size == 0) + return (0); + + /* Request access to the flash interface. */ + if ((rc = bnx_acquire_nvram_lock(sc)) != 0) + return (rc); + + /* Enable access to flash interface */ + bnx_enable_nvram_access(sc); + + len32 = buf_size; + offset32 = offset; + extra = 0; + + cmd_flags = 0; + + if (offset32 & 3) { + u_int8_t buf[4]; + u_int32_t pre_len; + + offset32 &= ~3; + pre_len = 4 - (offset & 3); + + if (pre_len >= len32) { + pre_len = len32; + cmd_flags = + BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; + } else + cmd_flags = BNX_NVM_COMMAND_FIRST; + + rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); + + if (rc) + return (rc); + + memcpy(ret_buf, buf + (offset & 3), pre_len); + + offset32 += 4; + ret_buf += pre_len; + len32 -= pre_len; + } + + if (len32 & 3) { + extra = 4 - (len32 & 3); + len32 = (len32 + 4) & ~3; + } + + if (len32 == 4) { + u_int8_t buf[4]; + + if (cmd_flags) + cmd_flags = BNX_NVM_COMMAND_LAST; + else + cmd_flags = + BNX_NVM_COMMAND_FIRST | BNX_NVM_COMMAND_LAST; + + rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } else if (len32 > 0) { + u_int8_t buf[4]; + + /* Read the first word. */ + if (cmd_flags) + cmd_flags = 0; + else + cmd_flags = BNX_NVM_COMMAND_FIRST; + + rc = bnx_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + + while (len32 > 4 && rc == 0) { + rc = bnx_nvram_read_dword(sc, offset32, ret_buf, 0); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + } + + if (rc) + return (rc); + + cmd_flags = BNX_NVM_COMMAND_LAST; + rc = bnx_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } + + /* Disable access to flash interface and release the lock. */ + bnx_disable_nvram_access(sc); + bnx_release_nvram_lock(sc); + + return (rc); +} + +#ifdef BNX_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for write access and writes the requested */ +/* data from the supplied buffer. The caller is responsible for */ +/* calculating any appropriate CRCs. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_write(struct bnx_softc *sc, u_int32_t offset, u_int8_t *data_buf, + int buf_size) +{ + u_int32_t written, offset32, len32; + u_int8_t *buf, start[4], end[4]; + int rc = 0; + int align_start, align_end; + + buf = data_buf; + offset32 = offset; + len32 = buf_size; + align_start = align_end = 0; + + if ((align_start = (offset32 & 3))) { + offset32 &= ~3; + len32 += align_start; + if ((rc = bnx_nvram_read(sc, offset32, start, 4))) + return (rc); + } + + if (len32 & 3) { + if ((len32 > 4) || !align_start) { + align_end = 4 - (len32 & 3); + len32 += align_end; + if ((rc = bnx_nvram_read(sc, offset32 + len32 - 4, + end, 4))) { + return (rc); + } + } + } + + if (align_start || align_end) { + buf = malloc(len32, M_DEVBUF, M_NOWAIT); + if (buf == 0) + return (ENOMEM); + + if (align_start) + memcpy(buf, start, 4); + + if (align_end) + memcpy(buf + len32 - 4, end, 4); + + memcpy(buf + align_start, data_buf, buf_size); + } + + written = 0; + while ((written < len32) && (rc == 0)) { + u_int32_t page_start, page_end, data_start, data_end; + u_int32_t addr, cmd_flags; + int i; + u_int8_t flash_buffer[264]; + + /* Find the page_start addr */ + page_start = offset32 + written; + page_start -= (page_start % sc->bnx_flash_info->page_size); + /* Find the page_end addr */ + page_end = page_start + sc->bnx_flash_info->page_size; + /* Find the data_start addr */ + data_start = (written == 0) ? offset32 : page_start; + /* Find the data_end addr */ + data_end = (page_end > offset32 + len32) ? + (offset32 + len32) : page_end; + + /* Request access to the flash interface. */ + if ((rc = bnx_acquire_nvram_lock(sc)) != 0) + goto nvram_write_end; + + /* Enable access to flash interface */ + bnx_enable_nvram_access(sc); + + cmd_flags = BNX_NVM_COMMAND_FIRST; + if (sc->bnx_flash_info->buffered == 0) { + int j; + + /* Read the whole page into the buffer + * (non-buffer flash only) */ + for (j = 0; j < sc->bnx_flash_info->page_size; j += 4) { + if (j == (sc->bnx_flash_info->page_size - 4)) + cmd_flags |= BNX_NVM_COMMAND_LAST; + + rc = bnx_nvram_read_dword(sc, + page_start + j, + &flash_buffer[j], + cmd_flags); + + if (rc) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Enable writes to flash interface (unlock write-protect) */ + if ((rc = bnx_enable_nvram_write(sc)) != 0) + goto nvram_write_end; + + /* Erase the page */ + if ((rc = bnx_nvram_erase_page(sc, page_start)) != 0) + goto nvram_write_end; + + /* Re-enable the write again for the actual write */ + bnx_enable_nvram_write(sc); + + /* Loop to write back the buffer data from page_start to + * data_start */ + i = 0; + if (sc->bnx_flash_info->buffered == 0) { + for (addr = page_start; addr < data_start; + addr += 4, i += 4) { + + rc = bnx_nvram_write_dword(sc, addr, + &flash_buffer[i], cmd_flags); + + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Loop to write the new data from data_start to data_end */ + for (addr = data_start; addr < data_end; addr += 4, i++) { + if ((addr == page_end - 4) || + ((sc->bnx_flash_info->buffered) && + (addr == data_end - 4))) { + + cmd_flags |= BNX_NVM_COMMAND_LAST; + } + + rc = bnx_nvram_write_dword(sc, addr, buf, cmd_flags); + + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + buf += 4; + } + + /* Loop to write back the buffer data from data_end + * to page_end */ + if (sc->bnx_flash_info->buffered == 0) { + for (addr = data_end; addr < page_end; + addr += 4, i += 4) { + + if (addr == page_end-4) + cmd_flags = BNX_NVM_COMMAND_LAST; + + rc = bnx_nvram_write_dword(sc, addr, + &flash_buffer[i], cmd_flags); + + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Disable writes to flash interface (lock write-protect) */ + bnx_disable_nvram_write(sc); + + /* Disable access to flash interface */ + bnx_disable_nvram_access(sc); + bnx_release_nvram_lock(sc); + + /* Increment written */ + written += data_end - data_start; + } + +nvram_write_end: + if (align_start || align_end) + free(buf, M_DEVBUF); + + return (rc); +} +#endif /* BNX_NVRAM_WRITE_SUPPORT */ + +/****************************************************************************/ +/* Verifies that NVRAM is accessible and contains valid data. */ +/* */ +/* Reads the configuration data from NVRAM and verifies that the CRC is */ +/* correct. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +int +bnx_nvram_test(struct bnx_softc *sc) +{ + u_int32_t buf[BNX_NVRAM_SIZE / 4]; + u_int8_t *data = (u_int8_t *) buf; + int rc = 0; + u_int32_t magic, csum; + + /* + * Check that the device NVRAM is valid by reading + * the magic value at offset 0. + */ + if ((rc = bnx_nvram_read(sc, 0, data, 4)) != 0) + goto bnx_nvram_test_done; + + magic = bnx_be32toh(buf[0]); + if (magic != BNX_NVRAM_MAGIC) { + rc = ENODEV; + BNX_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! " + "Expected: 0x%08X, Found: 0x%08X\n", + __FILE__, __LINE__, BNX_NVRAM_MAGIC, magic); + goto bnx_nvram_test_done; + } + + /* + * Verify that the device NVRAM includes valid + * configuration data. + */ + if ((rc = bnx_nvram_read(sc, 0x100, data, BNX_NVRAM_SIZE)) != 0) + goto bnx_nvram_test_done; + + csum = ether_crc32_le(data, 0x100); + if (csum != BNX_CRC32_RESIDUAL) { + rc = ENODEV; + BNX_PRINTF(sc, "%s(%d): Invalid Manufacturing Information " + "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", + __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); + goto bnx_nvram_test_done; + } + + csum = ether_crc32_le(data + 0x100, 0x100); + if (csum != BNX_CRC32_RESIDUAL) { + BNX_PRINTF(sc, "%s(%d): Invalid Feature Configuration " + "Information NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", + __FILE__, __LINE__, BNX_CRC32_RESIDUAL, csum); + rc = ENODEV; + } + +bnx_nvram_test_done: + return (rc); +} + +/****************************************************************************/ +/* Free any DMA memory owned by the driver. */ +/* */ +/* Scans through each data structre that requires DMA memory and frees */ +/* the memory if allocated. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_dma_free(struct bnx_softc *sc) +{ + int i; + + DBPRINT(sc,BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Destroy the status block. */ + if (sc->status_block != NULL && sc->status_map != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); + bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->status_block, + BNX_STATUS_BLK_SZ); + bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, + sc->status_rseg); + bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); + sc->status_block = NULL; + sc->status_map = NULL; + } + + /* Destroy the statistics block. */ + if (sc->stats_block != NULL && sc->stats_map != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); + bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->stats_block, + BNX_STATS_BLK_SZ); + bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, + sc->stats_rseg); + bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); + sc->stats_block = NULL; + sc->stats_map = NULL; + } + + /* Free, unmap and destroy all TX buffer descriptor chain pages. */ + for (i = 0; i < TX_PAGES; i++ ) { + if (sc->tx_bd_chain[i] != NULL && + sc->tx_bd_chain_map[i] != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, + sc->tx_bd_chain_map[i]); + bus_dmamem_unmap(sc->bnx_dmatag, + (caddr_t)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); + bus_dmamem_free(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], + sc->tx_bd_chain_rseg[i]); + bus_dmamap_destroy(sc->bnx_dmatag, + sc->tx_bd_chain_map[i]); + sc->tx_bd_chain[i] = NULL; + sc->tx_bd_chain_map[i] = NULL; + } + } + + /* Unload and destroy the TX mbuf maps. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (sc->tx_mbuf_map[i] != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, sc->tx_mbuf_map[i]); + bus_dmamap_destroy(sc->bnx_dmatag, sc->tx_mbuf_map[i]); + } + } + + /* Free, unmap and destroy all RX buffer descriptor chain pages. */ + for (i = 0; i < RX_PAGES; i++ ) { + if (sc->rx_bd_chain[i] != NULL && + sc->rx_bd_chain_map[i] != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, + sc->rx_bd_chain_map[i]); + bus_dmamem_unmap(sc->bnx_dmatag, + (caddr_t)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); + bus_dmamem_free(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], + sc->rx_bd_chain_rseg[i]); + + bus_dmamap_destroy(sc->bnx_dmatag, + sc->rx_bd_chain_map[i]); + sc->rx_bd_chain[i] = NULL; + sc->rx_bd_chain_map[i] = NULL; + } + } + + /* Unload and destroy the RX mbuf maps. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (sc->rx_mbuf_map[i] != NULL) { + bus_dmamap_unload(sc->bnx_dmatag, sc->rx_mbuf_map[i]); + bus_dmamap_destroy(sc->bnx_dmatag, sc->rx_mbuf_map[i]); + } + } + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); +} + +/****************************************************************************/ +/* Map TX buffers into TX buffer descriptors. */ +/* */ +/* Given a series of DMA memory containting an outgoing frame, map the */ +/* segments into the tx_bd structure used by the hardware. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_dma_map_tx_desc(void *arg, bus_dmamap_t map) +{ + struct bnx_dmamap_arg *map_arg; + struct bnx_softc *sc; + struct tx_bd *txbd = NULL; + int i = 0, nseg; + u_int16_t prod, chain_prod; + u_int32_t prod_bseq, addr; +#ifdef BNX_DEBUG + u_int16_t debug_prod; +#endif + + map_arg = arg; + sc = map_arg->sc; + nseg = map->dm_nsegs; + + /* Signal error to caller if there's too many segments */ + if (nseg > map_arg->maxsegs) { + DBPRINT(sc, BNX_WARN, "%s(): Mapped TX descriptors: max segs " + "= %d, " "actual segs = %d\n", + __FUNCTION__, map_arg->maxsegs, nseg); + + map_arg->maxsegs = 0; + return; + } + + /* prod points to an empty tx_bd at this point. */ + prod = map_arg->prod; + chain_prod = map_arg->chain_prod; + prod_bseq = map_arg->prod_bseq; + +#ifdef BNX_DEBUG + debug_prod = chain_prod; +#endif + + DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: prod = 0x%04X, chain_prod " + "= %04X, " "prod_bseq = 0x%08X\n", + __FUNCTION__, prod, chain_prod, prod_bseq); + + /* + * Cycle through each mbuf segment that makes up + * the outgoing frame, gathering the mapping info + * for that segment and creating a tx_bd for the + * mbuf. + */ + + txbd = &map_arg->tx_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; + + /* Setup the first tx_bd for the first segment. */ + addr = (u_int32_t)(map->dm_segs[i].ds_addr); + txbd->tx_bd_haddr_lo = htole32(addr); + addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); + txbd->tx_bd_haddr_hi = htole32(addr); + txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); + txbd->tx_bd_vlan_tag_flags = htole16(map_arg->tx_flags | + TX_BD_FLAGS_START); + prod_bseq += map->dm_segs[i].ds_len; + + bus_dmamap_sync(sc->bnx_dmatag, + sc->tx_bd_chain_map[TX_PAGE(chain_prod)], + sizeof(struct tx_bd) * TX_IDX(chain_prod), + sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); + + /* Setup any remaing segments. */ + for (i = 1; i < nseg; i++) { + prod = NEXT_TX_BD(prod); + chain_prod = TX_CHAIN_IDX(prod); + + txbd = + &map_arg->tx_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; + + addr = (u_int32_t)(map->dm_segs[i].ds_addr); + txbd->tx_bd_haddr_lo = htole32(addr); + addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); + txbd->tx_bd_haddr_hi = htole32(addr); + txbd->tx_bd_mss_nbytes = htole16(map->dm_segs[i].ds_len); + txbd->tx_bd_vlan_tag_flags = htole16(map_arg->tx_flags); + + prod_bseq += map->dm_segs[i].ds_len; + bus_dmamap_sync(sc->bnx_dmatag, + sc->tx_bd_chain_map[TX_PAGE(chain_prod)], + sizeof(struct tx_bd) * TX_IDX(chain_prod), + sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); + } + + /* Set the END flag on the last TX buffer descriptor. */ + txbd->tx_bd_vlan_tag_flags |= htole16(TX_BD_FLAGS_END); + bus_dmamap_sync(sc->bnx_dmatag, + sc->tx_bd_chain_map[TX_PAGE(chain_prod)], + sizeof(struct tx_bd) * TX_IDX(chain_prod), + sizeof(struct tx_bd), BUS_DMASYNC_PREWRITE); + + DBRUN(BNX_INFO_SEND, bnx_dump_tx_chain(sc, debug_prod, nseg)); + + DBPRINT(sc, BNX_INFO_SEND, "%s(): End: prod = 0x%04X, chain_prod " + "= %04X, " "prod_bseq = 0x%08X\n", + __FUNCTION__, prod, chain_prod, prod_bseq); + + /* prod points to the last tx_bd at this point. */ + map_arg->maxsegs = nseg; + map_arg->prod = prod; + map_arg->chain_prod = chain_prod; + map_arg->prod_bseq = prod_bseq; +} + +/****************************************************************************/ +/* Allocate any DMA memory needed by the driver. */ +/* */ +/* Allocates DMA memory needed for the various global structures needed by */ +/* hardware. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_dma_alloc(struct bnx_softc *sc) +{ + int i, rc = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* + * Allocate DMA memory for the status block, map the memory into DMA + * space, and fetch the physical address of the block. + */ + if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, 1, + BNX_STATUS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->status_map)) { + aprint_error("%s: Could not create status block DMA map!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATUS_BLK_SZ, + BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->status_seg, 1, + &sc->status_rseg, BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not allocate status block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_map(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg, + BNX_STATUS_BLK_SZ, (caddr_t *)&sc->status_block, BUS_DMA_NOWAIT)) { + aprint_error("%s: Could not map status block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamap_load(sc->bnx_dmatag, sc->status_map, + sc->status_block, BNX_STATUS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { + aprint_error("%s: Could not load status block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + sc->status_block_paddr = sc->status_map->dm_segs[0].ds_addr; + bzero(sc->status_block, BNX_STATUS_BLK_SZ); + + /* DRC - Fix for 64 bit addresses. */ + DBPRINT(sc, BNX_INFO, "status_block_paddr = 0x%08X\n", + (u_int32_t) sc->status_block_paddr); + + /* + * Allocate DMA memory for the statistics block, map the memory into + * DMA space, and fetch the physical address of the block. + */ + if (bus_dmamap_create(sc->bnx_dmatag, BNX_STATS_BLK_SZ, 1, + BNX_STATS_BLK_SZ, 0, BUS_DMA_NOWAIT, &sc->stats_map)) { + aprint_error("%s: Could not create stats block DMA map!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_STATS_BLK_SZ, + BNX_DMA_ALIGN, BNX_DMA_BOUNDARY, &sc->stats_seg, 1, + &sc->stats_rseg, BUS_DMA_NOWAIT)) { + aprint_error("%s: Could not allocate stats block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_map(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg, + BNX_STATS_BLK_SZ, (caddr_t *)&sc->stats_block, BUS_DMA_NOWAIT)) { + aprint_error("%s: Could not map stats block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamap_load(sc->bnx_dmatag, sc->stats_map, + sc->stats_block, BNX_STATS_BLK_SZ, NULL, BUS_DMA_NOWAIT)) { + aprint_error("%s: Could not load status block DMA memory!\n", + sc->bnx_dev.dv_xname); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; + bzero(sc->stats_block, BNX_STATS_BLK_SZ); + + /* DRC - Fix for 64 bit address. */ + DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", + (u_int32_t) sc->stats_block_paddr); + + /* + * Allocate DMA memory for the TX buffer descriptor chain, + * and fetch the physical address of the block. + */ + for (i = 0; i < TX_PAGES; i++) { + if (bus_dmamap_create(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, 1, + BNX_TX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, + &sc->tx_bd_chain_map[i])) { + aprint_error( + "%s: Could not create Tx desc %d DMA map!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_TX_CHAIN_PAGE_SZ, + BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->tx_bd_chain_seg[i], 1, + &sc->tx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not allocate TX desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_map(sc->bnx_dmatag, &sc->tx_bd_chain_seg[i], + sc->tx_bd_chain_rseg[i], BNX_TX_CHAIN_PAGE_SZ, + (caddr_t *)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not map TX desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamap_load(sc->bnx_dmatag, sc->tx_bd_chain_map[i], + (caddr_t)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ, NULL, + BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not load TX desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + sc->tx_bd_chain_paddr[i] = + sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; + + /* DRC - Fix for 64 bit systems. */ + DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", + i, (u_int32_t) sc->tx_bd_chain_paddr[i]); + } + + /* + * Create DMA maps for the TX buffer mbufs. + */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (bus_dmamap_create(sc->bnx_dmatag, + MCLBYTES * BNX_MAX_SEGMENTS, + USABLE_TX_BD - BNX_TX_SLACK_SPACE, + MCLBYTES, 0, BUS_DMA_NOWAIT, + &sc->tx_mbuf_map[i])) { + aprint_error( + "%s: Could not create Tx mbuf %d DMA map!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + } + + /* + * Allocate DMA memory for the Rx buffer descriptor chain, + * and fetch the physical address of the block. + */ + for (i = 0; i < RX_PAGES; i++) { + if (bus_dmamap_create(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, 1, + BNX_RX_CHAIN_PAGE_SZ, 0, BUS_DMA_NOWAIT, + &sc->rx_bd_chain_map[i])) { + aprint_error( + "%s: Could not create Rx desc %d DMA map!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, + BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, + &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not allocate Rx desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamem_map(sc->bnx_dmatag, &sc->rx_bd_chain_seg[i], + sc->rx_bd_chain_rseg[i], BNX_RX_CHAIN_PAGE_SZ, + (caddr_t *)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not map Rx desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + if (bus_dmamap_load(sc->bnx_dmatag, sc->rx_bd_chain_map[i], + (caddr_t)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ, NULL, + BUS_DMA_NOWAIT)) { + aprint_error( + "%s: Could not load Rx desc %d DMA memory!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + + bzero(sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); + sc->rx_bd_chain_paddr[i] = + sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; + + /* DRC - Fix for 64 bit systems. */ + DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", + i, (u_int32_t) sc->rx_bd_chain_paddr[i]); + bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], + 0, BNX_RX_CHAIN_PAGE_SZ, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + /* + * Create DMA maps for the Rx buffer mbufs. + */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (bus_dmamap_create(sc->bnx_dmatag, BNX_MAX_MRU, + BNX_MAX_SEGMENTS, BNX_MAX_MRU, 0, BUS_DMA_NOWAIT, + &sc->rx_mbuf_map[i])) { + aprint_error( + "%s: Could not create Rx mbuf %d DMA map!\n", + sc->bnx_dev.dv_xname, i); + rc = ENOMEM; + goto bnx_dma_alloc_exit; + } + } + + bnx_dma_alloc_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return(rc); +} + +/****************************************************************************/ +/* Release all resources used by the driver. */ +/* */ +/* Releases all resources acquired by the driver including interrupts, */ +/* interrupt handler, interfaces, mutexes, and DMA memory. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_release_resources(struct bnx_softc *sc) +{ + struct pci_attach_args *pa = &(sc->bnx_pa); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + bnx_dma_free(sc); + + if (sc->bnx_intrhand != NULL) + pci_intr_disestablish(pa->pa_pc, sc->bnx_intrhand); + + if (sc->bnx_size) + bus_space_unmap(sc->bnx_btag, sc->bnx_bhandle, sc->bnx_size); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); +} + +/****************************************************************************/ +/* Firmware synchronization. */ +/* */ +/* Before performing certain events such as a chip reset, synchronize with */ +/* the firmware first. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_fw_sync(struct bnx_softc *sc, u_int32_t msg_data) +{ + int i, rc = 0; + u_int32_t val; + + /* Don't waste any time if we've timed out before. */ + if (sc->bnx_fw_timed_out) { + rc = EBUSY; + goto bnx_fw_sync_exit; + } + + /* Increment the message sequence number. */ + sc->bnx_fw_wr_seq++; + msg_data |= sc->bnx_fw_wr_seq; + + DBPRINT(sc, BNX_VERBOSE, "bnx_fw_sync(): msg_data = 0x%08X\n", + msg_data); + + /* Send the message to the bootcode driver mailbox. */ + REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); + + /* Wait for the bootcode to acknowledge the message. */ + for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { + /* Check for a response in the bootcode firmware mailbox. */ + val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB); + if ((val & BNX_FW_MSG_ACK) == (msg_data & BNX_DRV_MSG_SEQ)) + break; + DELAY(1000); + } + + /* If we've timed out, tell the bootcode that we've stopped waiting. */ + if (((val & BNX_FW_MSG_ACK) != (msg_data & BNX_DRV_MSG_SEQ)) && + ((msg_data & BNX_DRV_MSG_DATA) != BNX_DRV_MSG_DATA_WAIT0)) { + BNX_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " + "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); + + msg_data &= ~BNX_DRV_MSG_CODE; + msg_data |= BNX_DRV_MSG_CODE_FW_TIMEOUT; + + REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data); + + sc->bnx_fw_timed_out = 1; + rc = EBUSY; + } + +bnx_fw_sync_exit: + return (rc); +} + +/****************************************************************************/ +/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, + u_int32_t rv2p_code_len, u_int32_t rv2p_proc) +{ + int i; + u_int32_t val; + + for (i = 0; i < rv2p_code_len; i += 8) { + REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); + rv2p_code++; + REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); + rv2p_code++; + + if (rv2p_proc == RV2P_PROC1) { + val = (i / 8) | BNX_RV2P_PROC1_ADDR_CMD_RDWR; + REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); + } + else { + val = (i / 8) | BNX_RV2P_PROC2_ADDR_CMD_RDWR; + REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); + } + } + + /* Reset the processor, un-stall is done later. */ + if (rv2p_proc == RV2P_PROC1) + REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); + else + REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); +} + +/****************************************************************************/ +/* Load RISC processor firmware. */ +/* */ +/* Loads firmware from the file if_bnxfw.h into the scratchpad memory */ +/* associated with a particular processor. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg, + struct fw_info *fw) +{ + u_int32_t offset; + u_int32_t val; + + /* Halt the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val |= cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->mode, val); + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + + /* Load the Text area. */ + offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); + if (fw->text) { + int j; + + for (j = 0; j < (fw->text_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->text[j]); + } + + /* Load the Data area. */ + offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); + if (fw->data) { + int j; + + for (j = 0; j < (fw->data_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->data[j]); + } + + /* Load the SBSS area. */ + offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); + if (fw->sbss) { + int j; + + for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->sbss[j]); + } + + /* Load the BSS area. */ + offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); + if (fw->bss) { + int j; + + for (j = 0; j < (fw->bss_len/4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->bss[j]); + } + + /* Load the Read-Only area. */ + offset = cpu_reg->spad_base + + (fw->rodata_addr - cpu_reg->mips_view_base); + if (fw->rodata) { + int j; + + for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->rodata[j]); + } + + /* Clear the pre-fetch instruction. */ + REG_WR_IND(sc, cpu_reg->inst, 0); + REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); + + /* Start the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val &= ~cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + REG_WR_IND(sc, cpu_reg->mode, val); +} + +/****************************************************************************/ +/* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ +/* */ +/* Loads the firmware for each CPU and starts the CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_init_cpus(struct bnx_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + /* Initialize the RV2P processor. */ + bnx_load_rv2p_fw(sc, bnx_rv2p_proc1, sizeof(bnx_rv2p_proc1), + RV2P_PROC1); + bnx_load_rv2p_fw(sc, bnx_rv2p_proc2, sizeof(bnx_rv2p_proc2), + RV2P_PROC2); + + /* Initialize the RX Processor. */ + cpu_reg.mode = BNX_RXP_CPU_MODE; + cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX_RXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE; + cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK; + cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION; + cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX_RXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx_RXP_b06FwReleaseMajor; + fw.ver_minor = bnx_RXP_b06FwReleaseMinor; + fw.ver_fix = bnx_RXP_b06FwReleaseFix; + fw.start_addr = bnx_RXP_b06FwStartAddr; + + fw.text_addr = bnx_RXP_b06FwTextAddr; + fw.text_len = bnx_RXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx_RXP_b06FwText; + + fw.data_addr = bnx_RXP_b06FwDataAddr; + fw.data_len = bnx_RXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx_RXP_b06FwData; + + fw.sbss_addr = bnx_RXP_b06FwSbssAddr; + fw.sbss_len = bnx_RXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx_RXP_b06FwSbss; + + fw.bss_addr = bnx_RXP_b06FwBssAddr; + fw.bss_len = bnx_RXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx_RXP_b06FwBss; + + fw.rodata_addr = bnx_RXP_b06FwRodataAddr; + fw.rodata_len = bnx_RXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx_RXP_b06FwRodata; + + DBPRINT(sc, BNX_INFO_RESET, "Loading RX firmware.\n"); + bnx_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the TX Processor. */ + cpu_reg.mode = BNX_TXP_CPU_MODE; + cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX_TXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE; + cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK; + cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION; + cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX_TXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx_TXP_b06FwReleaseMajor; + fw.ver_minor = bnx_TXP_b06FwReleaseMinor; + fw.ver_fix = bnx_TXP_b06FwReleaseFix; + fw.start_addr = bnx_TXP_b06FwStartAddr; + + fw.text_addr = bnx_TXP_b06FwTextAddr; + fw.text_len = bnx_TXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx_TXP_b06FwText; + + fw.data_addr = bnx_TXP_b06FwDataAddr; + fw.data_len = bnx_TXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx_TXP_b06FwData; + + fw.sbss_addr = bnx_TXP_b06FwSbssAddr; + fw.sbss_len = bnx_TXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx_TXP_b06FwSbss; + + fw.bss_addr = bnx_TXP_b06FwBssAddr; + fw.bss_len = bnx_TXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx_TXP_b06FwBss; + + fw.rodata_addr = bnx_TXP_b06FwRodataAddr; + fw.rodata_len = bnx_TXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx_TXP_b06FwRodata; + + DBPRINT(sc, BNX_INFO_RESET, "Loading TX firmware.\n"); + bnx_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the TX Patch-up Processor. */ + cpu_reg.mode = BNX_TPAT_CPU_MODE; + cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX_TPAT_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE; + cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK; + cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION; + cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX_TPAT_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx_TPAT_b06FwReleaseMajor; + fw.ver_minor = bnx_TPAT_b06FwReleaseMinor; + fw.ver_fix = bnx_TPAT_b06FwReleaseFix; + fw.start_addr = bnx_TPAT_b06FwStartAddr; + + fw.text_addr = bnx_TPAT_b06FwTextAddr; + fw.text_len = bnx_TPAT_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx_TPAT_b06FwText; + + fw.data_addr = bnx_TPAT_b06FwDataAddr; + fw.data_len = bnx_TPAT_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx_TPAT_b06FwData; + + fw.sbss_addr = bnx_TPAT_b06FwSbssAddr; + fw.sbss_len = bnx_TPAT_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx_TPAT_b06FwSbss; + + fw.bss_addr = bnx_TPAT_b06FwBssAddr; + fw.bss_len = bnx_TPAT_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx_TPAT_b06FwBss; + + fw.rodata_addr = bnx_TPAT_b06FwRodataAddr; + fw.rodata_len = bnx_TPAT_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx_TPAT_b06FwRodata; + + DBPRINT(sc, BNX_INFO_RESET, "Loading TPAT firmware.\n"); + bnx_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the Completion Processor. */ + cpu_reg.mode = BNX_COM_CPU_MODE; + cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA; + cpu_reg.state = BNX_COM_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE; + cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK; + cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BNX_COM_CPU_INSTRUCTION; + cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BNX_COM_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bnx_COM_b06FwReleaseMajor; + fw.ver_minor = bnx_COM_b06FwReleaseMinor; + fw.ver_fix = bnx_COM_b06FwReleaseFix; + fw.start_addr = bnx_COM_b06FwStartAddr; + + fw.text_addr = bnx_COM_b06FwTextAddr; + fw.text_len = bnx_COM_b06FwTextLen; + fw.text_index = 0; + fw.text = bnx_COM_b06FwText; + + fw.data_addr = bnx_COM_b06FwDataAddr; + fw.data_len = bnx_COM_b06FwDataLen; + fw.data_index = 0; + fw.data = bnx_COM_b06FwData; + + fw.sbss_addr = bnx_COM_b06FwSbssAddr; + fw.sbss_len = bnx_COM_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bnx_COM_b06FwSbss; + + fw.bss_addr = bnx_COM_b06FwBssAddr; + fw.bss_len = bnx_COM_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bnx_COM_b06FwBss; + + fw.rodata_addr = bnx_COM_b06FwRodataAddr; + fw.rodata_len = bnx_COM_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bnx_COM_b06FwRodata; + + DBPRINT(sc, BNX_INFO_RESET, "Loading COM firmware.\n"); + bnx_load_cpu_fw(sc, &cpu_reg, &fw); +} + +/****************************************************************************/ +/* Initialize context memory. */ +/* */ +/* Clears the memory associated with each Context ID (CID). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_init_context(struct bnx_softc *sc) +{ + u_int32_t vcid; + + vcid = 96; + while (vcid) { + u_int32_t vcid_addr, pcid_addr, offset; + + vcid--; + + vcid_addr = GET_CID_ADDR(vcid); + pcid_addr = vcid_addr; + + REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); + REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); + + /* Zero out the context. */ + for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) + CTX_WR(sc, 0x00, offset, 0); + + REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); + REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); + } +} + +/****************************************************************************/ +/* Fetch the permanent MAC address of the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_get_mac_addr(struct bnx_softc *sc) +{ + u_int32_t mac_lo = 0, mac_hi = 0; + + /* + * The NetXtreme II bootcode populates various NIC + * power-on and runtime configuration items in a + * shared memory area. The factory configured MAC + * address is available from both NVRAM and the + * shared memory area so we'll read the value from + * shared memory for speed. + */ + + mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER); + mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER); + + if ((mac_lo == 0) && (mac_hi == 0)) { + BNX_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", + __FILE__, __LINE__); + } else { + sc->eaddr[0] = (u_char)(mac_hi >> 8); + sc->eaddr[1] = (u_char)(mac_hi >> 0); + sc->eaddr[2] = (u_char)(mac_lo >> 24); + sc->eaddr[3] = (u_char)(mac_lo >> 16); + sc->eaddr[4] = (u_char)(mac_lo >> 8); + sc->eaddr[5] = (u_char)(mac_lo >> 0); + } + + DBPRINT(sc, BNX_INFO, "Permanent Ethernet address = " + "%s\n", ether_sprintf(sc->eaddr)); +} + +/****************************************************************************/ +/* Program the MAC address. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_set_mac_addr(struct bnx_softc *sc) +{ + u_int32_t val; + u_int8_t *mac_addr = LLADDR(sc->ethercom.ec_if.if_sadl); + + DBPRINT(sc, BNX_INFO, "Setting Ethernet address = " + "%s\n", ether_sprintf(sc->eaddr)); + + val = (mac_addr[0] << 8) | mac_addr[1]; + + REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); + + val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); +} + +/****************************************************************************/ +/* Stop the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_stop(struct bnx_softc *sc) +{ + struct ifnet *ifp = &sc->ethercom.ec_if; + struct ifmedia_entry *ifm; + struct mii_data *mii = NULL; + int mtmp, itmp; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + mii = &sc->bnx_mii; + + callout_stop(&sc->bnx_timeout); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + /* Disable the transmit/receive blocks. */ + REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); + REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); + DELAY(20); + + bnx_disable_intr(sc); + + /* Tell firmware that the driver is going away. */ + bnx_reset(sc, BNX_DRV_MSG_CODE_SUSPEND_NO_WOL); + + /* Free the RX lists. */ + bnx_free_rx_chain(sc); + + /* Free TX buffers. */ + bnx_free_tx_chain(sc); + + /* + * Isolate/power down the PHY, but leave the media selection + * unchanged so that things will be put back to normal when + * we bring the interface back up. + */ + + itmp = ifp->if_flags; + ifp->if_flags |= IFF_UP; + /* + * If we are called from bnx_detach(), mii is already NULL. + */ + if (mii != NULL) { + ifm = mii->mii_media.ifm_cur; + mtmp = ifm->ifm_media; + ifm->ifm_media = IFM_ETHER|IFM_NONE; + mii_mediachg(mii); + ifm->ifm_media = mtmp; + } + + ifp->if_flags = itmp; + ifp->if_timer = 0; + + sc->bnx_link = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + +} + +int +bnx_reset(struct bnx_softc *sc, u_int32_t reset_code) +{ + u_int32_t val; + int i, rc = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Wait for pending PCI transactions to complete. */ + REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, + BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | + BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); + val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS); + DELAY(5); + + /* Assume bootcode is running. */ + sc->bnx_fw_timed_out = 0; + + /* Give the firmware a chance to prepare for the reset. */ + rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT0 | reset_code); + if (rc) + goto bnx_reset_exit; + + /* Set a firmware reminder that this is a soft reset. */ + REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE, + BNX_DRV_RESET_SIGNATURE_MAGIC); + + /* Dummy read to force the chip to complete all current transactions. */ + val = REG_RD(sc, BNX_MISC_ID); + + /* Chip reset. */ + val = BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); + + /* Allow up to 30us for reset to complete. */ + for (i = 0; i < 10; i++) { + val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG); + if ((val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) + break; + + DELAY(10); + } + + /* Check that reset completed successfully. */ + if (val & (BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { + BNX_PRINTF(sc, "%s(%d): Reset failed!\n", __FILE__, __LINE__); + rc = EBUSY; + goto bnx_reset_exit; + } + + /* Make sure byte swapping is properly configured. */ + val = REG_RD(sc, BNX_PCI_SWAP_DIAG0); + if (val != 0x01020304) { + BNX_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", + __FILE__, __LINE__); + rc = ENODEV; + goto bnx_reset_exit; + } + + /* Just completed a reset, assume that firmware is running again. */ + sc->bnx_fw_timed_out = 0; + + /* Wait for the firmware to finish its initialization. */ + rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT1 | reset_code); + if (rc) + BNX_PRINTF(sc, "%s(%d): Firmware did not complete " + "initialization!\n", __FILE__, __LINE__); + +bnx_reset_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return (rc); +} + +int +bnx_chipinit(struct bnx_softc *sc) +{ + struct pci_attach_args *pa = &(sc->bnx_pa); + u_int32_t val; + int rc = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Make sure the interrupt is not active. */ + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); + + /* Initialize DMA byte/word swapping, configure the number of DMA */ + /* channels and PCI clock compensation delay. */ + val = BNX_DMA_CONFIG_DATA_BYTE_SWAP | + BNX_DMA_CONFIG_DATA_WORD_SWAP | +#if BYTE_ORDER == BIG_ENDIAN + BNX_DMA_CONFIG_CNTL_BYTE_SWAP | +#endif + BNX_DMA_CONFIG_CNTL_WORD_SWAP | + DMA_READ_CHANS << 12 | + DMA_WRITE_CHANS << 16; + + val |= (0x2 << 20) | BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY; + + if ((sc->bnx_flags & BNX_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) + val |= BNX_DMA_CONFIG_PCI_FAST_CLK_CMP; + + /* + * This setting resolves a problem observed on certain Intel PCI + * chipsets that cannot handle multiple outstanding DMA operations. + * See errata E9_5706A1_65. + */ + if ((BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && + (BNX_CHIP_ID(sc) != BNX_CHIP_ID_5706_A0) && + !(sc->bnx_flags & BNX_PCIX_FLAG)) + val |= BNX_DMA_CONFIG_CNTL_PING_PONG_DMA; + + REG_WR(sc, BNX_DMA_CONFIG, val); + + /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ + if (sc->bnx_flags & BNX_PCIX_FLAG) { + u_int16_t nval; + + nval = pci_conf_read(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD); + pci_conf_write(pa->pa_pc, pa->pa_tag, BNX_PCI_PCIX_CMD, + nval & ~0x2); + } + + /* Enable the RX_V2P and Context state machines before access. */ + REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, + BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + + /* Initialize context mapping and zero out the quick contexts. */ + bnx_init_context(sc); + + /* Initialize the on-boards CPUs */ + bnx_init_cpus(sc); + + /* Prepare NVRAM for access. */ + if (bnx_init_nvram(sc)) { + rc = ENODEV; + goto bnx_chipinit_exit; + } + + /* Set the kernel bypass block size */ + val = REG_RD(sc, BNX_MQ_CONFIG); + val &= ~BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE; + val |= BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; + REG_WR(sc, BNX_MQ_CONFIG, val); + + val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); + REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); + REG_WR(sc, BNX_MQ_KNL_WIND_END, val); + + val = (BCM_PAGE_BITS - 8) << 24; + REG_WR(sc, BNX_RV2P_CONFIG, val); + + /* Configure page size. */ + val = REG_RD(sc, BNX_TBDR_CONFIG); + val &= ~BNX_TBDR_CONFIG_PAGE_SIZE; + val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; + REG_WR(sc, BNX_TBDR_CONFIG, val); + +bnx_chipinit_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return(rc); +} + +/****************************************************************************/ +/* Initialize the controller in preparation to send/receive traffic. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_blockinit(struct bnx_softc *sc) +{ + u_int32_t reg, val; + int rc = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Load the hardware default MAC address. */ + bnx_set_mac_addr(sc); + + /* Set the Ethernet backoff seed value */ + val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + + (sc->eaddr[3]) + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); + REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); + + sc->last_status_idx = 0; + sc->rx_mode = BNX_EMAC_RX_MODE_SORT_MODE; + + /* Set up link change interrupt generation. */ + REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); + + /* Program the physical address of the status block. */ + REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); + REG_WR(sc, BNX_HC_STATUS_ADDR_H, + (u_int32_t)((u_int64_t)sc->status_block_paddr >> 32)); + + /* Program the physical address of the statistics block. */ + REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, + (u_int32_t)(sc->stats_block_paddr)); + REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, + (u_int32_t)((u_int64_t)sc->stats_block_paddr >> 32)); + + /* Program various host coalescing parameters. */ + REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int + << 16) | sc->bnx_tx_quick_cons_trip); + REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int + << 16) | sc->bnx_rx_quick_cons_trip); + REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | + sc->bnx_comp_prod_trip); + REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | + sc->bnx_tx_ticks); + REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | + sc->bnx_rx_ticks); + REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | + sc->bnx_com_ticks); + REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | + sc->bnx_cmd_ticks); + REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); + REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ + REG_WR(sc, BNX_HC_CONFIG, + (BNX_HC_CONFIG_RX_TMR_MODE | BNX_HC_CONFIG_TX_TMR_MODE | + BNX_HC_CONFIG_COLLECT_STATS)); + + /* Clear the internal statistics counters. */ + REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); + + /* Verify that bootcode is running. */ + reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE); + + DBRUNIF(DB_RANDOMTRUE(bnx_debug_bootcode_running_failure), + BNX_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", + __FILE__, __LINE__); reg = 0); + + if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) != + BNX_DEV_INFO_SIGNATURE_MAGIC) { + BNX_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " + "Expected: 08%08X\n", __FILE__, __LINE__, + (reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK), + BNX_DEV_INFO_SIGNATURE_MAGIC); + rc = ENODEV; + goto bnx_blockinit_exit; + } + + /* Check if any management firmware is running. */ + reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE); + if (reg & (BNX_PORT_FEATURE_ASF_ENABLED | + BNX_PORT_FEATURE_IMD_ENABLED)) { + DBPRINT(sc, BNX_INFO, "Management F/W Enabled.\n"); + sc->bnx_flags |= BNX_MFW_ENABLE_FLAG; + } + + sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base + + BNX_DEV_INFO_BC_REV); + + DBPRINT(sc, BNX_INFO, "bootcode rev = 0x%08X\n", sc->bnx_fw_ver); + + /* Allow bootcode to apply any additional fixes before enabling MAC. */ + rc = bnx_fw_sync(sc, BNX_DRV_MSG_DATA_WAIT2 | BNX_DRV_MSG_CODE_RESET); + + /* Enable link state change interrupt generation. */ + REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); + + /* Enable all remaining blocks in the MAC. */ + REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); + REG_RD(sc, BNX_MISC_ENABLE_SET_BITS); + DELAY(20); + +bnx_blockinit_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return (rc); +} + +/****************************************************************************/ +/* Encapsulate an mbuf cluster into the rx_bd chain. */ +/* */ +/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ +/* This routine will map an mbuf cluster into 1 or more rx_bd's as */ +/* necessary. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_get_buf(struct bnx_softc *sc, struct mbuf *m, u_int16_t *prod, + u_int16_t *chain_prod, u_int32_t *prod_bseq) +{ + bus_dmamap_t map; + struct mbuf *m_new = NULL; + struct rx_bd *rxbd; + int i, rc = 0; + u_int32_t addr; +#ifdef BNX_DEBUG + u_int16_t debug_chain_prod = *chain_prod; +#endif + + DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", + __FUNCTION__); + + /* Make sure the inputs are valid. */ + DBRUNIF((*chain_prod > MAX_RX_BD), + aprint_error("%s: RX producer out of range: 0x%04X > 0x%04X\n", + sc->bnx_dev.dv_xname, *chain_prod, (u_int16_t) MAX_RX_BD)); + + DBPRINT(sc, BNX_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = " + "0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, + *prod_bseq); + + if (m == NULL) { + DBRUNIF(DB_RANDOMTRUE(bnx_debug_mbuf_allocation_failure), + BNX_PRINTF(sc, "Simulating mbuf allocation failure.\n"); + + sc->mbuf_alloc_failed++; + rc = ENOBUFS; + goto bnx_get_buf_exit); + + /* This is a new mbuf allocation. */ + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + DBPRINT(sc, BNX_WARN, + "%s(%d): RX mbuf header allocation failed!\n", + __FILE__, __LINE__); + + DBRUNIF(1, sc->mbuf_alloc_failed++); + + rc = ENOBUFS; + goto bnx_get_buf_exit; + } + + DBRUNIF(1, sc->rx_mbuf_alloc++); + MEXTMALLOC(m_new, sc->mbuf_alloc_size, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + DBPRINT(sc, BNX_WARN, + "%s(%d): RX mbuf chain allocation failed!\n", + __FILE__, __LINE__); + + m_freem(m_new); + + DBRUNIF(1, sc->rx_mbuf_alloc--); + DBRUNIF(1, sc->mbuf_alloc_failed++); + + rc = ENOBUFS; + goto bnx_get_buf_exit; + } + + m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; + } else { + m_new = m; + m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; + m_new->m_data = m_new->m_ext.ext_buf; + } + + /* Map the mbuf cluster into device memory. */ + map = sc->rx_mbuf_map[*chain_prod]; + if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_new, BUS_DMA_NOWAIT)) { + BNX_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", + __FILE__, __LINE__); + + m_freem(m_new); + + DBRUNIF(1, sc->rx_mbuf_alloc--); + + rc = ENOBUFS; + goto bnx_get_buf_exit; + } + bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, + BUS_DMASYNC_PREREAD); + + /* Watch for overflow. */ + DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), + aprint_error("%s: Too many free rx_bd (0x%04X > 0x%04X)!\n", + sc->bnx_dev.dv_xname, + sc->free_rx_bd, (u_int16_t) USABLE_RX_BD)); + + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + + /* Setup the rx_bd for the first segment. */ + rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; + + addr = (u_int32_t)(map->dm_segs[0].ds_addr); + rxbd->rx_bd_haddr_lo = htole32(addr); + addr = (u_int32_t)((u_int64_t)map->dm_segs[0].ds_addr >> 32); + rxbd->rx_bd_haddr_hi = htole32(addr); + rxbd->rx_bd_len = htole32(map->dm_segs[0].ds_len); + rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); + *prod_bseq += map->dm_segs[0].ds_len; + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], + sizeof(struct rx_bd) * RX_IDX(*chain_prod), sizeof(struct rx_bd), + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + for (i = 1; i < map->dm_nsegs; i++) { + *prod = NEXT_RX_BD(*prod); + *chain_prod = RX_CHAIN_IDX(*prod); + + rxbd = + &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; + + addr = (u_int32_t)(map->dm_segs[i].ds_addr); + rxbd->rx_bd_haddr_lo = htole32(addr); + addr = (u_int32_t)((u_int64_t)map->dm_segs[i].ds_addr >> 32); + rxbd->rx_bd_haddr_hi = htole32(addr); + rxbd->rx_bd_len = htole32(map->dm_segs[i].ds_len); + rxbd->rx_bd_flags = 0; + *prod_bseq += map->dm_segs[i].ds_len; + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], + sizeof(struct rx_bd) * RX_IDX(*chain_prod), + sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_bd_chain_map[RX_PAGE(*chain_prod)], + sizeof(struct rx_bd) * RX_IDX(*chain_prod), + sizeof(struct rx_bd), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* Save the mbuf and update our counter. */ + sc->rx_mbuf_ptr[*chain_prod] = m_new; + sc->free_rx_bd -= map->dm_nsegs; + + DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, + map->dm_nsegs)); + + DBPRINT(sc, BNX_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod " + "= 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, *prod, + *chain_prod, *prod_bseq); + +bnx_get_buf_exit: + DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Exiting %s()\n", + __FUNCTION__); + + return(rc); +} + +/****************************************************************************/ +/* Allocate memory and initialize the TX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_init_tx_chain(struct bnx_softc *sc) +{ + struct tx_bd *txbd; + u_int32_t val, addr; + int i, rc = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Set the initial TX producer/consumer indices. */ + sc->tx_prod = 0; + sc->tx_cons = 0; + sc->tx_prod_bseq = 0; + sc->used_tx_bd = 0; + DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); + + /* + * The NetXtreme II supports a linked-list structure called + * a Buffer Descriptor Chain (or BD chain). A BD chain + * consists of a series of 1 or more chain pages, each of which + * consists of a fixed number of BD entries. + * The last BD entry on each page is a pointer to the next page + * in the chain, and the last pointer in the BD chain + * points back to the beginning of the chain. + */ + + /* Set the TX next pointer chain entries. */ + for (i = 0; i < TX_PAGES; i++) { + int j; + + txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (TX_PAGES - 1)) + j = 0; + else + j = i + 1; + + addr = (u_int32_t)(sc->tx_bd_chain_paddr[j]); + txbd->tx_bd_haddr_lo = htole32(addr); + addr = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[j] >> 32); + txbd->tx_bd_haddr_hi = htole32(addr); + bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, + BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); + } + + /* + * Initialize the context ID for an L2 TX chain. + */ + val = BNX_L2CTX_TYPE_TYPE_L2; + val |= BNX_L2CTX_TYPE_SIZE_L2; + CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TYPE, val); + + val = BNX_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_CMD_TYPE, val); + + /* Point the hardware to the first page in the chain. */ + val = (u_int32_t)((u_int64_t)sc->tx_bd_chain_paddr[0] >> 32); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_HI, val); + val = (u_int32_t)(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BNX_L2CTX_TBDR_BHADDR_LO, val); + + DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_chain(sc, 0, TOTAL_TX_BD)); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return(rc); +} + +/****************************************************************************/ +/* Free memory and clear the TX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_free_tx_chain(struct bnx_softc *sc) +{ + int i; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (sc->tx_mbuf_ptr[i] != NULL) { + if (sc->tx_mbuf_map != NULL) + bus_dmamap_sync(sc->bnx_dmatag, + sc->tx_mbuf_map[i], 0, + sc->tx_mbuf_map[i]->dm_mapsize, + BUS_DMASYNC_POSTWRITE); + m_freem(sc->tx_mbuf_ptr[i]); + sc->tx_mbuf_ptr[i] = NULL; + DBRUNIF(1, sc->tx_mbuf_alloc--); + } + } + + /* Clear each TX chain page. */ + for (i = 0; i < TX_PAGES; i++) { + bzero((char *)sc->tx_bd_chain[i], BNX_TX_CHAIN_PAGE_SZ); + bus_dmamap_sync(sc->bnx_dmatag, sc->tx_bd_chain_map[i], 0, + BNX_TX_CHAIN_PAGE_SZ, BUS_DMASYNC_PREWRITE); + } + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->tx_mbuf_alloc), + aprint_error("%s: Memory leak! Lost %d mbufs from tx chain!\n", + sc->bnx_dev.dv_xname, sc->tx_mbuf_alloc)); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); +} + +/****************************************************************************/ +/* Allocate memory and initialize the RX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_init_rx_chain(struct bnx_softc *sc) +{ + struct rx_bd *rxbd; + int i, rc = 0; + u_int16_t prod, chain_prod; + u_int32_t prod_bseq, val, addr; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Initialize the RX producer and consumer indices. */ + sc->rx_prod = 0; + sc->rx_cons = 0; + sc->rx_prod_bseq = 0; + sc->free_rx_bd = BNX_RX_SLACK_SPACE; + DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); + + /* Initialize the RX next pointer chain entries. */ + for (i = 0; i < RX_PAGES; i++) { + int j; + + rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (RX_PAGES - 1)) + j = 0; + else + j = i + 1; + + /* Setup the chain page pointers. */ + addr = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[j] >> 32); + rxbd->rx_bd_haddr_hi = htole32(addr); + addr = (u_int32_t)(sc->rx_bd_chain_paddr[j]); + rxbd->rx_bd_haddr_lo = htole32(addr); + bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], + 0, BNX_RX_CHAIN_PAGE_SZ, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + /* Initialize the context ID for an L2 RX chain. */ + val = BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; + val |= BNX_L2CTX_CTX_TYPE_SIZE_L2; + val |= 0x02 << 8; + CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_CTX_TYPE, val); + + /* Point the hardware to the first page in the chain. */ + val = (u_int32_t)((u_int64_t)sc->rx_bd_chain_paddr[0] >> 32); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_HI, val); + val = (u_int32_t)(sc->rx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BNX_L2CTX_NX_BDHADDR_LO, val); + + /* Allocate mbuf clusters for the rx_bd chain. */ + prod = prod_bseq = 0; + while (prod < BNX_RX_SLACK_SPACE) { + chain_prod = RX_CHAIN_IDX(prod); + if (bnx_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { + BNX_PRINTF(sc, + "Error filling RX chain: rx_bd[0x%04X]!\n", + chain_prod); + rc = ENOBUFS; + break; + } + prod = NEXT_RX_BD(prod); + } + + /* Save the RX chain producer index. */ + sc->rx_prod = prod; + sc->rx_prod_bseq = prod_bseq; + + for (i = 0; i < RX_PAGES; i++) + bus_dmamap_sync(sc->bnx_dmatag, sc->rx_bd_chain_map[i], 0, + sc->rx_bd_chain_map[i]->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* Tell the chip about the waiting rx_bd's. */ + REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); + REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); + + DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_chain(sc, 0, TOTAL_RX_BD)); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + return(rc); +} + +/****************************************************************************/ +/* Free memory and clear the RX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_free_rx_chain(struct bnx_softc *sc) +{ + int i; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + /* Free any mbufs still in the RX mbuf chain. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (sc->rx_mbuf_ptr[i] != NULL) { + if (sc->rx_mbuf_map[i] != NULL) + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_mbuf_map[i], 0, + sc->rx_mbuf_map[i]->dm_mapsize, + BUS_DMASYNC_POSTREAD); + m_freem(sc->rx_mbuf_ptr[i]); + sc->rx_mbuf_ptr[i] = NULL; + DBRUNIF(1, sc->rx_mbuf_alloc--); + } + } + + /* Clear each RX chain page. */ + for (i = 0; i < RX_PAGES; i++) + bzero((char *)sc->rx_bd_chain[i], BNX_RX_CHAIN_PAGE_SZ); + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->rx_mbuf_alloc), + aprint_error("%s: Memory leak! Lost %d mbufs from rx chain!\n", + sc->bnx_dev.dv_xname, sc->rx_mbuf_alloc)); + + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); +} + +/****************************************************************************/ +/* Set media options. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_ifmedia_upd(struct ifnet *ifp) +{ + struct bnx_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + int rc = 0; + + sc = ifp->if_softc; + ifm = &sc->bnx_ifmedia; + + /* DRC - ToDo: Add SerDes support. */ + + mii = &sc->bnx_mii; + sc->bnx_link = 0; + if (mii->mii_instance) { + struct mii_softc *miisc; + for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; + miisc = LIST_NEXT(miisc, mii_list)) + mii_phy_reset(miisc); + } + mii_mediachg(mii); + + return(rc); +} + +/****************************************************************************/ +/* Reports current media status. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bnx_softc *sc; + struct mii_data *mii; + int s; + + sc = ifp->if_softc; + + s = splnet(); + + mii = &sc->bnx_mii; + + /* DRC - ToDo: Add SerDes support. */ + + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + splx(s); +} + +/****************************************************************************/ +/* Handles PHY generated interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_phy_intr(struct bnx_softc *sc) +{ + u_int32_t new_link_state, old_link_state; + + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + new_link_state = sc->status_block->status_attn_bits & + STATUS_ATTN_BITS_LINK_STATE; + old_link_state = sc->status_block->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE; + + /* Handle any changes if the link state has changed. */ + if (new_link_state != old_link_state) { + DBRUN(BNX_VERBOSE_INTR, bnx_dump_status_block(sc)); + + sc->bnx_link = 0; + callout_stop(&sc->bnx_timeout); + bnx_tick(sc); + + /* Update the status_attn_bits_ack field in the status block. */ + if (new_link_state) { + REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, + STATUS_ATTN_BITS_LINK_STATE); + DBPRINT(sc, BNX_INFO, "Link is now UP.\n"); + } else { + REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, + STATUS_ATTN_BITS_LINK_STATE); + DBPRINT(sc, BNX_INFO, "Link is now DOWN.\n"); + } + } + + /* Acknowledge the link change interrupt. */ + REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); +} + +/****************************************************************************/ +/* Handles received frame interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_rx_intr(struct bnx_softc *sc) +{ + struct status_block *sblk = sc->status_block; + struct ifnet *ifp = &sc->ethercom.ec_if; + u_int16_t hw_cons, sw_cons, sw_chain_cons; + u_int16_t sw_prod, sw_chain_prod; + u_int32_t sw_prod_bseq; + struct l2_fhdr *l2fhdr; + int i; + + DBRUNIF(1, sc->rx_interrupts++); + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + + /* Prepare the RX chain pages to be accessed by the host CPU. */ + for (i = 0; i < RX_PAGES; i++) + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_bd_chain_map[i], 0, + sc->rx_bd_chain_map[i]->dm_mapsize, + BUS_DMASYNC_POSTWRITE); + + /* Get the hardware's view of the RX consumer index. */ + hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; + if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) + hw_cons++; + + /* Get working copies of the driver's view of the RX indices. */ + sw_cons = sc->rx_cons; + sw_prod = sc->rx_prod; + sw_prod_bseq = sc->rx_prod_bseq; + + DBPRINT(sc, BNX_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " + "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", + __FUNCTION__, sw_prod, sw_cons, sw_prod_bseq); + + /* Prevent speculative reads from getting ahead of the status block. */ + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + + /* + * Scan through the receive chain as long + * as there is work to do. + */ + while (sw_cons != hw_cons) { + struct mbuf *m; + struct rx_bd *rxbd; + unsigned int len; + u_int32_t status; + + /* Convert the producer/consumer indices to an actual + * rx_bd index. + */ + sw_chain_cons = RX_CHAIN_IDX(sw_cons); + sw_chain_prod = RX_CHAIN_IDX(sw_prod); + + /* Get the used rx_bd. */ + rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; + sc->free_rx_bd++; + + DBRUN(BNX_VERBOSE_RECV, aprint_error("%s(): ", __FUNCTION__); + bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); + + /* The mbuf is stored with the last rx_bd entry of a packet. */ + if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { + /* Validate that this is the last rx_bd. */ + DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), + aprint_error("%s: Unexpected mbuf found in " + "rx_bd[0x%04X]!\n", sc->bnx_dev.dv_xname, + sw_chain_cons); + bnx_breakpoint(sc)); + + /* DRC - ToDo: If the received packet is small, say less + * than 128 bytes, allocate a new mbuf here, + * copy the data to that mbuf, and recycle + * the mapped jumbo frame. + */ + + /* Unmap the mbuf from DMA space. */ + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_mbuf_map[sw_chain_cons], 0, + sc->rx_mbuf_map[sw_chain_cons]->dm_mapsize, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bnx_dmatag, + sc->rx_mbuf_map[sw_chain_cons]); + + /* Remove the mbuf from the driver's chain. */ + m = sc->rx_mbuf_ptr[sw_chain_cons]; + sc->rx_mbuf_ptr[sw_chain_cons] = NULL; + + /* + * Frames received on the NetXteme II are prepended + * with the l2_fhdr structure which provides status + * information about the received frame (including + * VLAN tags and checksum info) and are also + * automatically adjusted to align the IP header + * (i.e. two null bytes are inserted before the + * Ethernet header). + */ + l2fhdr = mtod(m, struct l2_fhdr *); + + len = l2fhdr->l2_fhdr_pkt_len; + status = l2fhdr->l2_fhdr_status; + + DBRUNIF(DB_RANDOMTRUE(bnx_debug_l2fhdr_status_check), + aprint_error("Simulating l2_fhdr status error.\n"); + status = status | L2_FHDR_ERRORS_PHY_DECODE); + + /* Watch for unusual sized frames. */ + DBRUNIF(((len < BNX_MIN_MTU) || + (len > BNX_MAX_JUMBO_ETHER_MTU_VLAN)), + aprint_error("%s: Unusual frame size found. " + "Min(%d), Actual(%d), Max(%d)\n", + sc->bnx_dev.dv_xname, (int)BNX_MIN_MTU, len, + (int) BNX_MAX_JUMBO_ETHER_MTU_VLAN); + + bnx_dump_mbuf(sc, m); + bnx_breakpoint(sc)); + + len -= ETHER_CRC_LEN; + + /* Check the received frame for errors. */ + if ((status & (L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | + L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | + L2_FHDR_ERRORS_GIANT_FRAME)) || + len < (BNX_MIN_MTU - ETHER_CRC_LEN) || + len > + (BNX_MAX_JUMBO_ETHER_MTU_VLAN - ETHER_CRC_LEN)) { + ifp->if_ierrors++; + DBRUNIF(1, sc->l2fhdr_status_errors++); + + /* Reuse the mbuf for a new frame. */ + if (bnx_get_buf(sc, m, &sw_prod, + &sw_chain_prod, &sw_prod_bseq)) { + DBRUNIF(1, bnx_breakpoint(sc)); + panic("%s: Can't reuse RX mbuf!\n", + sc->bnx_dev.dv_xname); + } + goto bnx_rx_int_next_rx; + } + + /* + * Get a new mbuf for the rx_bd. If no new + * mbufs are available then reuse the current mbuf, + * log an ierror on the interface, and generate + * an error in the system log. + */ + if (bnx_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, + &sw_prod_bseq)) { + DBRUN(BNX_WARN, BNX_PRINTF(sc, "Failed to allocate " + "new mbuf, incoming frame dropped!\n")); + + ifp->if_ierrors++; + + /* Try and reuse the exisitng mbuf. */ + if (bnx_get_buf(sc, m, &sw_prod, + &sw_chain_prod, &sw_prod_bseq)) { + DBRUNIF(1, bnx_breakpoint(sc)); + panic("%s: Double mbuf allocation " + "failure!", sc->bnx_dev.dv_xname); + } + goto bnx_rx_int_next_rx; + } + + /* Skip over the l2_fhdr when passing the data up + * the stack. + */ + m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); + + /* Adjust the pckt length to match the received data. */ + m->m_pkthdr.len = m->m_len = len; + + /* Send the packet to the appropriate interface. */ + m->m_pkthdr.rcvif = ifp; + + DBRUN(BNX_VERBOSE_RECV, + struct ether_header *eh; + eh = mtod(m, struct ether_header *); + aprint_error("%s: to: %s, from: %s, type: 0x%04X\n", + __FUNCTION__, ether_sprintf(eh->ether_dhost), + ether_sprintf(eh->ether_shost), + htons(eh->ether_type))); + + /* Validate the checksum. */ + + /* Check for an IP datagram. */ + if (status & L2_FHDR_STATUS_IP_DATAGRAM) { + /* Check if the IP checksum is valid. */ + if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) + == 0) + m->m_pkthdr.csum_flags |= + M_CSUM_IPv4; +#ifdef BNX_DEBUG + else + DBPRINT(sc, BNX_WARN_SEND, + "%s(): Invalid IP checksum " + "= 0x%04X!\n", + __FUNCTION__, + l2fhdr->l2_fhdr_ip_xsum + ); +#endif + } + + /* Check for a valid TCP/UDP frame. */ + if (status & (L2_FHDR_STATUS_TCP_SEGMENT | + L2_FHDR_STATUS_UDP_DATAGRAM)) { + /* Check for a good TCP/UDP checksum. */ + if ((status & + (L2_FHDR_ERRORS_TCP_XSUM | + L2_FHDR_ERRORS_UDP_XSUM)) == 0) { + m->m_pkthdr.csum_flags |= + M_CSUM_TCPv4 | + M_CSUM_UDPv4; + } else { + DBPRINT(sc, BNX_WARN_SEND, + "%s(): Invalid TCP/UDP " + "checksum = 0x%04X!\n", + __FUNCTION__, + l2fhdr->l2_fhdr_tcp_udp_xsum); + } + } + + /* + * If we received a packet with a vlan tag, + * attach that information to the packet. + */ + if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { +#if 0 + struct ether_vlan_header vh; + + DBPRINT(sc, BNX_VERBOSE_SEND, + "%s(): VLAN tag = 0x%04X\n", + __FUNCTION__, + l2fhdr->l2_fhdr_vlan_tag); + + if (m->m_pkthdr.len < ETHER_HDR_LEN) { + m_freem(m); + goto bnx_rx_int_next_rx; + } + m_copydata(m, 0, ETHER_HDR_LEN, (caddr_t)&vh); + vh.evl_proto = vh.evl_encap_proto; + vh.evl_tag = l2fhdr->l2_fhdr_vlan_tag >> 16; + vh.evl_encap_proto = htons(ETHERTYPE_VLAN); + m_adj(m, ETHER_HDR_LEN); + if ((m = m_prepend(m, sizeof(vh), M_DONTWAIT)) == NULL) + goto bnx_rx_int_next_rx; + m->m_pkthdr.len += sizeof(vh); + if (m->m_len < sizeof(vh) && + (m = m_pullup(m, sizeof(vh))) == NULL) + goto bnx_rx_int_next_rx; + m_copyback(m, 0, sizeof(vh), &vh); +#else + VLAN_INPUT_TAG(ifp, m, + l2fhdr->l2_fhdr_vlan_tag >> 16, + goto bnx_rx_int_next_rx); +#endif + } + +#if NBPFILTER > 0 + /* + * Handle BPF listeners. Let the BPF + * user see the packet. + */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m); +#endif + + /* Pass the mbuf off to the upper layers. */ + ifp->if_ipackets++; + DBPRINT(sc, BNX_VERBOSE_RECV, + "%s(): Passing received frame up.\n", __FUNCTION__); + //ether_input_mbuf(ifp, m); + (*ifp->if_input)(ifp, m); + DBRUNIF(1, sc->rx_mbuf_alloc--); + +bnx_rx_int_next_rx: + sw_prod = NEXT_RX_BD(sw_prod); + } + + sw_cons = NEXT_RX_BD(sw_cons); + + /* Refresh hw_cons to see if there's new work */ + if (sw_cons == hw_cons) { + hw_cons = sc->hw_rx_cons = + sblk->status_rx_quick_consumer_index0; + if ((hw_cons & USABLE_RX_BD_PER_PAGE) == + USABLE_RX_BD_PER_PAGE) + hw_cons++; + } + + /* Prevent speculative reads from getting ahead of + * the status block. + */ + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + } + + for (i = 0; i < RX_PAGES; i++) + bus_dmamap_sync(sc->bnx_dmatag, + sc->rx_bd_chain_map[i], 0, + sc->rx_bd_chain_map[i]->dm_mapsize, + BUS_DMASYNC_PREWRITE); + + sc->rx_cons = sw_cons; + sc->rx_prod = sw_prod; + sc->rx_prod_bseq = sw_prod_bseq; + + REG_WR16(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BDIDX, sc->rx_prod); + REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); + + DBPRINT(sc, BNX_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " + "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", + __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); +} + +/****************************************************************************/ +/* Handles transmit completion interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_tx_intr(struct bnx_softc *sc) +{ + struct status_block *sblk = sc->status_block; + struct ifnet *ifp = &sc->ethercom.ec_if; + u_int16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; + + DBRUNIF(1, sc->tx_interrupts++); + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + + /* Get the hardware's view of the TX consumer index. */ + hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; + + /* Skip to the next entry if this is a chain page pointer. */ + if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) + hw_tx_cons++; + + sw_tx_cons = sc->tx_cons; + + /* Prevent speculative reads from getting ahead of the status block. */ + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* Cycle through any completed TX chain page entries. */ + while (sw_tx_cons != hw_tx_cons) { +#ifdef BNX_DEBUG + struct tx_bd *txbd = NULL; +#endif + sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); + + DBPRINT(sc, BNX_INFO_SEND, "%s(): hw_tx_cons = 0x%04X, " + "sw_tx_cons = 0x%04X, sw_tx_chain_cons = 0x%04X\n", + __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); + + DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), + aprint_error("%s: TX chain consumer out of range! " + " 0x%04X > 0x%04X\n", sc->bnx_dev.dv_xname, + sw_tx_chain_cons, (int)MAX_TX_BD); bnx_breakpoint(sc)); + + DBRUNIF(1, txbd = &sc->tx_bd_chain + [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); + + DBRUNIF((txbd == NULL), + aprint_error("%s: Unexpected NULL tx_bd[0x%04X]!\n", + sc->bnx_dev.dv_xname, sw_tx_chain_cons); + bnx_breakpoint(sc)); + + DBRUN(BNX_INFO_SEND, aprint_debug("%s: ", __FUNCTION__); + bnx_dump_txbd(sc, sw_tx_chain_cons, txbd)); + + /* + * Free the associated mbuf. Remember + * that only the last tx_bd of a packet + * has an mbuf pointer and DMA map. + */ + if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { + /* Validate that this is the last tx_bd. */ + DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & + TX_BD_FLAGS_END)), + aprint_error("%s: tx_bd END flag not set but " + "txmbuf == NULL!\n", sc->bnx_dev.dv_xname); + bnx_breakpoint(sc)); + + DBRUN(BNX_INFO_SEND, + aprint_debug("%s: Unloading map/freeing mbuf " + "from tx_bd[0x%04X]\n", + __FUNCTION__, sw_tx_chain_cons)); + + /* Unmap the mbuf. */ + bus_dmamap_unload(sc->bnx_dmatag, + sc->tx_mbuf_map[sw_tx_chain_cons]); + + /* Free the mbuf. */ + m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); + sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; + DBRUNIF(1, sc->tx_mbuf_alloc--); + + ifp->if_opackets++; + } + + sc->used_tx_bd--; + sw_tx_cons = NEXT_TX_BD(sw_tx_cons); + + /* Refresh hw_cons to see if there's new work. */ + hw_tx_cons = sc->hw_tx_cons = + sblk->status_tx_quick_consumer_index0; + if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == + USABLE_TX_BD_PER_PAGE) + hw_tx_cons++; + + /* Prevent speculative reads from getting ahead of + * the status block. + */ + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + } + + /* Clear the TX timeout timer. */ + ifp->if_timer = 0; + + /* Clear the tx hardware queue full flag. */ + if ((sc->used_tx_bd + BNX_TX_SLACK_SPACE) < USABLE_TX_BD) { + DBRUNIF((ifp->if_flags & IFF_OACTIVE), + aprint_debug("%s: TX chain is open for business! Used " + "tx_bd = %d\n", sc->bnx_dev.dv_xname, + sc->used_tx_bd)); + ifp->if_flags &= ~IFF_OACTIVE; + } + + sc->tx_cons = sw_tx_cons; +} + +/****************************************************************************/ +/* Disables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_disable_intr(struct bnx_softc *sc) +{ + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); + REG_RD(sc, BNX_PCICFG_INT_ACK_CMD); +} + +/****************************************************************************/ +/* Enables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_enable_intr(struct bnx_softc *sc) +{ + u_int32_t val; + + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | + BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); + + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | + sc->last_status_idx); + + val = REG_RD(sc, BNX_HC_COMMAND); + REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); +} + +/****************************************************************************/ +/* Handles controller initialization. */ +/* */ +/****************************************************************************/ +int +bnx_init(struct ifnet *ifp) +{ + struct bnx_softc *sc = ifp->if_softc; + u_int32_t ether_mtu; + int s, error = 0; + + DBPRINT(sc, BNX_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); + + s = splnet(); + + bnx_stop(sc); + + if ((error = bnx_reset(sc, BNX_DRV_MSG_CODE_RESET)) != 0) { + aprint_error("bnx: Controller reset failed!\n"); + goto bnx_init_locked_exit; + } + + if ((error = bnx_chipinit(sc)) != 0) { + aprint_error("bnx: Controller initialization failed!\n"); + goto bnx_init_locked_exit; + } + + if ((error = bnx_blockinit(sc)) != 0) { + aprint_error("bnx: Block initialization failed!\n"); + goto bnx_init_locked_exit; + } + + /* Calculate and program the Ethernet MRU size. */ + ether_mtu = BNX_MAX_JUMBO_ETHER_MTU_VLAN; + + DBPRINT(sc, BNX_INFO, "%s(): setting MRU = %d\n", + __FUNCTION__, ether_mtu); + + /* + * Program the MRU and enable Jumbo frame + * support. + */ + REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | + BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA); + + /* Calculate the RX Ethernet frame size for rx_bd's. */ + sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; + + DBPRINT(sc, BNX_INFO, "%s(): mclbytes = %d, mbuf_alloc_size = %d, " + "max_frame_size = %d\n", __FUNCTION__, (int)MCLBYTES, + sc->mbuf_alloc_size, sc->max_frame_size); + + /* Program appropriate promiscuous/multicast filtering. */ + bnx_set_rx_mode(sc); + + /* Init RX buffer descriptor chain. */ + bnx_init_rx_chain(sc); + + /* Init TX buffer descriptor chain. */ + bnx_init_tx_chain(sc); + + /* Enable host interrupts. */ + bnx_enable_intr(sc); + + bnx_ifmedia_upd(ifp); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); + +bnx_init_locked_exit: + DBPRINT(sc, BNX_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); + + splx(s); + + return(error); +} + +/****************************************************************************/ +/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ +/* memory visible to the controller. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m_head, u_int16_t *prod, + u_int16_t *chain_prod, u_int32_t *prod_bseq) +{ + u_int32_t vlan_tag_flags = 0; + struct bnx_dmamap_arg map_arg; + bus_dmamap_t map; + int i, rc = 0; + struct m_tag *mtag; + + /* Transfer any checksum offload flags to the bd. */ + if (m_head->m_pkthdr.csum_flags) { + if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) + vlan_tag_flags |= TX_BD_FLAGS_IP_CKSUM; + if (m_head->m_pkthdr.csum_flags & + (M_CSUM_TCPv4 | M_CSUM_UDPv4)) + vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; + } + + /* Transfer any VLAN tags to the bd. */ + mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head); + if (mtag != NULL) + vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | + VLAN_TAG_VALUE(mtag)); + + /* Map the mbuf into DMAable memory. */ + map = sc->tx_mbuf_map[*chain_prod]; + map_arg.sc = sc; + map_arg.prod = *prod; + map_arg.chain_prod = *chain_prod; + map_arg.prod_bseq = *prod_bseq; + map_arg.tx_flags = vlan_tag_flags; + map_arg.maxsegs = USABLE_TX_BD - sc->used_tx_bd - BNX_TX_SLACK_SPACE; + +#if 0 + KASSERT(map_arg.maxsegs > 0, ("Invalid TX maxsegs value!")); +#endif + + for (i = 0; i < TX_PAGES; i++) + map_arg.tx_chain[i] = sc->tx_bd_chain[i]; + + /* Map the mbuf into our DMA address space. */ + if (bus_dmamap_load_mbuf(sc->bnx_dmatag, map, m_head, + BUS_DMA_NOWAIT)) { + aprint_error("%s: Error mapping mbuf into TX chain!\n", + sc->bnx_dev.dv_xname); + rc = ENOBUFS; + goto bnx_tx_encap_exit; + } + bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, + BUS_DMASYNC_PREWRITE); + bnx_dma_map_tx_desc(&map_arg, map); + + /* + * Ensure that the map for this transmission + * is placed at the array index of the last + * descriptor in this chain. This is done + * because a single map is used for all + * segments of the mbuf and we don't want to + * delete the map before all of the segments + * have been freed. + */ + sc->tx_mbuf_map[*chain_prod] = sc->tx_mbuf_map[map_arg.chain_prod]; + sc->tx_mbuf_map[map_arg.chain_prod] = map; + sc->tx_mbuf_ptr[map_arg.chain_prod] = m_head; + sc->used_tx_bd += map_arg.maxsegs; + + DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), + sc->tx_hi_watermark = sc->used_tx_bd); + + DBRUNIF(1, sc->tx_mbuf_alloc++); + + DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, *chain_prod, + map_arg.maxsegs)); + + /* prod still points the last used tx_bd at this point. */ + *prod = map_arg.prod; + *chain_prod = map_arg.chain_prod; + *prod_bseq = map_arg.prod_bseq; + +bnx_tx_encap_exit: + + return(rc); +} + +/****************************************************************************/ +/* Main transmit routine. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_start(struct ifnet *ifp) +{ + struct bnx_softc *sc = ifp->if_softc; + struct mbuf *m_head = NULL; + int count = 0; + u_int16_t tx_prod, tx_chain_prod; + u_int32_t tx_prod_bseq; + + /* If there's no link or the transmit queue is empty then just exit. */ + if (!sc->bnx_link || IFQ_IS_EMPTY(&ifp->if_snd)) { + DBPRINT(sc, BNX_INFO_SEND, + "%s(): No link or transmit queue empty.\n", __FUNCTION__); + goto bnx_start_locked_exit; + } + + /* prod points to the next free tx_bd. */ + tx_prod = sc->tx_prod; + tx_chain_prod = TX_CHAIN_IDX(tx_prod); + tx_prod_bseq = sc->tx_prod_bseq; + + DBPRINT(sc, BNX_INFO_SEND, "%s(): Start: tx_prod = 0x%04X, " + "tx_chain_prod = %04X, tx_prod_bseq = 0x%08X\n", + __FUNCTION__, tx_prod, tx_chain_prod, tx_prod_bseq); + + /* Keep adding entries while there is space in the ring. */ + while (sc->tx_mbuf_ptr[tx_chain_prod] == NULL) { + /* Check for any frames to send. */ + IFQ_POLL(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * Pack the data into the transmit ring. If we + * don't have room, place the mbuf back at the + * head of the queue and set the OACTIVE flag + * to wait for the NIC to drain the chain. + */ + if (bnx_tx_encap(sc, m_head, &tx_prod, &tx_chain_prod, + &tx_prod_bseq)) { + ifp->if_flags |= IFF_OACTIVE; + DBPRINT(sc, BNX_INFO_SEND, "TX chain is closed for " + "business! Total tx_bd used = %d\n", + sc->used_tx_bd); + break; + } + + IFQ_DEQUEUE(&ifp->if_snd, m_head); + count++; + +#if NBPFILTER > 0 + /* Send a copy of the frame to any BPF listeners. */ + if (ifp->if_bpf) + bpf_mtap(ifp->if_bpf, m_head); +#endif + tx_prod = NEXT_TX_BD(tx_prod); + tx_chain_prod = TX_CHAIN_IDX(tx_prod); + } + + if (count == 0) { + /* no packets were dequeued */ + DBPRINT(sc, BNX_VERBOSE_SEND, + "%s(): No packets were dequeued\n", __FUNCTION__); + goto bnx_start_locked_exit; + } + + /* Update the driver's counters. */ + sc->tx_prod = tx_prod; + sc->tx_prod_bseq = tx_prod_bseq; + + DBPRINT(sc, BNX_INFO_SEND, "%s(): End: tx_prod = 0x%04X, tx_chain_prod " + "= 0x%04X, tx_prod_bseq = 0x%08X\n", __FUNCTION__, tx_prod, + tx_chain_prod, tx_prod_bseq); + + /* Start the transmit. */ + REG_WR16(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BIDX, sc->tx_prod); + REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); + + /* Set the tx timeout. */ + ifp->if_timer = BNX_TX_TIMEOUT; + +bnx_start_locked_exit: + return; +} + +/****************************************************************************/ +/* Handles any IOCTL calls from the operating system. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct bnx_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct mii_data *mii; + int s, error = 0; + + s = splnet(); + + switch (command) { + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if ((ifp->if_flags & IFF_RUNNING) && + ((ifp->if_flags ^ sc->bnx_if_flags) & + (IFF_ALLMULTI | IFF_PROMISC)) != 0) { + bnx_set_rx_mode(sc); + } else if (!(ifp->if_flags & IFF_RUNNING)) + bnx_init(ifp); + + } else if (ifp->if_flags & IFF_RUNNING) + bnx_stop(sc); + + sc->bnx_if_flags = ifp->if_flags; + break; + + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + DBPRINT(sc, BNX_VERBOSE, "bnx_phy_flags = 0x%08X\n", + sc->bnx_phy_flags); + + if (sc->bnx_phy_flags & BNX_PHY_SERDES_FLAG) + error = ifmedia_ioctl(ifp, ifr, + &sc->bnx_ifmedia, command); + else { + mii = &sc->bnx_mii; + error = ifmedia_ioctl(ifp, ifr, + &mii->mii_media, command); + } + break; + + default: + error = ether_ioctl(ifp, command, data); + if (error == ENETRESET) { +#if 0 + if (ifp->if_flags & IFF_RUNNING) + /*bnx_setmulti(sc)*/; +#endif + error = 0; + } + break; + } + + splx(s); + + return (error); +} + +/****************************************************************************/ +/* Transmit timeout handler. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_watchdog(struct ifnet *ifp) +{ + struct bnx_softc *sc = ifp->if_softc; + + DBRUN(BNX_WARN_SEND, bnx_dump_driver_state(sc); + bnx_dump_status_block(sc)); + + aprint_error("%s: Watchdog timeout -- resetting!\n", + sc->bnx_dev.dv_xname); + + /* DBRUN(BNX_FATAL, bnx_breakpoint(sc)); */ + + bnx_init(ifp); + + ifp->if_oerrors++; +} + +/* + * Interrupt handler. + */ +/****************************************************************************/ +/* Main interrupt entry point. Verifies that the controller generated the */ +/* interrupt and then calls a separate routine for handle the various */ +/* interrupt causes (PHY, TX, RX). */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +int +bnx_intr(void *xsc) +{ + struct bnx_softc *sc; + struct ifnet *ifp; + u_int32_t status_attn_bits; + + sc = xsc; + ifp = &sc->ethercom.ec_if; + + DBRUNIF(1, sc->interrupts_generated++); + + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, + sc->status_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); + + /* + * If the hardware status block index + * matches the last value read by the + * driver and we haven't asserted our + * interrupt then there's nothing to do. + */ + if ((sc->status_block->status_idx == sc->last_status_idx) && + (REG_RD(sc, BNX_PCICFG_MISC_STATUS) & + BNX_PCICFG_MISC_STATUS_INTA_VALUE)) + return (0); + + /* Ack the interrupt and stop others from occuring. */ + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, + BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | + BNX_PCICFG_INT_ACK_CMD_MASK_INT); + + /* Keep processing data as long as there is work to do. */ + for (;;) { + status_attn_bits = sc->status_block->status_attn_bits; + + DBRUNIF(DB_RANDOMTRUE(bnx_debug_unexpected_attention), + aprint_debug("Simulating unexpected status attention bit set."); + status_attn_bits = status_attn_bits | + STATUS_ATTN_BITS_PARITY_ERROR); + + /* Was it a link change interrupt? */ + if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != + (sc->status_block->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE)) + bnx_phy_intr(sc); + + /* If any other attention is asserted then the chip is toast. */ + if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != + (sc->status_block->status_attn_bits_ack & + ~STATUS_ATTN_BITS_LINK_STATE))) { + DBRUN(1, sc->unexpected_attentions++); + + aprint_error("%s: Fatal attention detected: 0x%08X\n", + sc->bnx_dev.dv_xname, + sc->status_block->status_attn_bits); + + DBRUN(BNX_FATAL, + if (bnx_debug_unexpected_attention == 0) + bnx_breakpoint(sc)); + + bnx_init(ifp); + return (1); + } + + /* Check for any completed RX frames. */ + if (sc->status_block->status_rx_quick_consumer_index0 != + sc->hw_rx_cons) + bnx_rx_intr(sc); + + /* Check for any completed TX frames. */ + if (sc->status_block->status_tx_quick_consumer_index0 != + sc->hw_tx_cons) + bnx_tx_intr(sc); + + /* Save the status block index value for use during the + * next interrupt. + */ + sc->last_status_idx = sc->status_block->status_idx; + + /* Prevent speculative reads from getting ahead of the + * status block. + */ + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* If there's no work left then exit the isr. */ + if ((sc->status_block->status_rx_quick_consumer_index0 == + sc->hw_rx_cons) && + (sc->status_block->status_tx_quick_consumer_index0 == + sc->hw_tx_cons)) + break; + } + + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, + sc->status_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + + /* Re-enable interrupts. */ + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, + BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | + BNX_PCICFG_INT_ACK_CMD_MASK_INT); + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, + BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); + + /* Handle any frames that arrived while handling the interrupt. */ + if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) + bnx_start(ifp); + + return (1); +} + +/****************************************************************************/ +/* Programs the various packet receive modes (broadcast and multicast). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_set_rx_mode(struct bnx_softc *sc) +{ + struct ethercom *ec = &sc->ethercom; + struct ifnet *ifp = &ec->ec_if; + struct ether_multi *enm; + struct ether_multistep step; + u_int32_t hashes[4] = { 0, 0, 0, 0 }; + u_int32_t rx_mode, sort_mode; + int h, i; + + /* Initialize receive mode default settings. */ + rx_mode = sc->rx_mode & ~(BNX_EMAC_RX_MODE_PROMISCUOUS | + BNX_EMAC_RX_MODE_KEEP_VLAN_TAG); + sort_mode = 1 | BNX_RPM_SORT_USER0_BC_EN; + + /* + * ASF/IPMI/UMP firmware requires that VLAN tag stripping + * be enbled. + */ + if (!(sc->bnx_flags & BNX_MFW_ENABLE_FLAG)) + rx_mode |= BNX_EMAC_RX_MODE_KEEP_VLAN_TAG; + + /* + * Check for promiscuous, all multicast, or selected + * multicast address filtering. + */ + if (ifp->if_flags & IFF_PROMISC) { + DBPRINT(sc, BNX_INFO, "Enabling promiscuous mode.\n"); + + /* Enable promiscuous mode. */ + rx_mode |= BNX_EMAC_RX_MODE_PROMISCUOUS; + sort_mode |= BNX_RPM_SORT_USER0_PROM_EN; + } else if (ifp->if_flags & IFF_ALLMULTI) { +allmulti: + DBPRINT(sc, BNX_INFO, "Enabling all multicast mode.\n"); + + /* Enable all multicast addresses. */ + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) + REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), + 0xffffffff); + sort_mode |= BNX_RPM_SORT_USER0_MC_EN; + } else { + /* Accept one or more multicast(s). */ + DBPRINT(sc, BNX_INFO, "Enabling selective multicast mode.\n"); + + ETHER_FIRST_MULTI(step, ec, enm); + while (enm != NULL) { + if (bcmp(enm->enm_addrlo, enm->enm_addrhi, + ETHER_ADDR_LEN)) { + ifp->if_flags |= IFF_ALLMULTI; + goto allmulti; + } + h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & + 0x7F; + hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); + ETHER_NEXT_MULTI(step, enm); + } + + for (i = 0; i < 4; i++) + REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), + hashes[i]); + + sort_mode |= BNX_RPM_SORT_USER0_MC_HSH_EN; + } + + /* Only make changes if the recive mode has actually changed. */ + if (rx_mode != sc->rx_mode) { + DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", + rx_mode); + + sc->rx_mode = rx_mode; + REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); + } + + /* Disable and clear the exisitng sort before enabling a new sort. */ + REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); + REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); + REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); +} + +/****************************************************************************/ +/* Called periodically to updates statistics from the controllers */ +/* statistics block. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_stats_update(struct bnx_softc *sc) +{ + struct ifnet *ifp = &sc->ethercom.ec_if; + struct statistics_block *stats; + + DBPRINT(sc, BNX_EXCESSIVE, "Entering %s()\n", __FUNCTION__); + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + + stats = (struct statistics_block *)sc->stats_block; + + /* + * Update the interface statistics from the + * hardware statistics. + */ + ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; + + ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + + (u_long)stats->stat_EtherStatsOverrsizePkts + + (u_long)stats->stat_IfInMBUFDiscards + + (u_long)stats->stat_Dot3StatsAlignmentErrors + + (u_long)stats->stat_Dot3StatsFCSErrors; + + ifp->if_oerrors = (u_long) + stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + + (u_long)stats->stat_Dot3StatsExcessiveCollisions + + (u_long)stats->stat_Dot3StatsLateCollisions; + + /* + * Certain controllers don't report + * carrier sense errors correctly. + * See errata E11_5708CA0_1165. + */ + if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && + !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) + ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; + + /* + * Update the sysctl statistics from the + * hardware statistics. + */ + sc->stat_IfHCInOctets = ((u_int64_t)stats->stat_IfHCInOctets_hi << 32) + + (u_int64_t) stats->stat_IfHCInOctets_lo; + + sc->stat_IfHCInBadOctets = + ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + + (u_int64_t) stats->stat_IfHCInBadOctets_lo; + + sc->stat_IfHCOutOctets = + ((u_int64_t) stats->stat_IfHCOutOctets_hi << 32) + + (u_int64_t) stats->stat_IfHCOutOctets_lo; + + sc->stat_IfHCOutBadOctets = + ((u_int64_t) stats->stat_IfHCOutBadOctets_hi << 32) + + (u_int64_t) stats->stat_IfHCOutBadOctets_lo; + + sc->stat_IfHCInUcastPkts = + ((u_int64_t) stats->stat_IfHCInUcastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCInUcastPkts_lo; + + sc->stat_IfHCInMulticastPkts = + ((u_int64_t) stats->stat_IfHCInMulticastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCInMulticastPkts_lo; + + sc->stat_IfHCInBroadcastPkts = + ((u_int64_t) stats->stat_IfHCInBroadcastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCInBroadcastPkts_lo; + + sc->stat_IfHCOutUcastPkts = + ((u_int64_t) stats->stat_IfHCOutUcastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCOutUcastPkts_lo; + + sc->stat_IfHCOutMulticastPkts = + ((u_int64_t) stats->stat_IfHCOutMulticastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCOutMulticastPkts_lo; + + sc->stat_IfHCOutBroadcastPkts = + ((u_int64_t) stats->stat_IfHCOutBroadcastPkts_hi << 32) + + (u_int64_t) stats->stat_IfHCOutBroadcastPkts_lo; + + sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = + stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + + sc->stat_Dot3StatsCarrierSenseErrors = + stats->stat_Dot3StatsCarrierSenseErrors; + + sc->stat_Dot3StatsFCSErrors = stats->stat_Dot3StatsFCSErrors; + + sc->stat_Dot3StatsAlignmentErrors = + stats->stat_Dot3StatsAlignmentErrors; + + sc->stat_Dot3StatsSingleCollisionFrames = + stats->stat_Dot3StatsSingleCollisionFrames; + + sc->stat_Dot3StatsMultipleCollisionFrames = + stats->stat_Dot3StatsMultipleCollisionFrames; + + sc->stat_Dot3StatsDeferredTransmissions = + stats->stat_Dot3StatsDeferredTransmissions; + + sc->stat_Dot3StatsExcessiveCollisions = + stats->stat_Dot3StatsExcessiveCollisions; + + sc->stat_Dot3StatsLateCollisions = stats->stat_Dot3StatsLateCollisions; + + sc->stat_EtherStatsCollisions = stats->stat_EtherStatsCollisions; + + sc->stat_EtherStatsFragments = stats->stat_EtherStatsFragments; + + sc->stat_EtherStatsJabbers = stats->stat_EtherStatsJabbers; + + sc->stat_EtherStatsUndersizePkts = stats->stat_EtherStatsUndersizePkts; + + sc->stat_EtherStatsOverrsizePkts = stats->stat_EtherStatsOverrsizePkts; + + sc->stat_EtherStatsPktsRx64Octets = + stats->stat_EtherStatsPktsRx64Octets; + + sc->stat_EtherStatsPktsRx65Octetsto127Octets = + stats->stat_EtherStatsPktsRx65Octetsto127Octets; + + sc->stat_EtherStatsPktsRx128Octetsto255Octets = + stats->stat_EtherStatsPktsRx128Octetsto255Octets; + + sc->stat_EtherStatsPktsRx256Octetsto511Octets = + stats->stat_EtherStatsPktsRx256Octetsto511Octets; + + sc->stat_EtherStatsPktsRx512Octetsto1023Octets = + stats->stat_EtherStatsPktsRx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; + + sc->stat_EtherStatsPktsTx64Octets = + stats->stat_EtherStatsPktsTx64Octets; + + sc->stat_EtherStatsPktsTx65Octetsto127Octets = + stats->stat_EtherStatsPktsTx65Octetsto127Octets; + + sc->stat_EtherStatsPktsTx128Octetsto255Octets = + stats->stat_EtherStatsPktsTx128Octetsto255Octets; + + sc->stat_EtherStatsPktsTx256Octetsto511Octets = + stats->stat_EtherStatsPktsTx256Octetsto511Octets; + + sc->stat_EtherStatsPktsTx512Octetsto1023Octets = + stats->stat_EtherStatsPktsTx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; + + sc->stat_XonPauseFramesReceived = stats->stat_XonPauseFramesReceived; + + sc->stat_XoffPauseFramesReceived = stats->stat_XoffPauseFramesReceived; + + sc->stat_OutXonSent = stats->stat_OutXonSent; + + sc->stat_OutXoffSent = stats->stat_OutXoffSent; + + sc->stat_FlowControlDone = stats->stat_FlowControlDone; + + sc->stat_MacControlFramesReceived = + stats->stat_MacControlFramesReceived; + + sc->stat_XoffStateEntered = stats->stat_XoffStateEntered; + + sc->stat_IfInFramesL2FilterDiscards = + stats->stat_IfInFramesL2FilterDiscards; + + sc->stat_IfInRuleCheckerDiscards = stats->stat_IfInRuleCheckerDiscards; + + sc->stat_IfInFTQDiscards = stats->stat_IfInFTQDiscards; + + sc->stat_IfInMBUFDiscards = stats->stat_IfInMBUFDiscards; + + sc->stat_IfInRuleCheckerP4Hit = stats->stat_IfInRuleCheckerP4Hit; + + sc->stat_CatchupInRuleCheckerDiscards = + stats->stat_CatchupInRuleCheckerDiscards; + + sc->stat_CatchupInFTQDiscards = stats->stat_CatchupInFTQDiscards; + + sc->stat_CatchupInMBUFDiscards = stats->stat_CatchupInMBUFDiscards; + + sc->stat_CatchupInRuleCheckerP4Hit = + stats->stat_CatchupInRuleCheckerP4Hit; + + DBPRINT(sc, BNX_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); +} + +void +bnx_tick(void *xsc) +{ + struct bnx_softc *sc = xsc; + struct ifnet *ifp = &sc->ethercom.ec_if; + struct mii_data *mii = NULL; + u_int32_t msg; + + /* Tell the firmware that the driver is still running. */ +#ifdef BNX_DEBUG + msg = (u_int32_t)BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; +#else + msg = (u_int32_t)++sc->bnx_fw_drv_pulse_wr_seq; +#endif + REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg); + + /* Update the statistics from the hardware statistics block. */ + bnx_stats_update(sc); + + /* Schedule the next tick. */ + callout_reset(&sc->bnx_timeout, hz, bnx_tick, sc); + + /* If link is up already up then we're done. */ + if (sc->bnx_link) + goto bnx_tick_locked_exit; + + /* DRC - ToDo: Add SerDes support and check SerDes link here. */ + + mii = &sc->bnx_mii; + mii_tick(mii); + + /* Check if the link has come up. */ + if (!sc->bnx_link && mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bnx_link++; + /* Now that link is up, handle any outstanding TX traffic. */ + if (!IFQ_IS_EMPTY(&ifp->if_snd)) + bnx_start(ifp); + } + +bnx_tick_locked_exit: + return; +} + +/****************************************************************************/ +/* BNX Debug Routines */ +/****************************************************************************/ +#ifdef BNX_DEBUG + +/****************************************************************************/ +/* Prints out information about an mbuf. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) +{ + struct mbuf *mp = m; + + if (m == NULL) { + /* Index out of range. */ + aprint_error("mbuf ptr is null!\n"); + return; + } + + while (mp) { + aprint_debug("mbuf: vaddr = %p, m_len = %d, m_flags = ", + mp, mp->m_len); + + if (mp->m_flags & M_EXT) + aprint_debug("M_EXT "); + if (mp->m_flags & M_PKTHDR) + aprint_debug("M_PKTHDR "); + aprint_debug("\n"); + + if (mp->m_flags & M_EXT) + aprint_debug("- m_ext: vaddr = %p, ext_size = 0x%04zX\n", + mp, mp->m_ext.ext_size); + + mp = mp->m_next; + } +} + +/****************************************************************************/ +/* Prints out the mbufs in the TX mbuf chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +void +bnx_dump_tx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) +{ + struct mbuf *m; + int i; + + BNX_PRINTF(sc, + "----------------------------" + " tx mbuf data " + "----------------------------\n"); + + for (i = 0; i < count; i++) { + m = sc->tx_mbuf_ptr[chain_prod]; + BNX_PRINTF(sc, "txmbuf[%d]\n", chain_prod); + bnx_dump_mbuf(sc, m); + chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); + } + + BNX_PRINTF(sc, + "--------------------------------------------" + "----------------------------\n"); +} + +/* + * This routine prints the RX mbuf chain. + */ +void +bnx_dump_rx_mbuf_chain(struct bnx_softc *sc, int chain_prod, int count) +{ + struct mbuf *m; + int i; + + BNX_PRINTF(sc, + "----------------------------" + " rx mbuf data " + "----------------------------\n"); + + for (i = 0; i < count; i++) { + m = sc->rx_mbuf_ptr[chain_prod]; + BNX_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); + bnx_dump_mbuf(sc, m); + chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); + } + + + BNX_PRINTF(sc, + "--------------------------------------------" + "----------------------------\n"); +} + +void +bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) +{ + if (idx > MAX_TX_BD) + /* Index out of range. */ + BNX_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); + else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) + /* TX Chain page pointer. */ + BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain " + "page pointer\n", idx, txbd->tx_bd_haddr_hi, + txbd->tx_bd_haddr_lo); + else + /* Normal tx_bd entry. */ + BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " + "0x%08X, flags = 0x%08X\n", idx, + txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, + txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag_flags); +} + +void +bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) +{ + if (idx > MAX_RX_BD) + /* Index out of range. */ + BNX_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); + else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) + /* TX Chain page pointer. */ + BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " + "pointer\n", idx, rxbd->rx_bd_haddr_hi, + rxbd->rx_bd_haddr_lo); + else + /* Normal tx_bd entry. */ + BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " + "0x%08X, flags = 0x%08X\n", idx, + rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, + rxbd->rx_bd_len, rxbd->rx_bd_flags); +} + +void +bnx_dump_l2fhdr(struct bnx_softc *sc, int idx, struct l2_fhdr *l2fhdr) +{ + BNX_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " + "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " + "tcp_udp_xsum = 0x%04X\n", idx, + l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, + l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, + l2fhdr->l2_fhdr_tcp_udp_xsum); +} + +/* + * This routine prints the TX chain. + */ +void +bnx_dump_tx_chain(struct bnx_softc *sc, int tx_prod, int count) +{ + struct tx_bd *txbd; + int i; + + /* First some info about the tx_bd chain structure. */ + BNX_PRINTF(sc, + "----------------------------" + " tx_bd chain " + "----------------------------\n"); + + BNX_PRINTF(sc, + "page size = 0x%08X, tx chain pages = 0x%08X\n", + (u_int32_t)BCM_PAGE_SIZE, (u_int32_t) TX_PAGES); + + BNX_PRINTF(sc, + "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", + (u_int32_t)TOTAL_TX_BD_PER_PAGE, (u_int32_t)USABLE_TX_BD_PER_PAGE); + + BNX_PRINTF(sc, "total tx_bd = 0x%08X\n", (u_int32_t)TOTAL_TX_BD); + + BNX_PRINTF(sc, "" + "-----------------------------" + " tx_bd data " + "-----------------------------\n"); + + /* Now print out the tx_bd's themselves. */ + for (i = 0; i < count; i++) { + txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; + bnx_dump_txbd(sc, tx_prod, txbd); + tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); + } + + BNX_PRINTF(sc, + "-----------------------------" + "--------------" + "-----------------------------\n"); +} + +/* + * This routine prints the RX chain. + */ +void +bnx_dump_rx_chain(struct bnx_softc *sc, int rx_prod, int count) +{ + struct rx_bd *rxbd; + int i; + + /* First some info about the tx_bd chain structure. */ + BNX_PRINTF(sc, + "----------------------------" + " rx_bd chain " + "----------------------------\n"); + + BNX_PRINTF(sc, "----- RX_BD Chain -----\n"); + + BNX_PRINTF(sc, + "page size = 0x%08X, rx chain pages = 0x%08X\n", + (u_int32_t)BCM_PAGE_SIZE, (u_int32_t)RX_PAGES); + + BNX_PRINTF(sc, + "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", + (u_int32_t)TOTAL_RX_BD_PER_PAGE, (u_int32_t)USABLE_RX_BD_PER_PAGE); + + BNX_PRINTF(sc, "total rx_bd = 0x%08X\n", (u_int32_t)TOTAL_RX_BD); + + BNX_PRINTF(sc, + "----------------------------" + " rx_bd data " + "----------------------------\n"); + + /* Now print out the rx_bd's themselves. */ + for (i = 0; i < count; i++) { + rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; + bnx_dump_rxbd(sc, rx_prod, rxbd); + rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); + } + + BNX_PRINTF(sc, + "----------------------------" + "--------------" + "----------------------------\n"); +} + +/* + * This routine prints the status block. + */ +void +bnx_dump_status_block(struct bnx_softc *sc) +{ + struct status_block *sblk; + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + + sblk = sc->status_block; + + BNX_PRINTF(sc, "----------------------------- Status Block " + "-----------------------------\n"); + + BNX_PRINTF(sc, + "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", + sblk->status_attn_bits, sblk->status_attn_bits_ack, + sblk->status_idx); + + BNX_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", + sblk->status_rx_quick_consumer_index0, + sblk->status_tx_quick_consumer_index0); + + BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); + + /* Theses indices are not used for normal L2 drivers. */ + if (sblk->status_rx_quick_consumer_index1 || + sblk->status_tx_quick_consumer_index1) + BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", + sblk->status_rx_quick_consumer_index1, + sblk->status_tx_quick_consumer_index1); + + if (sblk->status_rx_quick_consumer_index2 || + sblk->status_tx_quick_consumer_index2) + BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", + sblk->status_rx_quick_consumer_index2, + sblk->status_tx_quick_consumer_index2); + + if (sblk->status_rx_quick_consumer_index3 || + sblk->status_tx_quick_consumer_index3) + BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", + sblk->status_rx_quick_consumer_index3, + sblk->status_tx_quick_consumer_index3); + + if (sblk->status_rx_quick_consumer_index4 || + sblk->status_rx_quick_consumer_index5) + BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", + sblk->status_rx_quick_consumer_index4, + sblk->status_rx_quick_consumer_index5); + + if (sblk->status_rx_quick_consumer_index6 || + sblk->status_rx_quick_consumer_index7) + BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", + sblk->status_rx_quick_consumer_index6, + sblk->status_rx_quick_consumer_index7); + + if (sblk->status_rx_quick_consumer_index8 || + sblk->status_rx_quick_consumer_index9) + BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", + sblk->status_rx_quick_consumer_index8, + sblk->status_rx_quick_consumer_index9); + + if (sblk->status_rx_quick_consumer_index10 || + sblk->status_rx_quick_consumer_index11) + BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", + sblk->status_rx_quick_consumer_index10, + sblk->status_rx_quick_consumer_index11); + + if (sblk->status_rx_quick_consumer_index12 || + sblk->status_rx_quick_consumer_index13) + BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", + sblk->status_rx_quick_consumer_index12, + sblk->status_rx_quick_consumer_index13); + + if (sblk->status_rx_quick_consumer_index14 || + sblk->status_rx_quick_consumer_index15) + BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", + sblk->status_rx_quick_consumer_index14, + sblk->status_rx_quick_consumer_index15); + + if (sblk->status_completion_producer_index || + sblk->status_cmd_consumer_index) + BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", + sblk->status_completion_producer_index, + sblk->status_cmd_consumer_index); + + BNX_PRINTF(sc, "-------------------------------------------" + "-----------------------------\n"); +} + +/* + * This routine prints the statistics block. + */ +void +bnx_dump_stats_block(struct bnx_softc *sc) +{ + struct statistics_block *sblk; + bus_dmamap_sync(sc->bnx_dmatag, sc->status_map, 0, BNX_STATUS_BLK_SZ, + BUS_DMASYNC_POSTREAD); + + sblk = sc->stats_block; + + BNX_PRINTF(sc, "" + "-----------------------------" + " Stats Block " + "-----------------------------\n"); + + BNX_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " + "IfHcInBadOctets = 0x%08X:%08X\n", + sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, + sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); + + BNX_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " + "IfHcOutBadOctets = 0x%08X:%08X\n", + sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, + sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); + + BNX_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " + "IfHcInMulticastPkts = 0x%08X:%08X\n", + sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, + sblk->stat_IfHCInMulticastPkts_hi, + sblk->stat_IfHCInMulticastPkts_lo); + + BNX_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " + "IfHcOutUcastPkts = 0x%08X:%08X\n", + sblk->stat_IfHCInBroadcastPkts_hi, + sblk->stat_IfHCInBroadcastPkts_lo, + sblk->stat_IfHCOutUcastPkts_hi, + sblk->stat_IfHCOutUcastPkts_lo); + + BNX_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, " + "IfHcOutBroadcastPkts = 0x%08X:%08X\n", + sblk->stat_IfHCOutMulticastPkts_hi, + sblk->stat_IfHCOutMulticastPkts_lo, + sblk->stat_IfHCOutBroadcastPkts_hi, + sblk->stat_IfHCOutBroadcastPkts_lo); + + if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + BNX_PRINTF(sc, "0x%08X : " + "emac_tx_stat_dot3statsinternalmactransmiterrors\n", + sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); + + if (sblk->stat_Dot3StatsCarrierSenseErrors) + BNX_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", + sblk->stat_Dot3StatsCarrierSenseErrors); + + if (sblk->stat_Dot3StatsFCSErrors) + BNX_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", + sblk->stat_Dot3StatsFCSErrors); + + if (sblk->stat_Dot3StatsAlignmentErrors) + BNX_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", + sblk->stat_Dot3StatsAlignmentErrors); + + if (sblk->stat_Dot3StatsSingleCollisionFrames) + BNX_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", + sblk->stat_Dot3StatsSingleCollisionFrames); + + if (sblk->stat_Dot3StatsMultipleCollisionFrames) + BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", + sblk->stat_Dot3StatsMultipleCollisionFrames); + + if (sblk->stat_Dot3StatsDeferredTransmissions) + BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", + sblk->stat_Dot3StatsDeferredTransmissions); + + if (sblk->stat_Dot3StatsExcessiveCollisions) + BNX_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", + sblk->stat_Dot3StatsExcessiveCollisions); + + if (sblk->stat_Dot3StatsLateCollisions) + BNX_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", + sblk->stat_Dot3StatsLateCollisions); + + if (sblk->stat_EtherStatsCollisions) + BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", + sblk->stat_EtherStatsCollisions); + + if (sblk->stat_EtherStatsFragments) + BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", + sblk->stat_EtherStatsFragments); + + if (sblk->stat_EtherStatsJabbers) + BNX_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", + sblk->stat_EtherStatsJabbers); + + if (sblk->stat_EtherStatsUndersizePkts) + BNX_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", + sblk->stat_EtherStatsUndersizePkts); + + if (sblk->stat_EtherStatsOverrsizePkts) + BNX_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", + sblk->stat_EtherStatsOverrsizePkts); + + if (sblk->stat_EtherStatsPktsRx64Octets) + BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", + sblk->stat_EtherStatsPktsRx64Octets); + + if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) + BNX_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", + sblk->stat_EtherStatsPktsRx65Octetsto127Octets); + + if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsRx128Octetsto255Octets\n", + sblk->stat_EtherStatsPktsRx128Octetsto255Octets); + + if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsRx256Octetsto511Octets\n", + sblk->stat_EtherStatsPktsRx256Octetsto511Octets); + + if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsRx512Octetsto1023Octets\n", + sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); + + if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsRx1024Octetsto1522Octets\n", + sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); + + if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsRx1523Octetsto9022Octets\n", + sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); + + if (sblk->stat_EtherStatsPktsTx64Octets) + BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", + sblk->stat_EtherStatsPktsTx64Octets); + + if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) + BNX_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", + sblk->stat_EtherStatsPktsTx65Octetsto127Octets); + + if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsTx128Octetsto255Octets\n", + sblk->stat_EtherStatsPktsTx128Octetsto255Octets); + + if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsTx256Octetsto511Octets\n", + sblk->stat_EtherStatsPktsTx256Octetsto511Octets); + + if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsTx512Octetsto1023Octets\n", + sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); + + if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsTx1024Octetsto1522Octets\n", + sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); + + if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) + BNX_PRINTF(sc, "0x%08X : " + "EtherStatsPktsTx1523Octetsto9022Octets\n", + sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); + + if (sblk->stat_XonPauseFramesReceived) + BNX_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", + sblk->stat_XonPauseFramesReceived); + + if (sblk->stat_XoffPauseFramesReceived) + BNX_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", + sblk->stat_XoffPauseFramesReceived); + + if (sblk->stat_OutXonSent) + BNX_PRINTF(sc, "0x%08X : OutXonSent\n", + sblk->stat_OutXonSent); + + if (sblk->stat_OutXoffSent) + BNX_PRINTF(sc, "0x%08X : OutXoffSent\n", + sblk->stat_OutXoffSent); + + if (sblk->stat_FlowControlDone) + BNX_PRINTF(sc, "0x%08X : FlowControlDone\n", + sblk->stat_FlowControlDone); + + if (sblk->stat_MacControlFramesReceived) + BNX_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", + sblk->stat_MacControlFramesReceived); + + if (sblk->stat_XoffStateEntered) + BNX_PRINTF(sc, "0x%08X : XoffStateEntered\n", + sblk->stat_XoffStateEntered); + + if (sblk->stat_IfInFramesL2FilterDiscards) + BNX_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", + sblk->stat_IfInFramesL2FilterDiscards); + + if (sblk->stat_IfInRuleCheckerDiscards) + BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", + sblk->stat_IfInRuleCheckerDiscards); + + if (sblk->stat_IfInFTQDiscards) + BNX_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", + sblk->stat_IfInFTQDiscards); + + if (sblk->stat_IfInMBUFDiscards) + BNX_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", + sblk->stat_IfInMBUFDiscards); + + if (sblk->stat_IfInRuleCheckerP4Hit) + BNX_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", + sblk->stat_IfInRuleCheckerP4Hit); + + if (sblk->stat_CatchupInRuleCheckerDiscards) + BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", + sblk->stat_CatchupInRuleCheckerDiscards); + + if (sblk->stat_CatchupInFTQDiscards) + BNX_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", + sblk->stat_CatchupInFTQDiscards); + + if (sblk->stat_CatchupInMBUFDiscards) + BNX_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", + sblk->stat_CatchupInMBUFDiscards); + + if (sblk->stat_CatchupInRuleCheckerP4Hit) + BNX_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", + sblk->stat_CatchupInRuleCheckerP4Hit); + + BNX_PRINTF(sc, + "-----------------------------" + "--------------" + "-----------------------------\n"); +} + +void +bnx_dump_driver_state(struct bnx_softc *sc) +{ + BNX_PRINTF(sc, + "-----------------------------" + " Driver State " + "-----------------------------\n"); + + BNX_PRINTF(sc, "%p - (sc) driver softc structure virtual " + "address\n", sc); + + BNX_PRINTF(sc, "%p - (sc->status_block) status block virtual address\n", + sc->status_block); + + BNX_PRINTF(sc, "%p - (sc->stats_block) statistics block virtual " + "address\n", sc->stats_block); + + BNX_PRINTF(sc, "%p - (sc->tx_bd_chain) tx_bd chain virtual " + "adddress\n", sc->tx_bd_chain); + + BNX_PRINTF(sc, "%p - (sc->rx_bd_chain) rx_bd chain virtual address\n", + sc->rx_bd_chain); + + BNX_PRINTF(sc, "%p - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", + sc->tx_mbuf_ptr); + + BNX_PRINTF(sc, "%p - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", + sc->rx_mbuf_ptr); + + BNX_PRINTF(sc, + " 0x%08X - (sc->interrupts_generated) h/w intrs\n", + sc->interrupts_generated); + + BNX_PRINTF(sc, + " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", + sc->rx_interrupts); + + BNX_PRINTF(sc, + " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", + sc->tx_interrupts); + + BNX_PRINTF(sc, + " 0x%08X - (sc->last_status_idx) status block index\n", + sc->last_status_idx); + + BNX_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", + sc->tx_prod); + + BNX_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", + sc->tx_cons); + + BNX_PRINTF(sc, + " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", + sc->tx_prod_bseq); + + BNX_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", + sc->rx_prod); + + BNX_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", + sc->rx_cons); + + BNX_PRINTF(sc, + " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", + sc->rx_prod_bseq); + + BNX_PRINTF(sc, + " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", + sc->rx_mbuf_alloc); + + BNX_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", + sc->free_rx_bd); + + BNX_PRINTF(sc, + "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", + sc->rx_low_watermark, (u_int32_t) USABLE_RX_BD); + + BNX_PRINTF(sc, + " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", + sc->tx_mbuf_alloc); + + BNX_PRINTF(sc, + " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", + sc->rx_mbuf_alloc); + + BNX_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", + sc->used_tx_bd); + + BNX_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", + sc->tx_hi_watermark, (u_int32_t) USABLE_TX_BD); + + BNX_PRINTF(sc, + " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", + sc->mbuf_alloc_failed); + + BNX_PRINTF(sc, "-------------------------------------------" + "-----------------------------\n"); +} + +void +bnx_dump_hw_state(struct bnx_softc *sc) +{ + u_int32_t val1; + int i; + + BNX_PRINTF(sc, + "----------------------------" + " Hardware State " + "----------------------------\n"); + + BNX_PRINTF(sc, "0x%08X : bootcode version\n", sc->bnx_fw_ver); + + val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", + val1, BNX_MISC_ENABLE_STATUS_BITS); + + val1 = REG_RD(sc, BNX_DMA_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS); + + val1 = REG_RD(sc, BNX_CTX_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS); + + val1 = REG_RD(sc, BNX_EMAC_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, + BNX_EMAC_STATUS); + + val1 = REG_RD(sc, BNX_RPM_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS); + + val1 = REG_RD(sc, BNX_TBDR_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, + BNX_TBDR_STATUS); + + val1 = REG_RD(sc, BNX_TDMA_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, + BNX_TDMA_STATUS); + + val1 = REG_RD(sc, BNX_HC_STATUS); + BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); + + BNX_PRINTF(sc, + "----------------------------" + "----------------" + "----------------------------\n"); + + BNX_PRINTF(sc, + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (i = 0x400; i < 0x8000; i += 0x10) + BNX_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", + i, REG_RD(sc, i), REG_RD(sc, i + 0x4), + REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); + + BNX_PRINTF(sc, + "----------------------------" + "----------------" + "----------------------------\n"); +} + +void +bnx_breakpoint(struct bnx_softc *sc) +{ + /* Unreachable code to shut the compiler up about unused functions. */ + if (0) { + bnx_dump_txbd(sc, 0, NULL); + bnx_dump_rxbd(sc, 0, NULL); + bnx_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); + bnx_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); + bnx_dump_l2fhdr(sc, 0, NULL); + bnx_dump_tx_chain(sc, 0, USABLE_TX_BD); + bnx_dump_rx_chain(sc, 0, USABLE_RX_BD); + bnx_dump_status_block(sc); + bnx_dump_stats_block(sc); + bnx_dump_driver_state(sc); + bnx_dump_hw_state(sc); + } + + bnx_dump_driver_state(sc); + /* Print the important status block fields. */ + bnx_dump_status_block(sc); + +#if 0 + /* Call the debugger. */ + breakpoint(); +#endif + + return; +} +#endif diff --git a/sys/dev/pci/if_bnxreg.h b/sys/dev/pci/if_bnxreg.h new file mode 100644 index 000000000000..35da333f7c97 --- /dev/null +++ b/sys/dev/pci/if_bnxreg.h @@ -0,0 +1,4848 @@ +/* $NetBSD: if_bnxreg.h,v 1.1 2006/12/17 23:02:06 bouyer Exp $ */ +/* $OpenBSD: if_bnxreg.h,v 1.11 2006/08/21 03:22:09 brad Exp $ */ + +/*- + * Copyright (c) 2006 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ + */ + +#undef BNX_DEBUG + +#ifndef _BNX_H_DEFINED +#define _BNX_H_DEFINED + +#ifdef _KERNEL_OPT +#include "bpfilter.h" +#include "opt_inet.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef INET +#include +#include +#include +#include +#include +#endif + +#include + +#if NBPFILTER > 0 +#include +#endif + +#include +#include +#include + +#include +#include +#include +#include + +#define ETHER_ALIGN 2 + +/****************************************************************************/ +/* Debugging macros and definitions. */ +/****************************************************************************/ +#define BNX_CP_LOAD 0x00000001 +#define BNX_CP_SEND 0x00000002 +#define BNX_CP_RECV 0x00000004 +#define BNX_CP_INTR 0x00000008 +#define BNX_CP_UNLOAD 0x00000010 +#define BNX_CP_RESET 0x00000020 +#define BNX_CP_ALL 0x00FFFFFF + +#define BNX_CP_MASK 0x00FFFFFF + +#define BNX_LEVEL_FATAL 0x00000000 +#define BNX_LEVEL_WARN 0x01000000 +#define BNX_LEVEL_INFO 0x02000000 +#define BNX_LEVEL_VERBOSE 0x03000000 +#define BNX_LEVEL_EXCESSIVE 0x04000000 + +#define BNX_LEVEL_MASK 0xFF000000 + +#define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN) +#define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO) +#define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE) + +#define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN) +#define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO) +#define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE) + +#define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN) +#define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO) +#define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE) + +#define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN) +#define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO) +#define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE) + +#define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN) +#define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO) +#define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE) + +#define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN) +#define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO) +#define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE) + +#define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL) +#define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN) +#define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO) +#define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE) +#define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE) + +#define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug) +#define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK)) +#define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m)) + +#ifdef BNX_DEBUG + +/* Print a message based on the logging level and code path. */ +#define DBPRINT(sc, level, format, args...) \ + if (BNX_LOG_MSG(level)) { \ + aprint_debug("%s: " format, \ + sc->bnx_dev.dv_xname, ## args); \ + } + +/* Runs a particular command based on the logging level and code path. */ +#define DBRUN(m, args...) \ + if (BNX_LOG_MSG(m)) { \ + args; \ + } + +/* Runs a particular command based on the logging level. */ +#define DBRUNLV(level, args...) \ + if (BNX_MSG_LEVEL(level)) { \ + args; \ + } + +/* Runs a particular command based on the code path. */ +#define DBRUNCP(cp, args...) \ + if (BNX_CODE_PATH(cp)) { \ + args; \ + } + +/* Runs a particular command based on a condition. */ +#define DBRUNIF(cond, args...) \ + if (cond) { \ + args; \ + } +#if 0 +/* Needed for random() function which is only used in debugging. */ +#include +#endif + +/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ +#define DB_RANDOMFALSE(defects) (random() > defects) +#define DB_OR_RANDOMFALSE(defects) || (random() > defects) +#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) + +/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ +#define DB_RANDOMTRUE(defects) (random() < defects) +#define DB_OR_RANDOMTRUE(defects) || (random() < defects) +#define DB_AND_RANDOMTRUE(defects) && (random() < defects) + +#else + +#define DBPRINT(level, format, args...) +#define DBRUN(m, args...) +#define DBRUNLV(level, args...) +#define DBRUNCP(cp, args...) +#define DBRUNIF(cond, args...) +#define DB_RANDOMFALSE(defects) +#define DB_OR_RANDOMFALSE(percent) +#define DB_AND_RANDOMFALSE(percent) +#define DB_RANDOMTRUE(defects) +#define DB_OR_RANDOMTRUE(percent) +#define DB_AND_RANDOMTRUE(percent) + +#endif /* BNX_DEBUG */ + + +/****************************************************************************/ +/* Device identification definitions. */ +/****************************************************************************/ +#define BRCM_VENDORID 0x14E4 +#define BRCM_DEVICEID_BCM5706 0x164A +#define BRCM_DEVICEID_BCM5706S 0x16AA +#define BRCM_DEVICEID_BCM5708 0x164C +#define BRCM_DEVICEID_BCM5708S 0x16AC + +#define HP_VENDORID 0x103C + +#define PCI_ANY_ID (u_int16_t) (~0U) + +/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ + +#define BNX_CHIP_NUM(sc) (((sc)->bnx_chipid) & 0xffff0000) +#define BNX_CHIP_NUM_5706 0x57060000 +#define BNX_CHIP_NUM_5708 0x57080000 + +#define BNX_CHIP_REV(sc) (((sc)->bnx_chipid) & 0x0000f000) +#define BNX_CHIP_REV_Ax 0x00000000 +#define BNX_CHIP_REV_Bx 0x00001000 +#define BNX_CHIP_REV_Cx 0x00002000 + +#define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0) +#define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f) + +#define BNX_CHIP_ID(sc) (((sc)->bnx_chipid) & 0xfffffff0) +#define BNX_CHIP_ID_5706_A0 0x57060000 +#define BNX_CHIP_ID_5706_A1 0x57060010 +#define BNX_CHIP_ID_5706_A2 0x57060020 +#define BNX_CHIP_ID_5708_A0 0x57080000 +#define BNX_CHIP_ID_5708_B0 0x57081000 +#define BNX_CHIP_ID_5708_B1 0x57081010 + +#define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf) + +/* A serdes chip will have the first bit of the bond id set. */ +#define BNX_CHIP_BOND_ID_SERDES_BIT 0x01 + + +/* shorthand one */ +#define BNX_ASICREV(x) ((x) >> 28) +#define BNX_ASICREV_BCM5700 0x06 + +/* chip revisions */ +#define BNX_CHIPREV(x) ((x) >> 24) +#define BNX_CHIPREV_5700_AX 0x70 +#define BNX_CHIPREV_5700_BX 0x71 +#define BNX_CHIPREV_5700_CX 0x72 +#define BNX_CHIPREV_5701_AX 0x00 + +struct bnx_type { + u_int16_t bnx_vid; + u_int16_t bnx_did; + u_int16_t bnx_svid; + u_int16_t bnx_sdid; + char *bnx_name; +}; + +/****************************************************************************/ +/* Byte order conversions. */ +/****************************************************************************/ +#define betoh32(x) be32toh(x) +#define bnx_htobe16(x) htobe16(x) +#define bnx_htobe32(x) htobe32(x) +#define bnx_htobe64(x) htobe64(x) +#define bnx_htole16(x) htole16(x) +#define bnx_htole32(x) htole32(x) +#define bnx_htole64(x) htole64(x) + +#define bnx_be16toh(x) betoh16(x) +#define bnx_be32toh(x) betoh32(x) +#define bnx_be64toh(x) betoh64(x) +#define bnx_le16toh(x) letoh16(x) +#define bnx_le32toh(x) letoh32(x) +#define bnx_le64toh(x) letoh64(x) + + +/****************************************************************************/ +/* NVRAM Access */ +/****************************************************************************/ + +/* Buffered flash (Atmel: AT45DB011B) specific information */ +#define SEEPROM_PAGE_BITS 2 +#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) +#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) +#define SEEPROM_PAGE_SIZE 4 +#define SEEPROM_TOTAL_SIZE 65536 + +#define BUFFERED_FLASH_PAGE_BITS 9 +#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) +#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) +#define BUFFERED_FLASH_PAGE_SIZE 264 +#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 + +#define SAIFUN_FLASH_PAGE_BITS 8 +#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) +#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) +#define SAIFUN_FLASH_PAGE_SIZE 256 +#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 + +#define ST_MICRO_FLASH_PAGE_BITS 8 +#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) +#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) +#define ST_MICRO_FLASH_PAGE_SIZE 256 +#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 + +#define NVRAM_TIMEOUT_COUNT 30000 +#define BNX_FLASHDESC_MAX 64 + +#define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \ + BNX_NVM_CFG1_BUFFER_MODE | \ + BNX_NVM_CFG1_PROTECT_MODE | \ + BNX_NVM_CFG1_FLASH_SIZE) + +#define FLASH_BACKUP_STRAP_MASK (0xf << 26) + +struct flash_spec { + u_int32_t strapping; + u_int32_t config1; + u_int32_t config2; + u_int32_t config3; + u_int32_t write1; + u_int32_t buffered; + u_int32_t page_bits; + u_int32_t page_size; + u_int32_t addr_mask; + u_int32_t total_size; + const u_int8_t *name; +}; + + +/****************************************************************************/ +/* Shared Memory layout */ +/* The BNX bootcode will initialize this data area with port configurtion */ +/* information which can be accessed by the driver. */ +/****************************************************************************/ + +/* + * This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. + */ +#define DRV_PULSE_PERIOD_MS 250 + +/* + * This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. + */ +#define FW_ACK_TIME_OUT_MS 100 + + +#define BNX_DRV_RESET_SIGNATURE 0x00000000 +#define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ + +#define BNX_DRV_MB 0x00000004 +#define BNX_DRV_MSG_CODE 0xff000000 +#define BNX_DRV_MSG_CODE_RESET 0x01000000 +#define BNX_DRV_MSG_CODE_UNLOAD 0x02000000 +#define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000 +#define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 +#define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 +#define BNX_DRV_MSG_CODE_PULSE 0x06000000 +#define BNX_DRV_MSG_CODE_DIAG 0x07000000 +#define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 + +#define BNX_DRV_MSG_DATA 0x00ff0000 +#define BNX_DRV_MSG_DATA_WAIT0 0x00010000 +#define BNX_DRV_MSG_DATA_WAIT1 0x00020000 +#define BNX_DRV_MSG_DATA_WAIT2 0x00030000 +#define BNX_DRV_MSG_DATA_WAIT3 0x00040000 + +#define BNX_DRV_MSG_SEQ 0x0000ffff + +#define BNX_FW_MB 0x00000008 +#define BNX_FW_MSG_ACK 0x0000ffff +#define BNX_FW_MSG_STATUS_MASK 0x00ff0000 +#define BNX_FW_MSG_STATUS_OK 0x00000000 +#define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000 + +#define BNX_LINK_STATUS 0x0000000c +#define BNX_LINK_STATUS_INIT_VALUE 0xffffffff +#define BNX_LINK_STATUS_LINK_UP 0x1 +#define BNX_LINK_STATUS_LINK_DOWN 0x0 +#define BNX_LINK_STATUS_SPEED_MASK 0x1e +#define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BNX_LINK_STATUS_10HALF (1<<1) +#define BNX_LINK_STATUS_10FULL (2<<1) +#define BNX_LINK_STATUS_100HALF (3<<1) +#define BNX_LINK_STATUS_100BASE_T4 (4<<1) +#define BNX_LINK_STATUS_100FULL (5<<1) +#define BNX_LINK_STATUS_1000HALF (6<<1) +#define BNX_LINK_STATUS_1000FULL (7<<1) +#define BNX_LINK_STATUS_2500HALF (8<<1) +#define BNX_LINK_STATUS_2500FULL (9<<1) +#define BNX_LINK_STATUS_AN_ENABLED (1<<5) +#define BNX_LINK_STATUS_AN_COMPLETE (1<<6) +#define BNX_LINK_STATUS_PARALLEL_DET (1<<7) +#define BNX_LINK_STATUS_RESERVED (1<<8) +#define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BNX_LINK_STATUS_SERDES_LINK (1<<20) +#define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) + +#define BNX_DRV_PULSE_MB 0x00000010 +#define BNX_DRV_PULSE_SEQ_MASK 0x00007fff + +/* Indicate to the firmware not to go into the + * OS absent when it is not getting driver pulse. + * This is used for debugging. */ +#define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 + +#define BNX_DEV_INFO_SIGNATURE 0x00000020 +#define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900 +#define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 +#define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01 +#define BNX_DEV_INFO_SECONDARY_PORT 0x80 +#define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 + +#define BNX_SHARED_HW_CFG_PART_NUM 0x00000024 + +#define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 +#define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 +#define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 +#define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 +#define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff + +#define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 +#define BNX_SHARED_HW_CFG_CONFIG 0x0000003c +#define BNX_SHARED_HW_CFG_DESIGN_NIC 0 +#define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1 +#define BNX_SHARED_HW_CFG_PHY_COPPER 0 +#define BNX_SHARED_HW_CFG_PHY_FIBER 0x2 +#define BNX_SHARED_HW_CFG_PHY_2_5G 0x20 +#define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40 +#define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 +#define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300 +#define BNX_SHARED_HW_CFG_LED_MODE_MAC 0 +#define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 +#define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 + +#define BNX_SHARED_HW_CFG_CONFIG2 0x00000040 +#define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 + +#define BNX_DEV_INFO_BC_REV 0x0000004c + +#define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050 +#define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff + +#define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054 +#define BNX_PORT_HW_CFG_CONFIG 0x00000058 +#define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff +#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 +#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 +#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 +#define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 + +#define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 +#define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c +#define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 +#define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 +#define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 +#define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c + +#define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 + +#define BNX_DEV_INFO_FORMAT_REV 0x000000c4 +#define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000 +#define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24) + +#define BNX_SHARED_FEATURE 0x000000c8 +#define BNX_SHARED_FEATURE_MASK 0xffffffff + +#define BNX_PORT_FEATURE 0x000000d8 +#define BNX_PORT2_FEATURE 0x00000014c +#define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000 +#define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000 +#define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000 +#define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000 +#define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf +#define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 +#define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1 +#define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2 +#define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3 +#define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4 +#define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5 +#define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6 +#define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7 +#define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8 +#define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9 +#define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa +#define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb +#define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc +#define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd +#define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe +#define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf + +#define BNX_PORT_FEATURE_WOL 0xdc +#define BNX_PORT2_FEATURE_WOL 0x150 +#define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 +#define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 +#define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 +#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 +#define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 +#define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 +#define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 +#define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 +#define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 +#define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 + +#define BNX_PORT_FEATURE_MBA 0xe0 +#define BNX_PORT2_FEATURE_MBA 0x154 +#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 +#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 +#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 +#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 +#define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 +#define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 +#define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 +#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 +#define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 +#define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 +#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 +#define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 +#define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 + +#define BNX_PORT_FEATURE_IMD 0xe4 +#define BNX_PORT2_FEATURE_IMD 0x158 +#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 +#define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 + +#define BNX_PORT_FEATURE_VLAN 0xe8 +#define BNX_PORT2_FEATURE_VLAN 0x15c +#define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff +#define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 + +#define BNX_BC_STATE_RESET_TYPE 0x000001c0 +#define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254 +#define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff +#define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \ + 0x00010000) +#define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \ + 0x00020000) +#define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \ + 0x00030000) +#define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_RESET) +#define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_UNLOAD) +#define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_SHUTDOWN) +#define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_WOL) +#define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_DIAG) +#define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \ + (msg)) + +#define BNX_BC_STATE 0x000001c4 +#define BNX_BC_STATE_ERR_MASK 0x0000ff00 +#define BNX_BC_STATE_SIGN 0x42530000 +#define BNX_BC_STATE_SIGN_MASK 0xffff0000 +#define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1) +#define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2) +#define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3) +#define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4) +#define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5) +#define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6) +#define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7) +#define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8) +#define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9) +#define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81) +#define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82) +#define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83) +#define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84) +#define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85) +#define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86) +#define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87) +#define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88) +#define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89) +#define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100) +#define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200) +#define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300) +#define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400) +#define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500) +#define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600) +#define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700) + +#define BNX_BC_STATE_DEBUG_CMD 0x1dc +#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 +#define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 +#define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff +#define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff + +#define HOST_VIEW_SHMEM_BASE 0x167c00 + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BNX_PCI_BAR0 0x10 +#define BNX_PCI_PCIX_CMD 0x42 + +/****************************************************************************/ +/* Convenience definitions. */ +/****************************************************************************/ +#define BNX_PRINTF(sc, fmt, args...) aprint_error("%s: " fmt, sc->bnx_dev.dv_xname, ##args) + +#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) +#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) +#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) +#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) +#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) +#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) +#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) +#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) +#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) +#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) + +#define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo + +/* + * The following data structures are generated from RTL code. + * Do not modify any values below this line. + */ + +/****************************************************************************/ +/* Do not modify any of the following data structures, they are generated */ +/* from RTL code. */ +/* */ +/* Begin machine generated definitions. */ +/****************************************************************************/ + +/* + * tx_bd definition + */ +struct tx_bd { + u_int32_t tx_bd_haddr_hi; + u_int32_t tx_bd_haddr_lo; + u_int32_t tx_bd_mss_nbytes; + u_int32_t tx_bd_vlan_tag_flags; + #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) + #define TX_BD_FLAGS_IP_CKSUM (1<<2) + #define TX_BD_FLAGS_VLAN_TAG (1<<3) + #define TX_BD_FLAGS_COAL_NOW (1<<4) + #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) + #define TX_BD_FLAGS_END (1<<6) + #define TX_BD_FLAGS_START (1<<7) + #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_SW_FLAGS (1<<13) + #define TX_BD_FLAGS_SW_SNAP (1<<14) + #define TX_BD_FLAGS_SW_LSO (1<<15) + +}; + + +/* + * rx_bd definition + */ +struct rx_bd { + u_int32_t rx_bd_haddr_hi; + u_int32_t rx_bd_haddr_lo; + u_int32_t rx_bd_len; + u_int32_t rx_bd_flags; + #define RX_BD_FLAGS_NOPUSH (1<<0) + #define RX_BD_FLAGS_DUMMY (1<<1) + #define RX_BD_FLAGS_END (1<<2) + #define RX_BD_FLAGS_START (1<<3) + +}; + + +/* + * status_block definition + */ +struct status_block { + u_int32_t status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) + #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) + #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) + #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) + #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) + #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) + #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) + #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) + #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) + #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) + #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) + #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) + #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) + #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) + #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) + #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) + #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) + #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) + #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) + #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) + #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) + #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) + #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) + #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) + #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) + #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) + #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + + u_int32_t status_attn_bits_ack; +#if BYTE_ORDER == BIG_ENDIAN + u_int16_t status_tx_quick_consumer_index0; + u_int16_t status_tx_quick_consumer_index1; + u_int16_t status_tx_quick_consumer_index2; + u_int16_t status_tx_quick_consumer_index3; + u_int16_t status_rx_quick_consumer_index0; + u_int16_t status_rx_quick_consumer_index1; + u_int16_t status_rx_quick_consumer_index2; + u_int16_t status_rx_quick_consumer_index3; + u_int16_t status_rx_quick_consumer_index4; + u_int16_t status_rx_quick_consumer_index5; + u_int16_t status_rx_quick_consumer_index6; + u_int16_t status_rx_quick_consumer_index7; + u_int16_t status_rx_quick_consumer_index8; + u_int16_t status_rx_quick_consumer_index9; + u_int16_t status_rx_quick_consumer_index10; + u_int16_t status_rx_quick_consumer_index11; + u_int16_t status_rx_quick_consumer_index12; + u_int16_t status_rx_quick_consumer_index13; + u_int16_t status_rx_quick_consumer_index14; + u_int16_t status_rx_quick_consumer_index15; + u_int16_t status_completion_producer_index; + u_int16_t status_cmd_consumer_index; + u_int16_t status_idx; + u_int16_t status_unused; +#elif BYTE_ORDER == LITTLE_ENDIAN + u_int16_t status_tx_quick_consumer_index1; + u_int16_t status_tx_quick_consumer_index0; + u_int16_t status_tx_quick_consumer_index3; + u_int16_t status_tx_quick_consumer_index2; + u_int16_t status_rx_quick_consumer_index1; + u_int16_t status_rx_quick_consumer_index0; + u_int16_t status_rx_quick_consumer_index3; + u_int16_t status_rx_quick_consumer_index2; + u_int16_t status_rx_quick_consumer_index5; + u_int16_t status_rx_quick_consumer_index4; + u_int16_t status_rx_quick_consumer_index7; + u_int16_t status_rx_quick_consumer_index6; + u_int16_t status_rx_quick_consumer_index9; + u_int16_t status_rx_quick_consumer_index8; + u_int16_t status_rx_quick_consumer_index11; + u_int16_t status_rx_quick_consumer_index10; + u_int16_t status_rx_quick_consumer_index13; + u_int16_t status_rx_quick_consumer_index12; + u_int16_t status_rx_quick_consumer_index15; + u_int16_t status_rx_quick_consumer_index14; + u_int16_t status_cmd_consumer_index; + u_int16_t status_completion_producer_index; + u_int16_t status_unused; + u_int16_t status_idx; +#endif +}; + + +/* + * statistics_block definition + */ +struct statistics_block { + u_int32_t stat_IfHCInOctets_hi; + u_int32_t stat_IfHCInOctets_lo; + u_int32_t stat_IfHCInBadOctets_hi; + u_int32_t stat_IfHCInBadOctets_lo; + u_int32_t stat_IfHCOutOctets_hi; + u_int32_t stat_IfHCOutOctets_lo; + u_int32_t stat_IfHCOutBadOctets_hi; + u_int32_t stat_IfHCOutBadOctets_lo; + u_int32_t stat_IfHCInUcastPkts_hi; + u_int32_t stat_IfHCInUcastPkts_lo; + u_int32_t stat_IfHCInMulticastPkts_hi; + u_int32_t stat_IfHCInMulticastPkts_lo; + u_int32_t stat_IfHCInBroadcastPkts_hi; + u_int32_t stat_IfHCInBroadcastPkts_lo; + u_int32_t stat_IfHCOutUcastPkts_hi; + u_int32_t stat_IfHCOutUcastPkts_lo; + u_int32_t stat_IfHCOutMulticastPkts_hi; + u_int32_t stat_IfHCOutMulticastPkts_lo; + u_int32_t stat_IfHCOutBroadcastPkts_hi; + u_int32_t stat_IfHCOutBroadcastPkts_lo; + u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u_int32_t stat_Dot3StatsCarrierSenseErrors; + u_int32_t stat_Dot3StatsFCSErrors; + u_int32_t stat_Dot3StatsAlignmentErrors; + u_int32_t stat_Dot3StatsSingleCollisionFrames; + u_int32_t stat_Dot3StatsMultipleCollisionFrames; + u_int32_t stat_Dot3StatsDeferredTransmissions; + u_int32_t stat_Dot3StatsExcessiveCollisions; + u_int32_t stat_Dot3StatsLateCollisions; + u_int32_t stat_EtherStatsCollisions; + u_int32_t stat_EtherStatsFragments; + u_int32_t stat_EtherStatsJabbers; + u_int32_t stat_EtherStatsUndersizePkts; + u_int32_t stat_EtherStatsOverrsizePkts; + u_int32_t stat_EtherStatsPktsRx64Octets; + u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; + u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; + u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; + u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; + u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; + u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; + u_int32_t stat_EtherStatsPktsTx64Octets; + u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; + u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; + u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; + u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; + u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; + u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; + u_int32_t stat_XonPauseFramesReceived; + u_int32_t stat_XoffPauseFramesReceived; + u_int32_t stat_OutXonSent; + u_int32_t stat_OutXoffSent; + u_int32_t stat_FlowControlDone; + u_int32_t stat_MacControlFramesReceived; + u_int32_t stat_XoffStateEntered; + u_int32_t stat_IfInFramesL2FilterDiscards; + u_int32_t stat_IfInRuleCheckerDiscards; + u_int32_t stat_IfInFTQDiscards; + u_int32_t stat_IfInMBUFDiscards; + u_int32_t stat_IfInRuleCheckerP4Hit; + u_int32_t stat_CatchupInRuleCheckerDiscards; + u_int32_t stat_CatchupInFTQDiscards; + u_int32_t stat_CatchupInMBUFDiscards; + u_int32_t stat_CatchupInRuleCheckerP4Hit; + u_int32_t stat_GenStat00; + u_int32_t stat_GenStat01; + u_int32_t stat_GenStat02; + u_int32_t stat_GenStat03; + u_int32_t stat_GenStat04; + u_int32_t stat_GenStat05; + u_int32_t stat_GenStat06; + u_int32_t stat_GenStat07; + u_int32_t stat_GenStat08; + u_int32_t stat_GenStat09; + u_int32_t stat_GenStat10; + u_int32_t stat_GenStat11; + u_int32_t stat_GenStat12; + u_int32_t stat_GenStat13; + u_int32_t stat_GenStat14; + u_int32_t stat_GenStat15; +}; + + +/* + * l2_fhdr definition + */ +struct l2_fhdr { + u_int32_t l2_fhdr_status; + #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) + #define L2_FHDR_STATUS_RULE_P2 (1<<3) + #define L2_FHDR_STATUS_RULE_P3 (1<<4) + #define L2_FHDR_STATUS_RULE_P4 (1<<5) + #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) + #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) + #define L2_FHDR_STATUS_RSS_HASH (1<<8) + #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) + #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) + #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + + #define L2_FHDR_ERRORS_BAD_CRC (1<<17) + #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) + #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) + #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) + #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) + #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) + #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) + + u_int32_t l2_fhdr_hash; +#if BYTE_ORDER == BIG_ENDIAN + u_int16_t l2_fhdr_pkt_len; + u_int16_t l2_fhdr_vlan_tag; + u_int16_t l2_fhdr_ip_xsum; + u_int16_t l2_fhdr_tcp_udp_xsum; +#elif BYTE_ORDER == LITTLE_ENDIAN + u_int16_t l2_fhdr_vlan_tag; + u_int16_t l2_fhdr_pkt_len; + u_int16_t l2_fhdr_tcp_udp_xsum; + u_int16_t l2_fhdr_ip_xsum; +#endif +}; + + +/* + * l2_context definition + */ +#define BNX_L2CTX_TYPE 0x00000000 +#define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) +#define BNX_L2CTX_TYPE_TYPE (0xf<<28) +#define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28) +#define BNX_L2CTX_TYPE_TYPE_L2 (1<<28) + +#define BNX_L2CTX_TX_HOST_BIDX 0x00000088 +#define BNX_L2CTX_EST_NBD 0x00000088 +#define BNX_L2CTX_CMD_TYPE 0x00000088 +#define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24) +#define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) +#define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) + +#define BNX_L2CTX_TX_HOST_BSEQ 0x00000090 +#define BNX_L2CTX_TSCH_BSEQ 0x00000094 +#define BNX_L2CTX_TBDR_BSEQ 0x00000098 +#define BNX_L2CTX_TBDR_BOFF 0x0000009c +#define BNX_L2CTX_TBDR_BIDX 0x0000009c +#define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0 +#define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4 +#define BNX_L2CTX_TXP_BOFF 0x000000a8 +#define BNX_L2CTX_TXP_BIDX 0x000000a8 +#define BNX_L2CTX_TXP_BSEQ 0x000000ac + + +/* + * l2_bd_chain_context definition + */ +#define BNX_L2CTX_BD_PRE_READ 0x00000000 +#define BNX_L2CTX_CTX_SIZE 0x00000000 +#define BNX_L2CTX_CTX_TYPE 0x00000000 +#define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) +#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) +#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) +#define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) + +#define BNX_L2CTX_HOST_BDIDX 0x00000004 +#define BNX_L2CTX_HOST_BSEQ 0x00000008 +#define BNX_L2CTX_NX_BSEQ 0x0000000c +#define BNX_L2CTX_NX_BDHADDR_HI 0x00000010 +#define BNX_L2CTX_NX_BDHADDR_LO 0x00000014 +#define BNX_L2CTX_NX_BDIDX 0x00000018 + + +/* + * pci_config_l definition + * offset: 0000 + */ +#define BNX_PCICFG_MISC_CONFIG 0x00000068 +#define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) +#define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) +#define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) +#define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) +#define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) +#define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) +#define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) +#define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) +#define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) +#define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) +#define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) + +#define BNX_PCICFG_MISC_STATUS 0x0000006c +#define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) +#define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) +#define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2) +#define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) +#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) +#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) +#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) +#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) +#define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) + +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078 +#define BNX_PCICFG_REG_WINDOW 0x00000080 +#define BNX_PCICFG_INT_ACK_CMD 0x00000084 +#define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) +#define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) +#define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) +#define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) + +#define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088 +#define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c +#define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 +#define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 + + +/* + * pci_reg definition + * offset: 0x400 + */ +#define BNX_PCI_GRC_WINDOW_ADDR 0x00000400 +#define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) + +#define BNX_PCI_CONFIG_1 0x00000404 +#define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) +#define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) +#define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) + +#define BNX_PCI_CONFIG_2 0x00000408 +#define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) +#define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) +#define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4) +#define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) +#define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) +#define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) +#define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) +#define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) +#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) +#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) +#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) +#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) +#define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) +#define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) +#define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) +#define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) + +#define BNX_PCI_CONFIG_3 0x0000040c +#define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) +#define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24) +#define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25) +#define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26) +#define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27) +#define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30) +#define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31) + +#define BNX_PCI_PM_DATA_A 0x00000410 +#define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) +#define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) +#define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) +#define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) + +#define BNX_PCI_PM_DATA_B 0x00000414 +#define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) +#define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) +#define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) +#define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) + +#define BNX_PCI_SWAP_DIAG0 0x00000418 +#define BNX_PCI_SWAP_DIAG1 0x0000041c +#define BNX_PCI_EXP_ROM_ADDR 0x00000420 +#define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) +#define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31) + +#define BNX_PCI_EXP_ROM_DATA 0x00000424 +#define BNX_PCI_VPD_INTF 0x00000428 +#define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0) + +#define BNX_PCI_VPD_ADDR_FLAG 0x0000042c +#define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) +#define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15) + +#define BNX_PCI_VPD_DATA 0x00000430 +#define BNX_PCI_ID_VAL1 0x00000434 +#define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) +#define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) + +#define BNX_PCI_ID_VAL2 0x00000438 +#define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) +#define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) + +#define BNX_PCI_ID_VAL3 0x0000043c +#define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) +#define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24) + +#define BNX_PCI_ID_VAL4 0x00000440 +#define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) +#define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) +#define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) +#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) +#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) +#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) +#define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) +#define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) +#define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) +#define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15) +#define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) +#define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) +#define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) +#define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) +#define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) + +#define BNX_PCI_ID_VAL5 0x00000444 +#define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0) +#define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1) +#define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2) +#define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3) +#define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4) +#define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) + +#define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448 +#define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) +#define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) +#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) +#define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) + +#define BNX_PCI_ID_VAL6 0x0000044c +#define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0) +#define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8) +#define BNX_PCI_ID_VAL6_BIST (0xffL<<16) + +#define BNX_PCI_MSI_DATA 0x00000450 +#define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) + +#define BNX_PCI_MSI_ADDR_H 0x00000454 +#define BNX_PCI_MSI_ADDR_L 0x00000458 + + +/* + * misc_reg definition + * offset: 0x800 + */ +#define BNX_MISC_COMMAND 0x00000800 +#define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0) +#define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1) +#define BNX_MISC_COMMAND_CORE_RESET (1L<<4) +#define BNX_MISC_COMMAND_HARD_RESET (1L<<5) +#define BNX_MISC_COMMAND_PAR_ERROR (1L<<8) +#define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) + +#define BNX_MISC_CFG 0x00000804 +#define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0) +#define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1) +#define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) +#define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1) +#define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) +#define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) +#define BNX_MISC_CFG_BIST_EN (1L<<3) +#define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) +#define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5) +#define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6) +#define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) +#define BNX_MISC_CFG_LEDMODE (0x3L<<8) +#define BNX_MISC_CFG_LEDMODE_MAC (0L<<8) +#define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8) +#define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8) + +#define BNX_MISC_ID 0x00000808 +#define BNX_MISC_ID_BOND_ID (0xfL<<0) +#define BNX_MISC_ID_CHIP_METAL (0xffL<<4) +#define BNX_MISC_ID_CHIP_REV (0xfL<<12) +#define BNX_MISC_ID_CHIP_NUM (0xffffL<<16) + +#define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c +#define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) +#define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) + +#define BNX_MISC_ENABLE_SET_BITS 0x00000810 +#define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) +#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) +#define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) + +#define BNX_MISC_ENABLE_CLR_BITS 0x00000814 +#define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) +#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) +#define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) + +#define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818 +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BNX_MISC_GPIO 0x0000081c +#define BNX_MISC_GPIO_VALUE (0xffL<<0) +#define BNX_MISC_GPIO_SET (0xffL<<8) +#define BNX_MISC_GPIO_CLR (0xffL<<16) +#define BNX_MISC_GPIO_FLOAT (0xffL<<24) + +#define BNX_MISC_GPIO_INT 0x00000820 +#define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0) +#define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) +#define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16) +#define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24) + +#define BNX_MISC_CONFIG_LFSR 0x00000824 +#define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0) + +#define BNX_MISC_LFSR_MASK_BITS 0x00000828 +#define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) +#define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) +#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) +#define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) +#define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) +#define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) +#define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) +#define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) +#define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) + +#define BNX_MISC_ARB_REQ0 0x0000082c +#define BNX_MISC_ARB_REQ1 0x00000830 +#define BNX_MISC_ARB_REQ2 0x00000834 +#define BNX_MISC_ARB_REQ3 0x00000838 +#define BNX_MISC_ARB_REQ4 0x0000083c +#define BNX_MISC_ARB_FREE0 0x00000840 +#define BNX_MISC_ARB_FREE1 0x00000844 +#define BNX_MISC_ARB_FREE2 0x00000848 +#define BNX_MISC_ARB_FREE3 0x0000084c +#define BNX_MISC_ARB_FREE4 0x00000850 +#define BNX_MISC_ARB_REQ_STATUS0 0x00000854 +#define BNX_MISC_ARB_REQ_STATUS1 0x00000858 +#define BNX_MISC_ARB_REQ_STATUS2 0x0000085c +#define BNX_MISC_ARB_REQ_STATUS3 0x00000860 +#define BNX_MISC_ARB_REQ_STATUS4 0x00000864 +#define BNX_MISC_ARB_GNT0 0x00000868 +#define BNX_MISC_ARB_GNT0_0 (0x7L<<0) +#define BNX_MISC_ARB_GNT0_1 (0x7L<<4) +#define BNX_MISC_ARB_GNT0_2 (0x7L<<8) +#define BNX_MISC_ARB_GNT0_3 (0x7L<<12) +#define BNX_MISC_ARB_GNT0_4 (0x7L<<16) +#define BNX_MISC_ARB_GNT0_5 (0x7L<<20) +#define BNX_MISC_ARB_GNT0_6 (0x7L<<24) +#define BNX_MISC_ARB_GNT0_7 (0x7L<<28) + +#define BNX_MISC_ARB_GNT1 0x0000086c +#define BNX_MISC_ARB_GNT1_8 (0x7L<<0) +#define BNX_MISC_ARB_GNT1_9 (0x7L<<4) +#define BNX_MISC_ARB_GNT1_10 (0x7L<<8) +#define BNX_MISC_ARB_GNT1_11 (0x7L<<12) +#define BNX_MISC_ARB_GNT1_12 (0x7L<<16) +#define BNX_MISC_ARB_GNT1_13 (0x7L<<20) +#define BNX_MISC_ARB_GNT1_14 (0x7L<<24) +#define BNX_MISC_ARB_GNT1_15 (0x7L<<28) + +#define BNX_MISC_ARB_GNT2 0x00000870 +#define BNX_MISC_ARB_GNT2_16 (0x7L<<0) +#define BNX_MISC_ARB_GNT2_17 (0x7L<<4) +#define BNX_MISC_ARB_GNT2_18 (0x7L<<8) +#define BNX_MISC_ARB_GNT2_19 (0x7L<<12) +#define BNX_MISC_ARB_GNT2_20 (0x7L<<16) +#define BNX_MISC_ARB_GNT2_21 (0x7L<<20) +#define BNX_MISC_ARB_GNT2_22 (0x7L<<24) +#define BNX_MISC_ARB_GNT2_23 (0x7L<<28) + +#define BNX_MISC_ARB_GNT3 0x00000874 +#define BNX_MISC_ARB_GNT3_24 (0x7L<<0) +#define BNX_MISC_ARB_GNT3_25 (0x7L<<4) +#define BNX_MISC_ARB_GNT3_26 (0x7L<<8) +#define BNX_MISC_ARB_GNT3_27 (0x7L<<12) +#define BNX_MISC_ARB_GNT3_28 (0x7L<<16) +#define BNX_MISC_ARB_GNT3_29 (0x7L<<20) +#define BNX_MISC_ARB_GNT3_30 (0x7L<<24) +#define BNX_MISC_ARB_GNT3_31 (0x7L<<28) + +#define BNX_MISC_PRBS_CONTROL 0x00000878 +#define BNX_MISC_PRBS_CONTROL_EN (1L<<0) +#define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1) +#define BNX_MISC_PRBS_CONTROL_INV (1L<<2) +#define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) +#define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4) +#define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) +#define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) +#define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) +#define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) + +#define BNX_MISC_PRBS_STATUS 0x0000087c +#define BNX_MISC_PRBS_STATUS_LOCK (1L<<0) +#define BNX_MISC_PRBS_STATUS_STKY (1L<<1) +#define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) +#define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16) + +#define BNX_MISC_SM_ASF_CONTROL 0x00000880 +#define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) +#define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) +#define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) +#define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) +#define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) +#define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) +#define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) +#define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) +#define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8) +#define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) +#define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) +#define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) +#define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) +#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) +#define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) +#define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) +#define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) + +#define BNX_MISC_SMB_IN 0x00000884 +#define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0) +#define BNX_MISC_SMB_IN_RDY (1L<<8) +#define BNX_MISC_SMB_IN_DONE (1L<<9) +#define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10) +#define BNX_MISC_SMB_IN_STATUS (0x7L<<11) +#define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11) +#define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11) +#define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) +#define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11) +#define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) + +#define BNX_MISC_SMB_OUT 0x00000888 +#define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0) +#define BNX_MISC_SMB_OUT_RDY (1L<<8) +#define BNX_MISC_SMB_OUT_START (1L<<9) +#define BNX_MISC_SMB_OUT_LAST (1L<<10) +#define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11) +#define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12) +#define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13) +#define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) +#define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) +#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) +#define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) +#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) +#define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) + +#define BNX_MISC_SMB_WATCHDOG 0x0000088c +#define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) + +#define BNX_MISC_SMB_HEARTBEAT 0x00000890 +#define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) + +#define BNX_MISC_SMB_POLL_ASF 0x00000894 +#define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) + +#define BNX_MISC_SMB_POLL_LEGACY 0x00000898 +#define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) + +#define BNX_MISC_SMB_RETRAN 0x0000089c +#define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0) + +#define BNX_MISC_SMB_TIMESTAMP 0x000008a0 +#define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) + +#define BNX_MISC_PERR_ENA0 0x000008a4 +#define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) +#define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) +#define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) +#define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) +#define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) +#define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) +#define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) +#define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) +#define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) +#define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) +#define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) +#define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) +#define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) +#define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) +#define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26) +#define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) +#define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) +#define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) +#define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) +#define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) + +#define BNX_MISC_PERR_ENA1 0x000008a8 +#define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) +#define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) +#define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) +#define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) +#define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) +#define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) +#define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) +#define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7) +#define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8) +#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) +#define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) +#define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) +#define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) +#define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) +#define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) +#define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) +#define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) +#define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) +#define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) +#define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) +#define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) +#define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) +#define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) +#define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23) +#define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24) +#define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) +#define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) +#define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) +#define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) +#define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) +#define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) +#define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) + +#define BNX_MISC_PERR_ENA2 0x000008ac +#define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0) +#define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) +#define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) +#define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) +#define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) +#define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) +#define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) +#define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) +#define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8) + +#define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0 +#define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) +#define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) + +#define BNX_MISC_VREG_CONTROL 0x000008b4 +#define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0) +#define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4) + +#define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8 +#define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) + +#define BNX_MISC_UNUSED0 0x000008bc + + +/* + * nvm_reg definition + * offset: 0x6400 + */ +#define BNX_NVM_COMMAND 0x00006400 +#define BNX_NVM_COMMAND_RST (1L<<0) +#define BNX_NVM_COMMAND_DONE (1L<<3) +#define BNX_NVM_COMMAND_DOIT (1L<<4) +#define BNX_NVM_COMMAND_WR (1L<<5) +#define BNX_NVM_COMMAND_ERASE (1L<<6) +#define BNX_NVM_COMMAND_FIRST (1L<<7) +#define BNX_NVM_COMMAND_LAST (1L<<8) +#define BNX_NVM_COMMAND_WREN (1L<<16) +#define BNX_NVM_COMMAND_WRDI (1L<<17) +#define BNX_NVM_COMMAND_EWSR (1L<<18) +#define BNX_NVM_COMMAND_WRSR (1L<<19) + +#define BNX_NVM_STATUS 0x00006404 +#define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0) +#define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4) +#define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) + +#define BNX_NVM_WRITE 0x00006408 +#define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) +#define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) + +#define BNX_NVM_ADDR 0x0000640c +#define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) +#define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) + +#define BNX_NVM_READ 0x00006410 +#define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0) +#define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0) + +#define BNX_NVM_CFG1 0x00006414 +#define BNX_NVM_CFG1_FLASH_MODE (1L<<0) +#define BNX_NVM_CFG1_BUFFER_MODE (1L<<1) +#define BNX_NVM_CFG1_PASS_MODE (1L<<2) +#define BNX_NVM_CFG1_BITBANG_MODE (1L<<3) +#define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4) +#define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) +#define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) +#define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) +#define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) +#define BNX_NVM_CFG1_PROTECT_MODE (1L<<24) +#define BNX_NVM_CFG1_FLASH_SIZE (1L<<25) +#define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31) + +#define BNX_NVM_CFG2 0x00006418 +#define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0) +#define BNX_NVM_CFG2_DUMMY (0xffL<<8) +#define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16) + +#define BNX_NVM_CFG3 0x0000641c +#define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) +#define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8) +#define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) +#define BNX_NVM_CFG3_READ_CMD (0xffL<<24) + +#define BNX_NVM_SW_ARB 0x00006420 +#define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) +#define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) +#define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) +#define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) +#define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) +#define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) +#define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) +#define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) +#define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8) +#define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9) +#define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10) +#define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11) +#define BNX_NVM_SW_ARB_REQ0 (1L<<12) +#define BNX_NVM_SW_ARB_REQ1 (1L<<13) +#define BNX_NVM_SW_ARB_REQ2 (1L<<14) +#define BNX_NVM_SW_ARB_REQ3 (1L<<15) + +#define BNX_NVM_ACCESS_ENABLE 0x00006424 +#define BNX_NVM_ACCESS_ENABLE_EN (1L<<0) +#define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1) + +#define BNX_NVM_WRITE1 0x00006428 +#define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0) +#define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8) +#define BNX_NVM_WRITE1_SR_DATA (0xffL<<16) + + + +/* + * dma_reg definition + * offset: 0xc00 + */ +#define BNX_DMA_COMMAND 0x00000c00 +#define BNX_DMA_COMMAND_ENABLE (1L<<0) + +#define BNX_DMA_STATUS 0x00000c04 +#define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0) +#define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) +#define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) +#define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) +#define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) +#define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) +#define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) +#define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) +#define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) +#define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) +#define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) + +#define BNX_DMA_CONFIG 0x00000c08 +#define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) +#define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) +#define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) +#define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) +#define BNX_DMA_CONFIG_ONE_DMA (1L<<6) +#define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) +#define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) +#define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) +#define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) +#define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) +#define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) +#define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) +#define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) +#define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24) +#define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) +#define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) +#define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) +#define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) +#define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) + +#define BNX_DMA_BLACKOUT 0x00000c0c +#define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) +#define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) +#define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) + +#define BNX_DMA_RCHAN_STAT 0x00000c30 +#define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BNX_DMA_WCHAN_STAT 0x00000c34 +#define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38 +#define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c +#define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BNX_DMA_RCHAN_STAT_00 0x00000c40 +#define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BNX_DMA_RCHAN_STAT_01 0x00000c44 +#define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BNX_DMA_RCHAN_STAT_02 0x00000c48 +#define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BNX_DMA_RCHAN_STAT_10 0x00000c4c +#define BNX_DMA_RCHAN_STAT_11 0x00000c50 +#define BNX_DMA_RCHAN_STAT_12 0x00000c54 +#define BNX_DMA_RCHAN_STAT_20 0x00000c58 +#define BNX_DMA_RCHAN_STAT_21 0x00000c5c +#define BNX_DMA_RCHAN_STAT_22 0x00000c60 +#define BNX_DMA_RCHAN_STAT_30 0x00000c64 +#define BNX_DMA_RCHAN_STAT_31 0x00000c68 +#define BNX_DMA_RCHAN_STAT_32 0x00000c6c +#define BNX_DMA_RCHAN_STAT_40 0x00000c70 +#define BNX_DMA_RCHAN_STAT_41 0x00000c74 +#define BNX_DMA_RCHAN_STAT_42 0x00000c78 +#define BNX_DMA_RCHAN_STAT_50 0x00000c7c +#define BNX_DMA_RCHAN_STAT_51 0x00000c80 +#define BNX_DMA_RCHAN_STAT_52 0x00000c84 +#define BNX_DMA_RCHAN_STAT_60 0x00000c88 +#define BNX_DMA_RCHAN_STAT_61 0x00000c8c +#define BNX_DMA_RCHAN_STAT_62 0x00000c90 +#define BNX_DMA_RCHAN_STAT_70 0x00000c94 +#define BNX_DMA_RCHAN_STAT_71 0x00000c98 +#define BNX_DMA_RCHAN_STAT_72 0x00000c9c +#define BNX_DMA_WCHAN_STAT_00 0x00000ca0 +#define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BNX_DMA_WCHAN_STAT_01 0x00000ca4 +#define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BNX_DMA_WCHAN_STAT_02 0x00000ca8 +#define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BNX_DMA_WCHAN_STAT_10 0x00000cac +#define BNX_DMA_WCHAN_STAT_11 0x00000cb0 +#define BNX_DMA_WCHAN_STAT_12 0x00000cb4 +#define BNX_DMA_WCHAN_STAT_20 0x00000cb8 +#define BNX_DMA_WCHAN_STAT_21 0x00000cbc +#define BNX_DMA_WCHAN_STAT_22 0x00000cc0 +#define BNX_DMA_WCHAN_STAT_30 0x00000cc4 +#define BNX_DMA_WCHAN_STAT_31 0x00000cc8 +#define BNX_DMA_WCHAN_STAT_32 0x00000ccc +#define BNX_DMA_WCHAN_STAT_40 0x00000cd0 +#define BNX_DMA_WCHAN_STAT_41 0x00000cd4 +#define BNX_DMA_WCHAN_STAT_42 0x00000cd8 +#define BNX_DMA_WCHAN_STAT_50 0x00000cdc +#define BNX_DMA_WCHAN_STAT_51 0x00000ce0 +#define BNX_DMA_WCHAN_STAT_52 0x00000ce4 +#define BNX_DMA_WCHAN_STAT_60 0x00000ce8 +#define BNX_DMA_WCHAN_STAT_61 0x00000cec +#define BNX_DMA_WCHAN_STAT_62 0x00000cf0 +#define BNX_DMA_WCHAN_STAT_70 0x00000cf4 +#define BNX_DMA_WCHAN_STAT_71 0x00000cf8 +#define BNX_DMA_WCHAN_STAT_72 0x00000cfc +#define BNX_DMA_ARB_STAT_00 0x00000d00 +#define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0) +#define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) +#define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) + +#define BNX_DMA_ARB_STAT_01 0x00000d04 +#define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) +#define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) +#define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) +#define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) +#define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) +#define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) +#define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) +#define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) + +#define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00 +#define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) +#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) +#define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) +#define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) +#define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) + +#define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04 +#define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08 +#define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) +#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) +#define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) +#define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) +#define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) + +#define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c +#define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10 +#define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) +#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) +#define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) +#define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) +#define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) + +#define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14 + + +/* + * context_reg definition + * offset: 0x1000 + */ +#define BNX_CTX_COMMAND 0x00001000 +#define BNX_CTX_COMMAND_ENABLED (1L<<0) + +#define BNX_CTX_STATUS 0x00001004 +#define BNX_CTX_STATUS_LOCK_WAIT (1L<<0) +#define BNX_CTX_STATUS_READ_STAT (1L<<16) +#define BNX_CTX_STATUS_WRITE_STAT (1L<<17) +#define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18) +#define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19) + +#define BNX_CTX_VIRT_ADDR 0x00001008 +#define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) + +#define BNX_CTX_PAGE_TBL 0x0000100c +#define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) + +#define BNX_CTX_DATA_ADR 0x00001010 +#define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) + +#define BNX_CTX_DATA 0x00001014 +#define BNX_CTX_LOCK 0x00001018 +#define BNX_CTX_LOCK_TYPE (0x7L<<0) +#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) +#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) +#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) +#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) +#define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) +#define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7) +#define BNX_CTX_LOCK_GRANTED (1L<<26) +#define BNX_CTX_LOCK_MODE (0x7L<<27) +#define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27) +#define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) +#define BNX_CTX_LOCK_MODE_SURE (0x2L<<27) +#define BNX_CTX_LOCK_STATUS (1L<<30) +#define BNX_CTX_LOCK_REQ (1L<<31) + +#define BNX_CTX_ACCESS_STATUS 0x00001040 +#define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) +#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) +#define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) +#define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) +#define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) + +#define BNX_CTX_DBG_LOCK_STATUS 0x00001044 +#define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) +#define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) + +#define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080 +#define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) +#define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) +#define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) + +#define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084 +#define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088 +#define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c +#define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090 +#define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094 +#define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098 +#define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c +#define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0 + + +/* + * emac_reg definition + * offset: 0x1400 + */ +#define BNX_EMAC_MODE 0x00001400 +#define BNX_EMAC_MODE_RESET (1L<<0) +#define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1) +#define BNX_EMAC_MODE_PORT (0x3L<<2) +#define BNX_EMAC_MODE_PORT_NONE (0L<<2) +#define BNX_EMAC_MODE_PORT_MII (1L<<2) +#define BNX_EMAC_MODE_PORT_GMII (2L<<2) +#define BNX_EMAC_MODE_PORT_MII_10 (3L<<2) +#define BNX_EMAC_MODE_MAC_LOOP (1L<<4) +#define BNX_EMAC_MODE_25G (1L<<5) +#define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) +#define BNX_EMAC_MODE_TX_BURST (1L<<8) +#define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) +#define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10) +#define BNX_EMAC_MODE_FORCE_LINK (1L<<11) +#define BNX_EMAC_MODE_MPKT (1L<<18) +#define BNX_EMAC_MODE_MPKT_RCVD (1L<<19) +#define BNX_EMAC_MODE_ACPI_RCVD (1L<<20) + +#define BNX_EMAC_STATUS 0x00001404 +#define BNX_EMAC_STATUS_LINK (1L<<11) +#define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12) +#define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22) +#define BNX_EMAC_STATUS_MI_INT (1L<<23) +#define BNX_EMAC_STATUS_AP_ERROR (1L<<24) +#define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) + +#define BNX_EMAC_ATTENTION_ENA 0x00001408 +#define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11) +#define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) +#define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23) +#define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) + +#define BNX_EMAC_LED 0x0000140c +#define BNX_EMAC_LED_OVERRIDE (1L<<0) +#define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1) +#define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2) +#define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3) +#define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) +#define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5) +#define BNX_EMAC_LED_TRAFFIC (1L<<6) +#define BNX_EMAC_LED_1000MB (1L<<7) +#define BNX_EMAC_LED_100MB (1L<<8) +#define BNX_EMAC_LED_10MB (1L<<9) +#define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10) +#define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19) +#define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31) + +#define BNX_EMAC_MAC_MATCH0 0x00001410 +#define BNX_EMAC_MAC_MATCH1 0x00001414 +#define BNX_EMAC_MAC_MATCH2 0x00001418 +#define BNX_EMAC_MAC_MATCH3 0x0000141c +#define BNX_EMAC_MAC_MATCH4 0x00001420 +#define BNX_EMAC_MAC_MATCH5 0x00001424 +#define BNX_EMAC_MAC_MATCH6 0x00001428 +#define BNX_EMAC_MAC_MATCH7 0x0000142c +#define BNX_EMAC_MAC_MATCH8 0x00001430 +#define BNX_EMAC_MAC_MATCH9 0x00001434 +#define BNX_EMAC_MAC_MATCH10 0x00001438 +#define BNX_EMAC_MAC_MATCH11 0x0000143c +#define BNX_EMAC_MAC_MATCH12 0x00001440 +#define BNX_EMAC_MAC_MATCH13 0x00001444 +#define BNX_EMAC_MAC_MATCH14 0x00001448 +#define BNX_EMAC_MAC_MATCH15 0x0000144c +#define BNX_EMAC_MAC_MATCH16 0x00001450 +#define BNX_EMAC_MAC_MATCH17 0x00001454 +#define BNX_EMAC_MAC_MATCH18 0x00001458 +#define BNX_EMAC_MAC_MATCH19 0x0000145c +#define BNX_EMAC_MAC_MATCH20 0x00001460 +#define BNX_EMAC_MAC_MATCH21 0x00001464 +#define BNX_EMAC_MAC_MATCH22 0x00001468 +#define BNX_EMAC_MAC_MATCH23 0x0000146c +#define BNX_EMAC_MAC_MATCH24 0x00001470 +#define BNX_EMAC_MAC_MATCH25 0x00001474 +#define BNX_EMAC_MAC_MATCH26 0x00001478 +#define BNX_EMAC_MAC_MATCH27 0x0000147c +#define BNX_EMAC_MAC_MATCH28 0x00001480 +#define BNX_EMAC_MAC_MATCH29 0x00001484 +#define BNX_EMAC_MAC_MATCH30 0x00001488 +#define BNX_EMAC_MAC_MATCH31 0x0000148c +#define BNX_EMAC_BACKOFF_SEED 0x00001498 +#define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) + +#define BNX_EMAC_RX_MTU_SIZE 0x0000149c +#define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) +#define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) + +#define BNX_EMAC_SERDES_CNTL 0x000014a4 +#define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0) +#define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3) +#define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) +#define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) +#define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10) +#define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11) +#define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12) +#define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13) +#define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) +#define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15) +#define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16) +#define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) +#define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) +#define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) +#define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) +#define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) + +#define BNX_EMAC_SERDES_STATUS 0x000014a8 +#define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) +#define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) + +#define BNX_EMAC_MDIO_COMM 0x000014ac +#define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0) +#define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) +#define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) +#define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26) +#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) +#define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) +#define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) +#define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) +#define BNX_EMAC_MDIO_COMM_FAIL (1L<<28) +#define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29) +#define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30) + +#define BNX_EMAC_MDIO_STATUS 0x000014b0 +#define BNX_EMAC_MDIO_STATUS_LINK (1L<<0) +#define BNX_EMAC_MDIO_STATUS_10MB (1L<<1) + +#define BNX_EMAC_MDIO_MODE 0x000014b4 +#define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) +#define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +#define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8) +#define BNX_EMAC_MDIO_MODE_MDIO (1L<<9) +#define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10) +#define BNX_EMAC_MDIO_MODE_MDC (1L<<11) +#define BNX_EMAC_MDIO_MODE_MDINT (1L<<12) +#define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) + +#define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8 +#define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) + +#define BNX_EMAC_TX_MODE 0x000014bc +#define BNX_EMAC_TX_MODE_RESET (1L<<0) +#define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4) +#define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) +#define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6) +#define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7) + +#define BNX_EMAC_TX_STATUS 0x000014c0 +#define BNX_EMAC_TX_STATUS_XOFFED (1L<<0) +#define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1) +#define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2) +#define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3) +#define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4) + +#define BNX_EMAC_TX_LENGTHS 0x000014c4 +#define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0) +#define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8) +#define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) + +#define BNX_EMAC_RX_MODE 0x000014c8 +#define BNX_EMAC_RX_MODE_RESET (1L<<0) +#define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2) +#define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) +#define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) +#define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) +#define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) +#define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7) +#define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8) +#define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) +#define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) +#define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) +#define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12) + +#define BNX_EMAC_RX_STATUS 0x000014cc +#define BNX_EMAC_RX_STATUS_FFED (1L<<0) +#define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) +#define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2) + +#define BNX_EMAC_MULTICAST_HASH0 0x000014d0 +#define BNX_EMAC_MULTICAST_HASH1 0x000014d4 +#define BNX_EMAC_MULTICAST_HASH2 0x000014d8 +#define BNX_EMAC_MULTICAST_HASH3 0x000014dc +#define BNX_EMAC_MULTICAST_HASH4 0x000014e0 +#define BNX_EMAC_MULTICAST_HASH5 0x000014e4 +#define BNX_EMAC_MULTICAST_HASH6 0x000014e8 +#define BNX_EMAC_MULTICAST_HASH7 0x000014ec +#define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 +#define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 +#define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 +#define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c +#define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 +#define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 +#define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 +#define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c +#define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 +#define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 +#define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 +#define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c +#define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 +#define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 +#define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 +#define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 +#define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 +#define BNX_EMAC_RXMAC_DEBUG0 0x0000155c +#define BNX_EMAC_RXMAC_DEBUG1 0x00001560 +#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) +#define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) +#define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) +#define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) +#define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) +#define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) +#define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) +#define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) +#define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) + +#define BNX_EMAC_RXMAC_DEBUG2 0x00001564 +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) +#define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) +#define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) +#define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) +#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) +#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) +#define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) +#define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) +#define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) + +#define BNX_EMAC_RXMAC_DEBUG3 0x00001568 +#define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) +#define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) + +#define BNX_EMAC_RXMAC_DEBUG4 0x0000156c +#define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) +#define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) +#define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) +#define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) +#define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) +#define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) +#define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) +#define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) +#define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28) + +#define BNX_EMAC_RXMAC_DEBUG5 0x00001570 +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) +#define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) +#define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) +#define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) +#define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) +#define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) +#define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) +#define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) +#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) +#define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) +#define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) + +#define BNX_EMAC_RX_STAT_AC0 0x00001580 +#define BNX_EMAC_RX_STAT_AC1 0x00001584 +#define BNX_EMAC_RX_STAT_AC2 0x00001588 +#define BNX_EMAC_RX_STAT_AC3 0x0000158c +#define BNX_EMAC_RX_STAT_AC4 0x00001590 +#define BNX_EMAC_RX_STAT_AC5 0x00001594 +#define BNX_EMAC_RX_STAT_AC6 0x00001598 +#define BNX_EMAC_RX_STAT_AC7 0x0000159c +#define BNX_EMAC_RX_STAT_AC8 0x000015a0 +#define BNX_EMAC_RX_STAT_AC9 0x000015a4 +#define BNX_EMAC_RX_STAT_AC10 0x000015a8 +#define BNX_EMAC_RX_STAT_AC11 0x000015ac +#define BNX_EMAC_RX_STAT_AC12 0x000015b0 +#define BNX_EMAC_RX_STAT_AC13 0x000015b4 +#define BNX_EMAC_RX_STAT_AC14 0x000015b8 +#define BNX_EMAC_RX_STAT_AC15 0x000015bc +#define BNX_EMAC_RX_STAT_AC16 0x000015c0 +#define BNX_EMAC_RX_STAT_AC17 0x000015c4 +#define BNX_EMAC_RX_STAT_AC18 0x000015c8 +#define BNX_EMAC_RX_STAT_AC19 0x000015cc +#define BNX_EMAC_RX_STAT_AC20 0x000015d0 +#define BNX_EMAC_RX_STAT_AC21 0x000015d4 +#define BNX_EMAC_RX_STAT_AC22 0x000015d8 +#define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc +#define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 +#define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 +#define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 +#define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c +#define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 +#define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 +#define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 +#define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c +#define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 +#define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 +#define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 +#define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c +#define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 +#define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c +#define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 +#define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 +#define BNX_EMAC_TXMAC_DEBUG0 0x00001658 +#define BNX_EMAC_TXMAC_DEBUG1 0x0000165c +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) +#define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) +#define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) +#define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) +#define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) +#define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) +#define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) +#define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) +#define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) +#define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) +#define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) + +#define BNX_EMAC_TXMAC_DEBUG2 0x00001660 +#define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) +#define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) +#define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) +#define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) + +#define BNX_EMAC_TXMAC_DEBUG3 0x00001664 +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) +#define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) +#define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) +#define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) +#define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) + +#define BNX_EMAC_TXMAC_DEBUG4 0x00001668 +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) +#define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) +#define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) +#define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) +#define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) +#define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) +#define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) +#define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) +#define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) +#define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) +#define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) +#define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) +#define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) +#define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31) + +#define BNX_EMAC_TX_STAT_AC0 0x00001680 +#define BNX_EMAC_TX_STAT_AC1 0x00001684 +#define BNX_EMAC_TX_STAT_AC2 0x00001688 +#define BNX_EMAC_TX_STAT_AC3 0x0000168c +#define BNX_EMAC_TX_STAT_AC4 0x00001690 +#define BNX_EMAC_TX_STAT_AC5 0x00001694 +#define BNX_EMAC_TX_STAT_AC6 0x00001698 +#define BNX_EMAC_TX_STAT_AC7 0x0000169c +#define BNX_EMAC_TX_STAT_AC8 0x000016a0 +#define BNX_EMAC_TX_STAT_AC9 0x000016a4 +#define BNX_EMAC_TX_STAT_AC10 0x000016a8 +#define BNX_EMAC_TX_STAT_AC11 0x000016ac +#define BNX_EMAC_TX_STAT_AC12 0x000016b0 +#define BNX_EMAC_TX_STAT_AC13 0x000016b4 +#define BNX_EMAC_TX_STAT_AC14 0x000016b8 +#define BNX_EMAC_TX_STAT_AC15 0x000016bc +#define BNX_EMAC_TX_STAT_AC16 0x000016c0 +#define BNX_EMAC_TX_STAT_AC17 0x000016c4 +#define BNX_EMAC_TX_STAT_AC18 0x000016c8 +#define BNX_EMAC_TX_STAT_AC19 0x000016cc +#define BNX_EMAC_TX_STAT_AC20 0x000016d0 +#define BNX_EMAC_TX_STAT_AC21 0x000016d4 +#define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 + + +/* + * rpm_reg definition + * offset: 0x1800 + */ +#define BNX_RPM_COMMAND 0x00001800 +#define BNX_RPM_COMMAND_ENABLED (1L<<0) +#define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4) + +#define BNX_RPM_STATUS 0x00001804 +#define BNX_RPM_STATUS_MBUF_WAIT (1L<<0) +#define BNX_RPM_STATUS_FREE_WAIT (1L<<1) + +#define BNX_RPM_CONFIG 0x00001808 +#define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) +#define BNX_RPM_CONFIG_ACPI_ENA (1L<<1) +#define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2) +#define BNX_RPM_CONFIG_MP_KEEP (1L<<3) +#define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) +#define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31) + +#define BNX_RPM_VLAN_MATCH0 0x00001810 +#define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) + +#define BNX_RPM_VLAN_MATCH1 0x00001814 +#define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) + +#define BNX_RPM_VLAN_MATCH2 0x00001818 +#define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) + +#define BNX_RPM_VLAN_MATCH3 0x0000181c +#define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) + +#define BNX_RPM_SORT_USER0 0x00001820 +#define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0) +#define BNX_RPM_SORT_USER0_BC_EN (1L<<16) +#define BNX_RPM_SORT_USER0_MC_EN (1L<<17) +#define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18) +#define BNX_RPM_SORT_USER0_PROM_EN (1L<<19) +#define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20) +#define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24) +#define BNX_RPM_SORT_USER0_ENA (1L<<31) + +#define BNX_RPM_SORT_USER1 0x00001824 +#define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0) +#define BNX_RPM_SORT_USER1_BC_EN (1L<<16) +#define BNX_RPM_SORT_USER1_MC_EN (1L<<17) +#define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18) +#define BNX_RPM_SORT_USER1_PROM_EN (1L<<19) +#define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20) +#define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24) +#define BNX_RPM_SORT_USER1_ENA (1L<<31) + +#define BNX_RPM_SORT_USER2 0x00001828 +#define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0) +#define BNX_RPM_SORT_USER2_BC_EN (1L<<16) +#define BNX_RPM_SORT_USER2_MC_EN (1L<<17) +#define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18) +#define BNX_RPM_SORT_USER2_PROM_EN (1L<<19) +#define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20) +#define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24) +#define BNX_RPM_SORT_USER2_ENA (1L<<31) + +#define BNX_RPM_SORT_USER3 0x0000182c +#define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0) +#define BNX_RPM_SORT_USER3_BC_EN (1L<<16) +#define BNX_RPM_SORT_USER3_MC_EN (1L<<17) +#define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18) +#define BNX_RPM_SORT_USER3_PROM_EN (1L<<19) +#define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20) +#define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24) +#define BNX_RPM_SORT_USER3_ENA (1L<<31) + +#define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 +#define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 +#define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848 +#define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c +#define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 +#define BNX_RPM_STAT_AC0 0x00001880 +#define BNX_RPM_STAT_AC1 0x00001884 +#define BNX_RPM_STAT_AC2 0x00001888 +#define BNX_RPM_STAT_AC3 0x0000188c +#define BNX_RPM_STAT_AC4 0x00001890 +#define BNX_RPM_RC_CNTL_0 0x00001900 +#define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0) +#define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8) +#define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11) +#define BNX_RPM_RC_CNTL_0_P4 (1L<<12) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) +#define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) +#define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16) +#define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) +#define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) +#define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) +#define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16) +#define BNX_RPM_RC_CNTL_0_SBIT (1L<<19) +#define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) +#define BNX_RPM_RC_CNTL_0_MAP (1L<<24) +#define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25) +#define BNX_RPM_RC_CNTL_0_MASK (1L<<26) +#define BNX_RPM_RC_CNTL_0_P1 (1L<<27) +#define BNX_RPM_RC_CNTL_0_P2 (1L<<28) +#define BNX_RPM_RC_CNTL_0_P3 (1L<<29) +#define BNX_RPM_RC_CNTL_0_NBIT (1L<<30) + +#define BNX_RPM_RC_VALUE_MASK_0 0x00001904 +#define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) +#define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) + +#define BNX_RPM_RC_CNTL_1 0x00001908 +#define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_1_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_1 0x0000190c +#define BNX_RPM_RC_CNTL_2 0x00001910 +#define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_2_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_2 0x00001914 +#define BNX_RPM_RC_CNTL_3 0x00001918 +#define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_3_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_3 0x0000191c +#define BNX_RPM_RC_CNTL_4 0x00001920 +#define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_4_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_4 0x00001924 +#define BNX_RPM_RC_CNTL_5 0x00001928 +#define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_5_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_5 0x0000192c +#define BNX_RPM_RC_CNTL_6 0x00001930 +#define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_6_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_6 0x00001934 +#define BNX_RPM_RC_CNTL_7 0x00001938 +#define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_7_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_7 0x0000193c +#define BNX_RPM_RC_CNTL_8 0x00001940 +#define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_8_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_8 0x00001944 +#define BNX_RPM_RC_CNTL_9 0x00001948 +#define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_9_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_9 0x0000194c +#define BNX_RPM_RC_CNTL_10 0x00001950 +#define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_10_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_10 0x00001954 +#define BNX_RPM_RC_CNTL_11 0x00001958 +#define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_11_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_11 0x0000195c +#define BNX_RPM_RC_CNTL_12 0x00001960 +#define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_12_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_12 0x00001964 +#define BNX_RPM_RC_CNTL_13 0x00001968 +#define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_13_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_13 0x0000196c +#define BNX_RPM_RC_CNTL_14 0x00001970 +#define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_14_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_14 0x00001974 +#define BNX_RPM_RC_CNTL_15 0x00001978 +#define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0) +#define BNX_RPM_RC_CNTL_15_B (0xfffL<<19) + +#define BNX_RPM_RC_VALUE_MASK_15 0x0000197c +#define BNX_RPM_RC_CONFIG 0x00001980 +#define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) +#define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) + +#define BNX_RPM_DEBUG0 0x00001984 +#define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0) +#define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) +#define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) +#define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) +#define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) +#define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) +#define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) +#define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22) +#define BNX_RPM_DEBUG0_FM_STARTED (1L<<23) +#define BNX_RPM_DEBUG0_DONE (1L<<24) +#define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25) +#define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) +#define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) +#define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28) +#define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) + +#define BNX_RPM_DEBUG1 0x00001988 +#define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) +#define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) +#define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) +#define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) +#define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) +#define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) +#define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) + +#define BNX_RPM_DEBUG2 0x0000198c +#define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) +#define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16) +#define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) +#define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) +#define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) +#define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) +#define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) +#define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29) +#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) +#define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) + +#define BNX_RPM_DEBUG3 0x00001990 +#define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) +#define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) +#define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) +#define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) +#define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) +#define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) +#define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) +#define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) +#define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) +#define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) +#define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) +#define BNX_RPM_DEBUG3_DROP_NXT (1L<<23) +#define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24) +#define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) +#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) +#define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) +#define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) +#define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) +#define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29) +#define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) +#define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) +#define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30) +#define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) +#define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) +#define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) + +#define BNX_RPM_DEBUG4 0x00001994 +#define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) +#define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) +#define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) +#define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) + +#define BNX_RPM_DEBUG5 0x00001998 +#define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) +#define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) +#define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) +#define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) +#define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) +#define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) +#define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) +#define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) +#define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) +#define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) +#define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) +#define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) +#define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) +#define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) +#define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) +#define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31) + +#define BNX_RPM_DEBUG6 0x0000199c +#define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) +#define BNX_RPM_DEBUG6_VEC (0xffffL<<16) + +#define BNX_RPM_DEBUG7 0x000019a0 +#define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) + +#define BNX_RPM_DEBUG8 0x000019a4 +#define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) +#define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) +#define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) +#define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) +#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) +#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) +#define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) +#define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) +#define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) +#define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) +#define BNX_RPM_DEBUG8_EOF_DET (1L<<12) +#define BNX_RPM_DEBUG8_SOF_DET (1L<<13) +#define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14) +#define BNX_RPM_DEBUG8_ALL_DONE (1L<<15) +#define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) +#define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24) + +#define BNX_RPM_DEBUG9 0x000019a8 +#define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) +#define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) +#define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) +#define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) +#define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) +#define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) +#define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) + +#define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0 +#define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4 +#define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8 +#define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc +#define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0 +#define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4 +#define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8 +#define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc +#define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0 +#define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4 +#define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8 +#define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec +#define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0 +#define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4 +#define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8 +#define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc + + +/* + * rbuf_reg definition + * offset: 0x200000 + */ +#define BNX_RBUF_COMMAND 0x00200000 +#define BNX_RBUF_COMMAND_ENABLED (1L<<0) +#define BNX_RBUF_COMMAND_FREE_INIT (1L<<1) +#define BNX_RBUF_COMMAND_RAM_INIT (1L<<2) +#define BNX_RBUF_COMMAND_OVER_FREE (1L<<4) +#define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5) + +#define BNX_RBUF_STATUS1 0x00200004 +#define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) + +#define BNX_RBUF_STATUS2 0x00200008 +#define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) +#define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) + +#define BNX_RBUF_CONFIG 0x0020000c +#define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) +#define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) + +#define BNX_RBUF_FW_BUF_ALLOC 0x00200010 +#define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) + +#define BNX_RBUF_FW_BUF_FREE 0x00200014 +#define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) +#define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) +#define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) + +#define BNX_RBUF_FW_BUF_SEL 0x00200018 +#define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) +#define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) +#define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) + +#define BNX_RBUF_CONFIG2 0x0020001c +#define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) +#define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) + +#define BNX_RBUF_CONFIG3 0x00200020 +#define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) +#define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) + +#define BNX_RBUF_PKT_DATA 0x00208000 +#define BNX_RBUF_CLIST_DATA 0x00210000 +#define BNX_RBUF_BUF_DATA 0x00220000 + + +/* + * rv2p_reg definition + * offset: 0x2800 + */ +#define BNX_RV2P_COMMAND 0x00002800 +#define BNX_RV2P_COMMAND_ENABLED (1L<<0) +#define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1) +#define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2) +#define BNX_RV2P_COMMAND_ABORT0 (1L<<4) +#define BNX_RV2P_COMMAND_ABORT1 (1L<<5) +#define BNX_RV2P_COMMAND_ABORT2 (1L<<6) +#define BNX_RV2P_COMMAND_ABORT3 (1L<<7) +#define BNX_RV2P_COMMAND_ABORT4 (1L<<8) +#define BNX_RV2P_COMMAND_ABORT5 (1L<<9) +#define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16) +#define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17) +#define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18) + +#define BNX_RV2P_STATUS 0x00002804 +#define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) +#define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) + +#define BNX_RV2P_CONFIG 0x00002808 +#define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0) +#define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) +#define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) +#define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) +#define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810 +#define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) + +#define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814 +#define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) + +#define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818 +#define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) + +#define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c +#define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) + +#define BNX_RV2P_INSTR_HIGH 0x00002830 +#define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) + +#define BNX_RV2P_INSTR_LOW 0x00002834 +#define BNX_RV2P_PROC1_ADDR_CMD 0x00002838 +#define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) +#define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) + +#define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c +#define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) +#define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) + +#define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840 +#define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844 +#define BNX_RV2P_GRC_PROC_DEBUG 0x00002848 +#define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c +#define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_RV2P_PFTQ_DATA 0x00002b40 +#define BNX_RV2P_PFTQ_CMD 0x00002b78 +#define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10) +#define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) +#define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26) +#define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) +#define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_RV2P_PFTQ_CMD_POP (1L<<30) +#define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31) + +#define BNX_RV2P_PFTQ_CTL 0x00002b7c +#define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0) +#define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) +#define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_RV2P_TFTQ_DATA 0x00002b80 +#define BNX_RV2P_TFTQ_CMD 0x00002bb8 +#define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10) +#define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) +#define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26) +#define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) +#define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_RV2P_TFTQ_CMD_POP (1L<<30) +#define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31) + +#define BNX_RV2P_TFTQ_CTL 0x00002bbc +#define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0) +#define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) +#define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_RV2P_MFTQ_DATA 0x00002bc0 +#define BNX_RV2P_MFTQ_CMD 0x00002bf8 +#define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10) +#define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) +#define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26) +#define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) +#define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_RV2P_MFTQ_CMD_POP (1L<<30) +#define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31) + +#define BNX_RV2P_MFTQ_CTL 0x00002bfc +#define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0) +#define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) +#define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * mq_reg definition + * offset: 0x3c00 + */ +#define BNX_MQ_COMMAND 0x00003c00 +#define BNX_MQ_COMMAND_ENABLED (1L<<0) +#define BNX_MQ_COMMAND_OVERFLOW (1L<<4) +#define BNX_MQ_COMMAND_WR_ERROR (1L<<5) +#define BNX_MQ_COMMAND_RD_ERROR (1L<<6) + +#define BNX_MQ_STATUS 0x00003c04 +#define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) +#define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) +#define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18) + +#define BNX_MQ_CONFIG 0x00003c08 +#define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0) +#define BNX_MQ_CONFIG_HALT_DIS (1L<<1) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) +#define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) +#define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) +#define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) + +#define BNX_MQ_ENQUEUE1 0x00003c0c +#define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2) +#define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8) +#define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) +#define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28) + +#define BNX_MQ_ENQUEUE2 0x00003c10 +#define BNX_MQ_BAD_WR_ADDR 0x00003c14 +#define BNX_MQ_BAD_RD_ADDR 0x00003c18 +#define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c +#define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) + +#define BNX_MQ_KNL_WIND_END 0x00003c20 +#define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) + +#define BNX_MQ_KNL_WRITE_MASK1 0x00003c24 +#define BNX_MQ_KNL_TX_MASK1 0x00003c28 +#define BNX_MQ_KNL_CMD_MASK1 0x00003c2c +#define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 +#define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34 +#define BNX_MQ_KNL_WRITE_MASK2 0x00003c38 +#define BNX_MQ_KNL_TX_MASK2 0x00003c3c +#define BNX_MQ_KNL_CMD_MASK2 0x00003c40 +#define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 +#define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48 +#define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c +#define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50 +#define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54 +#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 +#define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c +#define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 +#define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64 +#define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68 +#define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c +#define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 +#define BNX_MQ_MEM_WR_ADDR 0x00003c74 +#define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) + +#define BNX_MQ_MEM_WR_DATA0 0x00003c78 +#define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) + +#define BNX_MQ_MEM_WR_DATA1 0x00003c7c +#define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) + +#define BNX_MQ_MEM_WR_DATA2 0x00003c80 +#define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) + +#define BNX_MQ_MEM_RD_ADDR 0x00003c84 +#define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) + +#define BNX_MQ_MEM_RD_DATA0 0x00003c88 +#define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) + +#define BNX_MQ_MEM_RD_DATA1 0x00003c8c +#define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) + +#define BNX_MQ_MEM_RD_DATA2 0x00003c90 +#define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) + + + +/* + * tbdr_reg definition + * offset: 0x5000 + */ +#define BNX_TBDR_COMMAND 0x00005000 +#define BNX_TBDR_COMMAND_ENABLE (1L<<0) +#define BNX_TBDR_COMMAND_SOFT_RST (1L<<1) +#define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4) + +#define BNX_TBDR_STATUS 0x00005004 +#define BNX_TBDR_STATUS_DMA_WAIT (1L<<0) +#define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1) +#define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) +#define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) +#define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) +#define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) +#define BNX_TBDR_STATUS_BURST_CNT (1L<<6) + +#define BNX_TBDR_CONFIG 0x00005008 +#define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0) +#define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8) +#define BNX_TBDR_CONFIG_PRIORITY (1L<<9) +#define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) +#define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c +#define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_TBDR_FTQ_DATA 0x000053c0 +#define BNX_TBDR_FTQ_CMD 0x000053f8 +#define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_TBDR_FTQ_CMD_POP (1L<<30) +#define BNX_TBDR_FTQ_CMD_BUSY (1L<<31) + +#define BNX_TBDR_FTQ_CTL 0x000053fc +#define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * tdma_reg definition + * offset: 0x5c00 + */ +#define BNX_TDMA_COMMAND 0x00005c00 +#define BNX_TDMA_COMMAND_ENABLED (1L<<0) +#define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4) +#define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) + +#define BNX_TDMA_STATUS 0x00005c04 +#define BNX_TDMA_STATUS_DMA_WAIT (1L<<0) +#define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) +#define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) +#define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3) +#define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) +#define BNX_TDMA_STATUS_BURST_CNT (1L<<17) + +#define BNX_TDMA_CONFIG 0x00005c08 +#define BNX_TDMA_CONFIG_ONE_DMA (1L<<0) +#define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1) +#define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) +#define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) +#define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) +#define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) +#define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) +#define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8) +#define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8) +#define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8) +#define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8) +#define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8) +#define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15) +#define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16) +#define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20) + +#define BNX_TDMA_PAYLOAD_PROD 0x00005c0c +#define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) + +#define BNX_TDMA_DBG_WATCHDOG 0x00005c10 +#define BNX_TDMA_DBG_TRIGGER 0x00005c14 +#define BNX_TDMA_DMAD_FSM 0x00005c80 +#define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0) +#define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4) +#define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) +#define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12) +#define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16) +#define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20) +#define BNX_TDMA_DMAD_FSM_BD (0xfL<<24) + +#define BNX_TDMA_DMAD_STATUS 0x00005c84 +#define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) +#define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) +#define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) +#define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) + +#define BNX_TDMA_DR_INTF_FSM 0x00005c88 +#define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) +#define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) +#define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) +#define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) +#define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) + +#define BNX_TDMA_DR_INTF_STATUS 0x00005c8c +#define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) +#define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) +#define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) +#define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) +#define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) + +#define BNX_TDMA_FTQ_DATA 0x00005fc0 +#define BNX_TDMA_FTQ_CMD 0x00005ff8 +#define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_TDMA_FTQ_CMD_POP (1L<<30) +#define BNX_TDMA_FTQ_CMD_BUSY (1L<<31) + +#define BNX_TDMA_FTQ_CTL 0x00005ffc +#define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * hc_reg definition + * offset: 0x6800 + */ +#define BNX_HC_COMMAND 0x00006800 +#define BNX_HC_COMMAND_ENABLE (1L<<0) +#define BNX_HC_COMMAND_SKIP_ABORT (1L<<4) +#define BNX_HC_COMMAND_COAL_NOW (1L<<16) +#define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) +#define BNX_HC_COMMAND_STATS_NOW (1L<<18) +#define BNX_HC_COMMAND_FORCE_INT (0x3L<<19) +#define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19) +#define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19) +#define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19) +#define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19) +#define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21) + +#define BNX_HC_STATUS 0x00006804 +#define BNX_HC_STATUS_MASTER_ABORT (1L<<0) +#define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1) +#define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) +#define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) +#define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) +#define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) +#define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) +#define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) +#define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) +#define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) + +#define BNX_HC_CONFIG 0x00006808 +#define BNX_HC_CONFIG_COLLECT_STATS (1L<<0) +#define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1) +#define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2) +#define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3) +#define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4) +#define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) +#define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6) +#define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) + +#define BNX_HC_ATTN_BITS_ENABLE 0x0000680c +#define BNX_HC_STATUS_ADDR_L 0x00006810 +#define BNX_HC_STATUS_ADDR_H 0x00006814 +#define BNX_HC_STATISTICS_ADDR_L 0x00006818 +#define BNX_HC_STATISTICS_ADDR_H 0x0000681c +#define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820 +#define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BNX_HC_COMP_PROD_TRIP 0x00006824 +#define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) +#define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16) + +#define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828 +#define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BNX_HC_RX_TICKS 0x0000682c +#define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0) +#define BNX_HC_RX_TICKS_INT (0x3ffL<<16) + +#define BNX_HC_TX_TICKS 0x00006830 +#define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0) +#define BNX_HC_TX_TICKS_INT (0x3ffL<<16) + +#define BNX_HC_COM_TICKS 0x00006834 +#define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0) +#define BNX_HC_COM_TICKS_INT (0x3ffL<<16) + +#define BNX_HC_CMD_TICKS 0x00006838 +#define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0) +#define BNX_HC_CMD_TICKS_INT (0x3ffL<<16) + +#define BNX_HC_PERIODIC_TICKS 0x0000683c +#define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) + +#define BNX_HC_STAT_COLLECT_TICKS 0x00006840 +#define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) + +#define BNX_HC_STATS_TICKS 0x00006844 +#define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) + +#define BNX_HC_STAT_MEM_DATA 0x0000684c +#define BNX_HC_STAT_GEN_SEL_0 0x00006850 +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) +#define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) + +#define BNX_HC_STAT_GEN_SEL_1 0x00006854 +#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) +#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) +#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) +#define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) + +#define BNX_HC_STAT_GEN_SEL_2 0x00006858 +#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) +#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) +#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) +#define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) + +#define BNX_HC_STAT_GEN_SEL_3 0x0000685c +#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) +#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) +#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) +#define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) + +#define BNX_HC_STAT_GEN_STAT0 0x00006888 +#define BNX_HC_STAT_GEN_STAT1 0x0000688c +#define BNX_HC_STAT_GEN_STAT2 0x00006890 +#define BNX_HC_STAT_GEN_STAT3 0x00006894 +#define BNX_HC_STAT_GEN_STAT4 0x00006898 +#define BNX_HC_STAT_GEN_STAT5 0x0000689c +#define BNX_HC_STAT_GEN_STAT6 0x000068a0 +#define BNX_HC_STAT_GEN_STAT7 0x000068a4 +#define BNX_HC_STAT_GEN_STAT8 0x000068a8 +#define BNX_HC_STAT_GEN_STAT9 0x000068ac +#define BNX_HC_STAT_GEN_STAT10 0x000068b0 +#define BNX_HC_STAT_GEN_STAT11 0x000068b4 +#define BNX_HC_STAT_GEN_STAT12 0x000068b8 +#define BNX_HC_STAT_GEN_STAT13 0x000068bc +#define BNX_HC_STAT_GEN_STAT14 0x000068c0 +#define BNX_HC_STAT_GEN_STAT15 0x000068c4 +#define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8 +#define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc +#define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0 +#define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4 +#define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8 +#define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc +#define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0 +#define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4 +#define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8 +#define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec +#define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0 +#define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4 +#define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8 +#define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc +#define BNX_HC_STAT_GEN_STAT_AC14 0x00006900 +#define BNX_HC_STAT_GEN_STAT_AC15 0x00006904 +#define BNX_HC_VIS 0x00006908 +#define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) +#define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) +#define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) +#define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) +#define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12) +#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) +#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) +#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) +#define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) + +#define BNX_HC_VIS_1 0x0000690c +#define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4) +#define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) +#define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) +#define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5) +#define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) +#define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) +#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) +#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) +#define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) +#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) +#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) +#define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) +#define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) +#define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) +#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) +#define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) +#define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23) +#define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) +#define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) +#define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) +#define BNX_HC_VIS_1_INT_B (1L<<27) + +#define BNX_HC_DEBUG_VECT_PEEK 0x00006910 +#define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + + + +/* + * txp_reg definition + * offset: 0x40000 + */ +#define BNX_TXP_CPU_MODE 0x00045000 +#define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_TXP_CPU_STATE 0x00045004 +#define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_TXP_CPU_EVENT_MASK 0x00045008 +#define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c +#define BNX_TXP_CPU_INSTRUCTION 0x00045020 +#define BNX_TXP_CPU_DATA_ACCESS 0x00045024 +#define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028 +#define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c +#define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 +#define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034 +#define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 +#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_TXP_CPU_REG_FILE 0x00045200 +#define BNX_TXP_FTQ_DATA 0x000453c0 +#define BNX_TXP_FTQ_CMD 0x000453f8 +#define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_TXP_FTQ_CMD_POP (1L<<30) +#define BNX_TXP_FTQ_CMD_BUSY (1L<<31) + +#define BNX_TXP_FTQ_CTL 0x000453fc +#define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_TXP_SCRATCH 0x00060000 + + +/* + * tpat_reg definition + * offset: 0x80000 + */ +#define BNX_TPAT_CPU_MODE 0x00085000 +#define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_TPAT_CPU_STATE 0x00085004 +#define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_TPAT_CPU_EVENT_MASK 0x00085008 +#define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c +#define BNX_TPAT_CPU_INSTRUCTION 0x00085020 +#define BNX_TPAT_CPU_DATA_ACCESS 0x00085024 +#define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 +#define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c +#define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 +#define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034 +#define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 +#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_TPAT_CPU_REG_FILE 0x00085200 +#define BNX_TPAT_FTQ_DATA 0x000853c0 +#define BNX_TPAT_FTQ_CMD 0x000853f8 +#define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_TPAT_FTQ_CMD_POP (1L<<30) +#define BNX_TPAT_FTQ_CMD_BUSY (1L<<31) + +#define BNX_TPAT_FTQ_CTL 0x000853fc +#define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_TPAT_SCRATCH 0x000a0000 + + +/* + * rxp_reg definition + * offset: 0xc0000 + */ +#define BNX_RXP_CPU_MODE 0x000c5000 +#define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_RXP_CPU_STATE 0x000c5004 +#define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_RXP_CPU_EVENT_MASK 0x000c5008 +#define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c +#define BNX_RXP_CPU_INSTRUCTION 0x000c5020 +#define BNX_RXP_CPU_DATA_ACCESS 0x000c5024 +#define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 +#define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c +#define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 +#define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034 +#define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 +#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_RXP_CPU_REG_FILE 0x000c5200 +#define BNX_RXP_CFTQ_DATA 0x000c5380 +#define BNX_RXP_CFTQ_CMD 0x000c53b8 +#define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10) +#define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25) +#define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26) +#define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28) +#define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_RXP_CFTQ_CMD_POP (1L<<30) +#define BNX_RXP_CFTQ_CMD_BUSY (1L<<31) + +#define BNX_RXP_CFTQ_CTL 0x000c53bc +#define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0) +#define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1) +#define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_RXP_FTQ_DATA 0x000c53c0 +#define BNX_RXP_FTQ_CMD 0x000c53f8 +#define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_RXP_FTQ_CMD_POP (1L<<30) +#define BNX_RXP_FTQ_CMD_BUSY (1L<<31) + +#define BNX_RXP_FTQ_CTL 0x000c53fc +#define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_RXP_SCRATCH 0x000e0000 + + +/* + * com_reg definition + * offset: 0x100000 + */ +#define BNX_COM_CPU_MODE 0x00105000 +#define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_COM_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_COM_CPU_STATE 0x00105004 +#define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_COM_CPU_EVENT_MASK 0x00105008 +#define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c +#define BNX_COM_CPU_INSTRUCTION 0x00105020 +#define BNX_COM_CPU_DATA_ACCESS 0x00105024 +#define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028 +#define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c +#define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 +#define BNX_COM_CPU_HW_BREAKPOINT 0x00105034 +#define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038 +#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048 +#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_COM_CPU_REG_FILE 0x00105200 +#define BNX_COM_COMXQ_FTQ_DATA 0x00105340 +#define BNX_COM_COMXQ_FTQ_CMD 0x00105378 +#define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30) +#define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX_COM_COMXQ_FTQ_CTL 0x0010537c +#define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_COM_COMTQ_FTQ_DATA 0x00105380 +#define BNX_COM_COMTQ_FTQ_CMD 0x001053b8 +#define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30) +#define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX_COM_COMTQ_FTQ_CTL 0x001053bc +#define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_COM_COMQ_FTQ_DATA 0x001053c0 +#define BNX_COM_COMQ_FTQ_CMD 0x001053f8 +#define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30) +#define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX_COM_COMQ_FTQ_CTL 0x001053fc +#define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_COM_SCRATCH 0x00120000 + + +/* + * cp_reg definition + * offset: 0x180000 + */ +#define BNX_CP_CPU_MODE 0x00185000 +#define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_CP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_CP_CPU_STATE 0x00185004 +#define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_CP_CPU_EVENT_MASK 0x00185008 +#define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c +#define BNX_CP_CPU_INSTRUCTION 0x00185020 +#define BNX_CP_CPU_DATA_ACCESS 0x00185024 +#define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028 +#define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c +#define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 +#define BNX_CP_CPU_HW_BREAKPOINT 0x00185034 +#define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038 +#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048 +#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_CP_CPU_REG_FILE 0x00185200 +#define BNX_CP_CPQ_FTQ_DATA 0x001853c0 +#define BNX_CP_CPQ_FTQ_CMD 0x001853f8 +#define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30) +#define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX_CP_CPQ_FTQ_CTL 0x001853fc +#define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_CP_SCRATCH 0x001a0000 + + +/* + * mcp_reg definition + * offset: 0x140000 + */ +#define BNX_MCP_CPU_MODE 0x00145000 +#define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0) +#define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1) +#define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10) +#define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BNX_MCP_CPU_STATE 0x00145004 +#define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0) +#define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BNX_MCP_CPU_EVENT_MASK 0x00145008 +#define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c +#define BNX_MCP_CPU_INSTRUCTION 0x00145020 +#define BNX_MCP_CPU_DATA_ACCESS 0x00145024 +#define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028 +#define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c +#define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 +#define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034 +#define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 +#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BNX_MCP_CPU_REG_FILE 0x00145200 +#define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0 +#define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8 +#define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30) +#define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) + +#define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc +#define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BNX_MCP_ROM 0x00150000 +#define BNX_MCP_SCRATCH 0x00160000 + +#define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH +#define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 +#define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000 +#define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff +#define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 + +#define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4 +#define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8 + +/****************************************************************************/ +/* End machine generated definitions. */ +/****************************************************************************/ + +#define NUM_MC_HASH_REGISTERS 8 + + +/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ +#define PHY_BCM5706_PHY_ID 0x00206160 + +#define PHY_ID(id) ((id) & 0xfffffff0) +#define PHY_REV_ID(id) ((id) & 0xf) + +/* 5708 Serdes PHY registers */ + +#define BCM5708S_UP1 0xb + +#define BCM5708S_UP1_2G5 0x1 + +#define BCM5708S_BLK_ADDR 0x1f + +#define BCM5708S_BLK_ADDR_DIG 0x0000 +#define BCM5708S_BLK_ADDR_DIG3 0x0002 +#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 + +/* Digital Block */ +#define BCM5708S_1000X_CTL1 0x10 + +#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 +#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 + +#define BCM5708S_1000X_CTL2 0x11 + +#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 + +#define BCM5708S_1000X_STAT1 0x14 + +#define BCM5708S_1000X_STAT1_SGMII 0x0001 +#define BCM5708S_1000X_STAT1_LINK 0x0002 +#define BCM5708S_1000X_STAT1_FD 0x0004 +#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 +#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 +#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 +#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 +#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 +#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 +#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 + +/* Digital3 Block */ +#define BCM5708S_DIG_3_0 0x10 + +#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 + +/* Tx/Misc Block */ +#define BCM5708S_TX_ACTL1 0x15 + +#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 + +#define BCM5708S_TX_ACTL3 0x17 + +#define RX_COPY_THRESH 92 + +#define DMA_READ_CHANS 5 +#define DMA_WRITE_CHANS 3 + +/* Use the natural page size of the host CPU. */ +/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ +#define BCM_PAGE_BITS PAGE_SHIFT +#define BCM_PAGE_SIZE PAGE_SIZE + +#define TX_PAGES 2 +#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) +#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) +#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) +#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) +#define MAX_TX_BD (TOTAL_TX_BD - 1) +#define BNX_TX_SLACK_SPACE 16 + +#define RX_PAGES 2 +#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) +#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) +#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) +#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) +#define MAX_RX_BD (TOTAL_RX_BD - 1) +#define BNX_RX_SLACK_SPACE (MAX_RX_BD - 8) + +#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ + (USABLE_TX_BD_PER_PAGE - 1)) ? \ + (x) + 2 : (x) + 1 + +#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) + +#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) +#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) + +#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ + (USABLE_RX_BD_PER_PAGE - 1)) ? \ + (x) + 2 : (x) + 1 + +#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) + +#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) +#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) + +/* Context size. */ +#define CTX_SHIFT 7 +#define CTX_SIZE (1 << CTX_SHIFT) +#define CTX_MASK (CTX_SIZE - 1) +#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) +#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) + +#define PHY_CTX_SHIFT 6 +#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) +#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) +#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) +#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) + +#define MB_KERNEL_CTX_SHIFT 8 +#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) +#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) +#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) + +#define MAX_CID_CNT 0x4000 +#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) +#define INVALID_CID_ADDR 0xffffffff + +#define TX_CID 16 +#define RX_CID 0 + +#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) +#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) + +/****************************************************************************/ +/* BNX Processor Firmwware Load Definitions */ +/****************************************************************************/ + +struct cpu_reg { + u_int32_t mode; + u_int32_t mode_value_halt; + u_int32_t mode_value_sstep; + + u_int32_t state; + u_int32_t state_value_clear; + + u_int32_t gpr0; + u_int32_t evmask; + u_int32_t pc; + u_int32_t inst; + u_int32_t bp; + + u_int32_t spad_base; + + u_int32_t mips_view_base; +}; + +struct fw_info { + u_int32_t ver_major; + u_int32_t ver_minor; + u_int32_t ver_fix; + + u_int32_t start_addr; + + /* Text section. */ + u_int32_t text_addr; + u_int32_t text_len; + u_int32_t text_index; + u_int32_t *text; + + /* Data section. */ + u_int32_t data_addr; + u_int32_t data_len; + u_int32_t data_index; + u_int32_t *data; + + /* SBSS section. */ + u_int32_t sbss_addr; + u_int32_t sbss_len; + u_int32_t sbss_index; + u_int32_t *sbss; + + /* BSS section. */ + u_int32_t bss_addr; + u_int32_t bss_len; + u_int32_t bss_index; + u_int32_t *bss; + + /* Read-only section. */ + u_int32_t rodata_addr; + u_int32_t rodata_len; + u_int32_t rodata_index; + u_int32_t *rodata; +}; + +#define RV2P_PROC1 0 +#define RV2P_PROC2 1 + +#define BNX_MIREG(x) ((x & 0x1F) << 16) +#define BNX_MIPHY(x) ((x & 0x1F) << 21) +#define BNX_PHY_TIMEOUT 50 + +#define BNX_NVRAM_SIZE 0x200 +#define BNX_NVRAM_MAGIC 0x669955aa +#define BNX_CRC32_RESIDUAL 0xdebb20e3 + +#define BNX_TX_TIMEOUT 5 + +#define BNX_MAX_SEGMENTS 8 +#define BNX_DMA_ALIGN 8 +#define BNX_DMA_BOUNDARY 0 + +#define BNX_MIN_MTU 60 +#define BNX_MIN_ETHER_MTU 64 + +#define BNX_MAX_STD_MTU 1500 +#define BNX_MAX_STD_ETHER_MTU 1518 +#define BNX_MAX_STD_ETHER_MTU_VLAN 1522 + +#define BNX_MAX_JUMBO_MTU 9000 +#define BNX_MAX_JUMBO_ETHER_MTU 9018 +#define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022 + +#define BNX_MAX_MRU 9216 + +/****************************************************************************/ +/* BNX Device State Data Structure */ +/****************************************************************************/ + +#define BNX_STATUS_BLK_SZ sizeof(struct status_block) +#define BNX_STATS_BLK_SZ sizeof(struct statistics_block) +#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE +#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE +/* + * Mbuf pointers. We need these to keep track of the virtual addresses + * of our mbuf chains since we can only convert from physical to virtual, + * not the other way around. + */ + +struct bnx_dmamap_arg { + struct bnx_softc *sc; /* Pointer back to device context */ + bus_addr_t busaddr; /* Physical address of mapped memory */ + u_int32_t tx_flags; /* Flags for frame transmit */ + u_int16_t prod; + u_int16_t chain_prod; + int maxsegs; /* Max segments supported for this mapped memory */ + u_int32_t prod_bseq; + struct tx_bd *tx_chain[TX_PAGES]; +}; + + +struct bnx_softc +{ + struct device bnx_dev; /* Parent device handle */ + struct ethercom ethercom; + struct pci_attach_args bnx_pa; + + struct ifmedia bnx_ifmedia; /* TBI media info */ + + bus_space_tag_t bnx_btag; /* Device bus tag */ + bus_space_handle_t bnx_bhandle; /* Device bus handle */ + bus_size_t bnx_size; + + void *bnx_intrhand; /* Interrupt handler */ + void *bnx_powerhook; + void *bnx_shutdownhook; + + /* ASIC Chip ID. */ + u_int32_t bnx_chipid; + + /* General controller flags. */ + u_int32_t bnx_flags; +#define BNX_PCIX_FLAG 0x01 +#define BNX_PCI_32BIT_FLAG 0x02 +#define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */ +#define BNX_NO_WOL_FLAG 0x08 +#define BNX_USING_DAC_FLAG 0x10 +#define BNX_USING_MSI_FLAG 0x20 +#define BNX_MFW_ENABLE_FLAG 0x40 + + /* PHY specific flags. */ + u_int32_t bnx_phy_flags; +#define BNX_PHY_SERDES_FLAG 1 +#define BNX_PHY_CRC_FIX_FLAG 2 +#define BNX_PHY_PARALLEL_DETECT_FLAG 4 +#define BNX_PHY_2_5G_CAPABLE_FLAG 8 +#define BNX_PHY_INT_MODE_MASK_FLAG 0x300 +#define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 +#define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200 + + int bnx_if_flags; + + u_int16_t bus_speed_mhz; /* PCI bus speed */ + struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ + u_int32_t bnx_flash_size; /* Flash NVRAM size */ + u_int32_t bnx_shmem_base; /* Shared Memory base address */ + char * bnx_name; /* Name string */ + + /* Tracks the version of bootcode firmware. */ + u_int32_t bnx_fw_ver; + + /* Tracks the state of the firmware. 0 = Running while any */ + /* other value indicates that the firmware is not responding. */ + u_int16_t bnx_fw_timed_out; + + /* An incrementing sequence used to coordinate messages passed */ + /* from the driver to the firmware. */ + u_int16_t bnx_fw_wr_seq; + + /* An incrementing sequence used to let the firmware know that */ + /* the driver is still operating. Without the pulse, management */ + /* firmware such as IPMI or UMP will operate in OS absent state. */ + u_int16_t bnx_fw_drv_pulse_wr_seq; + + /* Ethernet MAC address. */ + u_char eaddr[6]; + + /* These setting are used by the host coalescing (HC) block to */ + /* to control how often the status block, statistics block and */ + /* interrupts are generated. */ + u_int16_t bnx_tx_quick_cons_trip_int; + u_int16_t bnx_tx_quick_cons_trip; + u_int16_t bnx_rx_quick_cons_trip_int; + u_int16_t bnx_rx_quick_cons_trip; + u_int16_t bnx_comp_prod_trip_int; + u_int16_t bnx_comp_prod_trip; + u_int16_t bnx_tx_ticks_int; + u_int16_t bnx_tx_ticks; + u_int16_t bnx_rx_ticks_int; + u_int16_t bnx_rx_ticks; + u_int16_t bnx_com_ticks_int; + u_int16_t bnx_com_ticks; + u_int16_t bnx_cmd_ticks_int; + u_int16_t bnx_cmd_ticks; + u_int32_t bnx_stats_ticks; + + /* The address of the integrated PHY on the MII bus. */ + int bnx_phy_addr; + + /* The device handle for the MII bus child device. */ + struct mii_data bnx_mii; + + /* Driver maintained TX chain pointers and byte counter. */ + u_int16_t rx_prod; + u_int16_t rx_cons; + u_int32_t rx_prod_bseq; /* Counts the bytes used. */ + u_int16_t tx_prod; + u_int16_t tx_cons; + u_int32_t tx_prod_bseq; /* Counts the bytes used. */ + + int bnx_link; + struct callout bnx_timeout; + + /* Frame size and mbuf allocation size for RX frames. */ + u_int32_t max_frame_size; + int mbuf_alloc_size; + + /* Receive mode settings (i.e promiscuous, multicast, etc.). */ + u_int32_t rx_mode; + + /* Bus tag for the bnx controller. */ + bus_dma_tag_t bnx_dmatag; + + /* H/W maintained TX buffer descriptor chain structure. */ + bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; + int tx_bd_chain_rseg[TX_PAGES]; + bus_dmamap_t tx_bd_chain_map[TX_PAGES]; + struct tx_bd *tx_bd_chain[TX_PAGES]; + bus_addr_t tx_bd_chain_paddr[TX_PAGES]; + + /* H/W maintained RX buffer descriptor chain structure. */ + bus_dma_segment_t rx_bd_chain_seg[TX_PAGES]; + int rx_bd_chain_rseg[TX_PAGES]; + bus_dmamap_t rx_bd_chain_map[RX_PAGES]; + struct rx_bd *rx_bd_chain[RX_PAGES]; + bus_addr_t rx_bd_chain_paddr[RX_PAGES]; + + /* H/W maintained status block. */ + bus_dma_segment_t status_seg; + int status_rseg; + bus_dmamap_t status_map; + struct status_block *status_block; /* virtual address */ + bus_addr_t status_block_paddr; /* Physical address */ + + /* Driver maintained status block values. */ + u_int16_t last_status_idx; + u_int16_t hw_rx_cons; + u_int16_t hw_tx_cons; + + /* H/W maintained statistics block. */ + bus_dma_segment_t stats_seg; + int stats_rseg; + bus_dmamap_t stats_map; + struct statistics_block *stats_block; /* Virtual address */ + bus_addr_t stats_block_paddr; /* Physical address */ + + /* Bus tag for RX/TX mbufs. */ + bus_dma_segment_t rx_mbuf_seg; + int rx_mbuf_rseg; + bus_dma_segment_t tx_mbuf_seg; + int tx_mbuf_rseg; + + /* S/W maintained mbuf TX chain structure. */ + bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; + struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; + + /* S/W maintained mbuf RX chain structure. */ + bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; + struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; + + /* Track the number of rx_bd and tx_bd's in use. */ + u_int16_t free_rx_bd; + u_int16_t used_tx_bd; + + /* Provides access to hardware statistics through sysctl. */ + u_int64_t stat_IfHCInOctets; + u_int64_t stat_IfHCInBadOctets; + u_int64_t stat_IfHCOutOctets; + u_int64_t stat_IfHCOutBadOctets; + u_int64_t stat_IfHCInUcastPkts; + u_int64_t stat_IfHCInMulticastPkts; + u_int64_t stat_IfHCInBroadcastPkts; + u_int64_t stat_IfHCOutUcastPkts; + u_int64_t stat_IfHCOutMulticastPkts; + u_int64_t stat_IfHCOutBroadcastPkts; + + u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u_int32_t stat_Dot3StatsCarrierSenseErrors; + u_int32_t stat_Dot3StatsFCSErrors; + u_int32_t stat_Dot3StatsAlignmentErrors; + u_int32_t stat_Dot3StatsSingleCollisionFrames; + u_int32_t stat_Dot3StatsMultipleCollisionFrames; + u_int32_t stat_Dot3StatsDeferredTransmissions; + u_int32_t stat_Dot3StatsExcessiveCollisions; + u_int32_t stat_Dot3StatsLateCollisions; + u_int32_t stat_EtherStatsCollisions; + u_int32_t stat_EtherStatsFragments; + u_int32_t stat_EtherStatsJabbers; + u_int32_t stat_EtherStatsUndersizePkts; + u_int32_t stat_EtherStatsOverrsizePkts; + u_int32_t stat_EtherStatsPktsRx64Octets; + u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; + u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; + u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; + u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; + u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; + u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; + u_int32_t stat_EtherStatsPktsTx64Octets; + u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; + u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; + u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; + u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; + u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; + u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; + u_int32_t stat_XonPauseFramesReceived; + u_int32_t stat_XoffPauseFramesReceived; + u_int32_t stat_OutXonSent; + u_int32_t stat_OutXoffSent; + u_int32_t stat_FlowControlDone; + u_int32_t stat_MacControlFramesReceived; + u_int32_t stat_XoffStateEntered; + u_int32_t stat_IfInFramesL2FilterDiscards; + u_int32_t stat_IfInRuleCheckerDiscards; + u_int32_t stat_IfInFTQDiscards; + u_int32_t stat_IfInMBUFDiscards; + u_int32_t stat_IfInRuleCheckerP4Hit; + u_int32_t stat_CatchupInRuleCheckerDiscards; + u_int32_t stat_CatchupInFTQDiscards; + u_int32_t stat_CatchupInMBUFDiscards; + u_int32_t stat_CatchupInRuleCheckerP4Hit; + +#ifdef BNX_DEBUG + /* Track the number of enqueued mbufs. */ + int tx_mbuf_alloc; + int rx_mbuf_alloc; + + /* Track how many and what type of interrupts are generated. */ + u_int32_t interrupts_generated; + u_int32_t interrupts_handled; + u_int32_t rx_interrupts; + u_int32_t tx_interrupts; + + u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ + u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ + u_int32_t mbuf_alloc_failed; /* Mbuf allocation failure counter. */ + u_int32_t l2fhdr_status_errors; + u_int32_t unexpected_attentions; + u_int32_t lost_status_block_updates; +#endif +}; + +#endif /* #ifndef _BNX_H_DEFINED */