Add basic glue for AArch64, including not-yet-used assembler files.
This commit is contained in:
joerg
parent
11ff370a53
commit
e9e26132dd
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# $NetBSD: Makefile,v 1.1 2016/10/17 00:24:13 joerg Exp $
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.include "bsd.own.mk"
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CRYPTODIST=${NETBSDSRCDIR}/crypto
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.include "${NETBSDSRCDIR}/crypto/Makefile.openssl"
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regen:
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for i in ${OPENSSLSRC}/crypto/aes/asm/aesv8-armx.pl \
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${OPENSSLSRC}/crypto/modes/asm/ghashv8-armx.pl \
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${OPENSSLSRC}/crypto/sha/asm/sha1-armv8.pl; do \
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j=$$(basename $$i .pl).S; \
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perl $$i > $$j; \
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done
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.PATH.S: ${.PARSEDIR}
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#AES_SRCS = aesv8-armx.S
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#AESCPPFLAGS = -DAES_ASM
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.include "../../aes.inc"
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@ -0,0 +1,754 @@
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#include "arm_arch.h"
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#if __ARM_MAX_ARCH__>=7
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.text
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.arch armv7-a
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.fpu neon
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.code 32
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.align 5
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rcon:
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.long 0x01,0x01,0x01,0x01
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.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d @ rotate-n-splat
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.long 0x1b,0x1b,0x1b,0x1b
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.globl aes_v8_set_encrypt_key
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.type aes_v8_set_encrypt_key,%function
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.align 5
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aes_v8_set_encrypt_key:
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.Lenc_key:
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mov r3,#-1
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cmp r0,#0
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beq .Lenc_key_abort
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cmp r2,#0
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beq .Lenc_key_abort
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mov r3,#-2
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cmp r1,#128
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blt .Lenc_key_abort
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cmp r1,#256
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bgt .Lenc_key_abort
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tst r1,#0x3f
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bne .Lenc_key_abort
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adr r3,rcon
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cmp r1,#192
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veor q0,q0,q0
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vld1.8 {q3},[r0]!
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mov r1,#8 @ reuse r1
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vld1.32 {q1,q2},[r3]!
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blt .Loop128
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beq .L192
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b .L256
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.align 4
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.Loop128:
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vtbl.8 d20,{q3},d4
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vtbl.8 d21,{q3},d5
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vext.8 q9,q0,q3,#12
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vst1.32 {q3},[r2]!
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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subs r1,r1,#1
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q10,q10,q1
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veor q3,q3,q9
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vshl.u8 q1,q1,#1
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veor q3,q3,q10
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bne .Loop128
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vld1.32 {q1},[r3]
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vtbl.8 d20,{q3},d4
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vtbl.8 d21,{q3},d5
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vext.8 q9,q0,q3,#12
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vst1.32 {q3},[r2]!
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q10,q10,q1
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veor q3,q3,q9
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vshl.u8 q1,q1,#1
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veor q3,q3,q10
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vtbl.8 d20,{q3},d4
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vtbl.8 d21,{q3},d5
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vext.8 q9,q0,q3,#12
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vst1.32 {q3},[r2]!
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q10,q10,q1
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veor q3,q3,q9
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veor q3,q3,q10
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vst1.32 {q3},[r2]
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add r2,r2,#0x50
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mov r12,#10
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b .Ldone
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.align 4
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.L192:
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vld1.8 {d16},[r0]!
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vmov.i8 q10,#8 @ borrow q10
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vst1.32 {q3},[r2]!
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vsub.i8 q2,q2,q10 @ adjust the mask
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.Loop192:
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vtbl.8 d20,{q8},d4
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vtbl.8 d21,{q8},d5
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vext.8 q9,q0,q3,#12
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vst1.32 {d16},[r2]!
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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subs r1,r1,#1
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vdup.32 q9,d7[1]
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veor q9,q9,q8
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veor q10,q10,q1
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vext.8 q8,q0,q8,#12
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vshl.u8 q1,q1,#1
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veor q8,q8,q9
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veor q3,q3,q10
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veor q8,q8,q10
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vst1.32 {q3},[r2]!
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bne .Loop192
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mov r12,#12
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add r2,r2,#0x20
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b .Ldone
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.align 4
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.L256:
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vld1.8 {q8},[r0]
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mov r1,#7
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mov r12,#14
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vst1.32 {q3},[r2]!
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.Loop256:
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vtbl.8 d20,{q8},d4
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vtbl.8 d21,{q8},d5
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vext.8 q9,q0,q3,#12
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vst1.32 {q8},[r2]!
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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subs r1,r1,#1
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q3,q3,q9
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vext.8 q9,q0,q9,#12
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veor q10,q10,q1
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veor q3,q3,q9
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vshl.u8 q1,q1,#1
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veor q3,q3,q10
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vst1.32 {q3},[r2]!
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beq .Ldone
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vdup.32 q10,d7[1]
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vext.8 q9,q0,q8,#12
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.byte 0x00,0x43,0xf0,0xf3 @ aese q10,q0
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veor q8,q8,q9
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vext.8 q9,q0,q9,#12
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veor q8,q8,q9
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vext.8 q9,q0,q9,#12
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veor q8,q8,q9
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veor q8,q8,q10
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b .Loop256
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.Ldone:
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str r12,[r2]
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mov r3,#0
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.Lenc_key_abort:
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mov r0,r3 @ return value
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bx lr
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.size aes_v8_set_encrypt_key,.-aes_v8_set_encrypt_key
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.globl aes_v8_set_decrypt_key
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.type aes_v8_set_decrypt_key,%function
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.align 5
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aes_v8_set_decrypt_key:
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stmdb sp!,{r4,lr}
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bl .Lenc_key
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cmp r0,#0
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bne .Ldec_key_abort
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sub r2,r2,#240 @ restore original r2
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mov r4,#-16
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add r0,r2,r12,lsl#4 @ end of key schedule
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vld1.32 {q0},[r2]
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vld1.32 {q1},[r0]
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vst1.32 {q0},[r0],r4
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vst1.32 {q1},[r2]!
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.Loop_imc:
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vld1.32 {q0},[r2]
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vld1.32 {q1},[r0]
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.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
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.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
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vst1.32 {q0},[r0],r4
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vst1.32 {q1},[r2]!
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cmp r0,r2
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bhi .Loop_imc
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vld1.32 {q0},[r2]
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.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
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vst1.32 {q0},[r0]
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eor r0,r0,r0 @ return value
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.Ldec_key_abort:
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ldmia sp!,{r4,pc}
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.size aes_v8_set_decrypt_key,.-aes_v8_set_decrypt_key
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.globl aes_v8_encrypt
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.type aes_v8_encrypt,%function
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.align 5
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aes_v8_encrypt:
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ldr r3,[r2,#240]
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vld1.32 {q0},[r2]!
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vld1.8 {q2},[r0]
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sub r3,r3,#2
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vld1.32 {q1},[r2]!
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.Loop_enc:
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.byte 0x00,0x43,0xb0,0xf3 @ aese q2,q0
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.byte 0x84,0x43,0xb0,0xf3 @ aesmc q2,q2
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vld1.32 {q0},[r2]!
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subs r3,r3,#2
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.byte 0x02,0x43,0xb0,0xf3 @ aese q2,q1
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.byte 0x84,0x43,0xb0,0xf3 @ aesmc q2,q2
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vld1.32 {q1},[r2]!
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bgt .Loop_enc
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.byte 0x00,0x43,0xb0,0xf3 @ aese q2,q0
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.byte 0x84,0x43,0xb0,0xf3 @ aesmc q2,q2
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vld1.32 {q0},[r2]
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.byte 0x02,0x43,0xb0,0xf3 @ aese q2,q1
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veor q2,q2,q0
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vst1.8 {q2},[r1]
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bx lr
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.size aes_v8_encrypt,.-aes_v8_encrypt
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.globl aes_v8_decrypt
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.type aes_v8_decrypt,%function
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.align 5
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aes_v8_decrypt:
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ldr r3,[r2,#240]
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vld1.32 {q0},[r2]!
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vld1.8 {q2},[r0]
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sub r3,r3,#2
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vld1.32 {q1},[r2]!
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.Loop_dec:
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.byte 0x40,0x43,0xb0,0xf3 @ aesd q2,q0
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.byte 0xc4,0x43,0xb0,0xf3 @ aesimc q2,q2
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vld1.32 {q0},[r2]!
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subs r3,r3,#2
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.byte 0x42,0x43,0xb0,0xf3 @ aesd q2,q1
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.byte 0xc4,0x43,0xb0,0xf3 @ aesimc q2,q2
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vld1.32 {q1},[r2]!
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bgt .Loop_dec
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.byte 0x40,0x43,0xb0,0xf3 @ aesd q2,q0
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.byte 0xc4,0x43,0xb0,0xf3 @ aesimc q2,q2
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vld1.32 {q0},[r2]
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.byte 0x42,0x43,0xb0,0xf3 @ aesd q2,q1
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veor q2,q2,q0
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vst1.8 {q2},[r1]
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bx lr
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.size aes_v8_decrypt,.-aes_v8_decrypt
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.globl aes_v8_cbc_encrypt
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.type aes_v8_cbc_encrypt,%function
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.align 5
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aes_v8_cbc_encrypt:
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mov ip,sp
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stmdb sp!,{r4-r8,lr}
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vstmdb sp!,{d8-d15} @ ABI specification says so
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ldmia ip,{r4-r5} @ load remaining args
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subs r2,r2,#16
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mov r8,#16
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blo .Lcbc_abort
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moveq r8,#0
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cmp r5,#0 @ en- or decrypting?
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ldr r5,[r3,#240]
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and r2,r2,#-16
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vld1.8 {q6},[r4]
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vld1.8 {q0},[r0],r8
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vld1.32 {q8-q9},[r3] @ load key schedule...
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sub r5,r5,#6
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add r7,r3,r5,lsl#4 @ pointer to last 7 round keys
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sub r5,r5,#2
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vld1.32 {q10-q11},[r7]!
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vld1.32 {q12-q13},[r7]!
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vld1.32 {q14-q15},[r7]!
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vld1.32 {q7},[r7]
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add r7,r3,#32
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mov r6,r5
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beq .Lcbc_dec
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cmp r5,#2
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veor q0,q0,q6
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veor q5,q8,q7
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beq .Lcbc_enc128
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vld1.32 {q2-q3},[r7]
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add r7,r3,#16
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add r6,r3,#16*4
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add r12,r3,#16*5
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.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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add r14,r3,#16*6
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add r3,r3,#16*7
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b .Lenter_cbc_enc
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.align 4
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.Loop_cbc_enc:
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.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vst1.8 {q6},[r1]!
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.Lenter_cbc_enc:
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.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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.byte 0x04,0x03,0xb0,0xf3 @ aese q0,q2
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.32 {q8},[r6]
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cmp r5,#4
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.byte 0x06,0x03,0xb0,0xf3 @ aese q0,q3
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.32 {q9},[r12]
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beq .Lcbc_enc192
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.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.32 {q8},[r14]
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.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.32 {q9},[r3]
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nop
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.Lcbc_enc192:
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.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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subs r2,r2,#16
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.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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moveq r8,#0
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.byte 0x24,0x03,0xb0,0xf3 @ aese q0,q10
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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.byte 0x26,0x03,0xb0,0xf3 @ aese q0,q11
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.8 {q8},[r0],r8
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.byte 0x28,0x03,0xb0,0xf3 @ aese q0,q12
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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veor q8,q8,q5
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.byte 0x2a,0x03,0xb0,0xf3 @ aese q0,q13
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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vld1.32 {q9},[r7] @ re-pre-load rndkey[1]
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.byte 0x2c,0x03,0xb0,0xf3 @ aese q0,q14
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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.byte 0x2e,0x03,0xb0,0xf3 @ aese q0,q15
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veor q6,q0,q7
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bhs .Loop_cbc_enc
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vst1.8 {q6},[r1]!
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b .Lcbc_done
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.align 5
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.Lcbc_enc128:
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vld1.32 {q2-q3},[r7]
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.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
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.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
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b .Lenter_cbc_enc128
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.Loop_cbc_enc128:
|
||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
vst1.8 {q6},[r1]!
|
||||
.Lenter_cbc_enc128:
|
||||
.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
subs r2,r2,#16
|
||||
.byte 0x04,0x03,0xb0,0xf3 @ aese q0,q2
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
moveq r8,#0
|
||||
.byte 0x06,0x03,0xb0,0xf3 @ aese q0,q3
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x24,0x03,0xb0,0xf3 @ aese q0,q10
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x26,0x03,0xb0,0xf3 @ aese q0,q11
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
vld1.8 {q8},[r0],r8
|
||||
.byte 0x28,0x03,0xb0,0xf3 @ aese q0,q12
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x2a,0x03,0xb0,0xf3 @ aese q0,q13
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x2c,0x03,0xb0,0xf3 @ aese q0,q14
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
veor q8,q8,q5
|
||||
.byte 0x2e,0x03,0xb0,0xf3 @ aese q0,q15
|
||||
veor q6,q0,q7
|
||||
bhs .Loop_cbc_enc128
|
||||
|
||||
vst1.8 {q6},[r1]!
|
||||
b .Lcbc_done
|
||||
.align 5
|
||||
.Lcbc_dec:
|
||||
vld1.8 {q10},[r0]!
|
||||
subs r2,r2,#32 @ bias
|
||||
add r6,r5,#2
|
||||
vorr q3,q0,q0
|
||||
vorr q1,q0,q0
|
||||
vorr q11,q10,q10
|
||||
blo .Lcbc_dec_tail
|
||||
|
||||
vorr q1,q10,q10
|
||||
vld1.8 {q10},[r0]!
|
||||
vorr q2,q0,q0
|
||||
vorr q3,q1,q1
|
||||
vorr q11,q10,q10
|
||||
|
||||
.Loop3x_cbc_dec:
|
||||
.byte 0x60,0x03,0xb0,0xf3 @ aesd q0,q8
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x60,0x23,0xb0,0xf3 @ aesd q1,q8
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x60,0x43,0xf0,0xf3 @ aesd q10,q8
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.32 {q8},[r7]!
|
||||
subs r6,r6,#2
|
||||
.byte 0x62,0x03,0xb0,0xf3 @ aesd q0,q9
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x62,0x23,0xb0,0xf3 @ aesd q1,q9
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x62,0x43,0xf0,0xf3 @ aesd q10,q9
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.32 {q9},[r7]!
|
||||
bgt .Loop3x_cbc_dec
|
||||
|
||||
.byte 0x60,0x03,0xb0,0xf3 @ aesd q0,q8
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x60,0x23,0xb0,0xf3 @ aesd q1,q8
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x60,0x43,0xf0,0xf3 @ aesd q10,q8
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
veor q4,q6,q7
|
||||
subs r2,r2,#0x30
|
||||
veor q5,q2,q7
|
||||
movlo r6,r2 @ r6, r6, is zero at this point
|
||||
.byte 0x62,0x03,0xb0,0xf3 @ aesd q0,q9
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x62,0x23,0xb0,0xf3 @ aesd q1,q9
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x62,0x43,0xf0,0xf3 @ aesd q10,q9
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
veor q9,q3,q7
|
||||
add r0,r0,r6 @ r0 is adjusted in such way that
|
||||
@ at exit from the loop q1-q10
|
||||
@ are loaded with last "words"
|
||||
vorr q6,q11,q11
|
||||
mov r7,r3
|
||||
.byte 0x68,0x03,0xb0,0xf3 @ aesd q0,q12
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x68,0x23,0xb0,0xf3 @ aesd q1,q12
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x68,0x43,0xf0,0xf3 @ aesd q10,q12
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.8 {q2},[r0]!
|
||||
.byte 0x6a,0x03,0xb0,0xf3 @ aesd q0,q13
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x6a,0x23,0xb0,0xf3 @ aesd q1,q13
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x6a,0x43,0xf0,0xf3 @ aesd q10,q13
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.8 {q3},[r0]!
|
||||
.byte 0x6c,0x03,0xb0,0xf3 @ aesd q0,q14
|
||||
.byte 0xc0,0x03,0xb0,0xf3 @ aesimc q0,q0
|
||||
.byte 0x6c,0x23,0xb0,0xf3 @ aesd q1,q14
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x6c,0x43,0xf0,0xf3 @ aesd q10,q14
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.8 {q11},[r0]!
|
||||
.byte 0x6e,0x03,0xb0,0xf3 @ aesd q0,q15
|
||||
.byte 0x6e,0x23,0xb0,0xf3 @ aesd q1,q15
|
||||
.byte 0x6e,0x43,0xf0,0xf3 @ aesd q10,q15
|
||||
vld1.32 {q8},[r7]! @ re-pre-load rndkey[0]
|
||||
add r6,r5,#2
|
||||
veor q4,q4,q0
|
||||
veor q5,q5,q1
|
||||
veor q10,q10,q9
|
||||
vld1.32 {q9},[r7]! @ re-pre-load rndkey[1]
|
||||
vst1.8 {q4},[r1]!
|
||||
vorr q0,q2,q2
|
||||
vst1.8 {q5},[r1]!
|
||||
vorr q1,q3,q3
|
||||
vst1.8 {q10},[r1]!
|
||||
vorr q10,q11,q11
|
||||
bhs .Loop3x_cbc_dec
|
||||
|
||||
cmn r2,#0x30
|
||||
beq .Lcbc_done
|
||||
nop
|
||||
|
||||
.Lcbc_dec_tail:
|
||||
.byte 0x60,0x23,0xb0,0xf3 @ aesd q1,q8
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x60,0x43,0xf0,0xf3 @ aesd q10,q8
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.32 {q8},[r7]!
|
||||
subs r6,r6,#2
|
||||
.byte 0x62,0x23,0xb0,0xf3 @ aesd q1,q9
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x62,0x43,0xf0,0xf3 @ aesd q10,q9
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
vld1.32 {q9},[r7]!
|
||||
bgt .Lcbc_dec_tail
|
||||
|
||||
.byte 0x60,0x23,0xb0,0xf3 @ aesd q1,q8
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x60,0x43,0xf0,0xf3 @ aesd q10,q8
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
.byte 0x62,0x23,0xb0,0xf3 @ aesd q1,q9
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x62,0x43,0xf0,0xf3 @ aesd q10,q9
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
.byte 0x68,0x23,0xb0,0xf3 @ aesd q1,q12
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x68,0x43,0xf0,0xf3 @ aesd q10,q12
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
cmn r2,#0x20
|
||||
.byte 0x6a,0x23,0xb0,0xf3 @ aesd q1,q13
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x6a,0x43,0xf0,0xf3 @ aesd q10,q13
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
veor q5,q6,q7
|
||||
.byte 0x6c,0x23,0xb0,0xf3 @ aesd q1,q14
|
||||
.byte 0xc2,0x23,0xb0,0xf3 @ aesimc q1,q1
|
||||
.byte 0x6c,0x43,0xf0,0xf3 @ aesd q10,q14
|
||||
.byte 0xe4,0x43,0xf0,0xf3 @ aesimc q10,q10
|
||||
veor q9,q3,q7
|
||||
.byte 0x6e,0x23,0xb0,0xf3 @ aesd q1,q15
|
||||
.byte 0x6e,0x43,0xf0,0xf3 @ aesd q10,q15
|
||||
beq .Lcbc_dec_one
|
||||
veor q5,q5,q1
|
||||
veor q9,q9,q10
|
||||
vorr q6,q11,q11
|
||||
vst1.8 {q5},[r1]!
|
||||
vst1.8 {q9},[r1]!
|
||||
b .Lcbc_done
|
||||
|
||||
.Lcbc_dec_one:
|
||||
veor q5,q5,q10
|
||||
vorr q6,q11,q11
|
||||
vst1.8 {q5},[r1]!
|
||||
|
||||
.Lcbc_done:
|
||||
vst1.8 {q6},[r4]
|
||||
.Lcbc_abort:
|
||||
vldmia sp!,{d8-d15}
|
||||
ldmia sp!,{r4-r8,pc}
|
||||
.size aes_v8_cbc_encrypt,.-aes_v8_cbc_encrypt
|
||||
.globl aes_v8_ctr32_encrypt_blocks
|
||||
.type aes_v8_ctr32_encrypt_blocks,%function
|
||||
.align 5
|
||||
aes_v8_ctr32_encrypt_blocks:
|
||||
mov ip,sp
|
||||
stmdb sp!,{r4-r10,lr}
|
||||
vstmdb sp!,{d8-d15} @ ABI specification says so
|
||||
ldr r4, [ip] @ load remaining arg
|
||||
ldr r5,[r3,#240]
|
||||
|
||||
ldr r8, [r4, #12]
|
||||
vld1.32 {q0},[r4]
|
||||
|
||||
vld1.32 {q8-q9},[r3] @ load key schedule...
|
||||
sub r5,r5,#4
|
||||
mov r12,#16
|
||||
cmp r2,#2
|
||||
add r7,r3,r5,lsl#4 @ pointer to last 5 round keys
|
||||
sub r5,r5,#2
|
||||
vld1.32 {q12-q13},[r7]!
|
||||
vld1.32 {q14-q15},[r7]!
|
||||
vld1.32 {q7},[r7]
|
||||
add r7,r3,#32
|
||||
mov r6,r5
|
||||
movlo r12,#0
|
||||
#ifndef __ARMEB__
|
||||
rev r8, r8
|
||||
#endif
|
||||
vorr q1,q0,q0
|
||||
add r10, r8, #1
|
||||
vorr q10,q0,q0
|
||||
add r8, r8, #2
|
||||
vorr q6,q0,q0
|
||||
rev r10, r10
|
||||
vmov.32 d3[1],r10
|
||||
bls .Lctr32_tail
|
||||
rev r12, r8
|
||||
sub r2,r2,#3 @ bias
|
||||
vmov.32 d21[1],r12
|
||||
b .Loop3x_ctr32
|
||||
|
||||
.align 4
|
||||
.Loop3x_ctr32:
|
||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x20,0x23,0xb0,0xf3 @ aese q1,q8
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
.byte 0x20,0x43,0xf0,0xf3 @ aese q10,q8
|
||||
.byte 0xa4,0x43,0xf0,0xf3 @ aesmc q10,q10
|
||||
vld1.32 {q8},[r7]!
|
||||
subs r6,r6,#2
|
||||
.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x22,0x23,0xb0,0xf3 @ aese q1,q9
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
.byte 0x22,0x43,0xf0,0xf3 @ aese q10,q9
|
||||
.byte 0xa4,0x43,0xf0,0xf3 @ aesmc q10,q10
|
||||
vld1.32 {q9},[r7]!
|
||||
bgt .Loop3x_ctr32
|
||||
|
||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||
.byte 0x80,0x83,0xb0,0xf3 @ aesmc q4,q0
|
||||
.byte 0x20,0x23,0xb0,0xf3 @ aese q1,q8
|
||||
.byte 0x82,0xa3,0xb0,0xf3 @ aesmc q5,q1
|
||||
vld1.8 {q2},[r0]!
|
||||
vorr q0,q6,q6
|
||||
.byte 0x20,0x43,0xf0,0xf3 @ aese q10,q8
|
||||
.byte 0xa4,0x43,0xf0,0xf3 @ aesmc q10,q10
|
||||
vld1.8 {q3},[r0]!
|
||||
vorr q1,q6,q6
|
||||
.byte 0x22,0x83,0xb0,0xf3 @ aese q4,q9
|
||||
.byte 0x88,0x83,0xb0,0xf3 @ aesmc q4,q4
|
||||
.byte 0x22,0xa3,0xb0,0xf3 @ aese q5,q9
|
||||
.byte 0x8a,0xa3,0xb0,0xf3 @ aesmc q5,q5
|
||||
vld1.8 {q11},[r0]!
|
||||
mov r7,r3
|
||||
.byte 0x22,0x43,0xf0,0xf3 @ aese q10,q9
|
||||
.byte 0xa4,0x23,0xf0,0xf3 @ aesmc q9,q10
|
||||
vorr q10,q6,q6
|
||||
add r9,r8,#1
|
||||
.byte 0x28,0x83,0xb0,0xf3 @ aese q4,q12
|
||||
.byte 0x88,0x83,0xb0,0xf3 @ aesmc q4,q4
|
||||
.byte 0x28,0xa3,0xb0,0xf3 @ aese q5,q12
|
||||
.byte 0x8a,0xa3,0xb0,0xf3 @ aesmc q5,q5
|
||||
veor q2,q2,q7
|
||||
add r10,r8,#2
|
||||
.byte 0x28,0x23,0xf0,0xf3 @ aese q9,q12
|
||||
.byte 0xa2,0x23,0xf0,0xf3 @ aesmc q9,q9
|
||||
veor q3,q3,q7
|
||||
add r8,r8,#3
|
||||
.byte 0x2a,0x83,0xb0,0xf3 @ aese q4,q13
|
||||
.byte 0x88,0x83,0xb0,0xf3 @ aesmc q4,q4
|
||||
.byte 0x2a,0xa3,0xb0,0xf3 @ aese q5,q13
|
||||
.byte 0x8a,0xa3,0xb0,0xf3 @ aesmc q5,q5
|
||||
veor q11,q11,q7
|
||||
rev r9,r9
|
||||
.byte 0x2a,0x23,0xf0,0xf3 @ aese q9,q13
|
||||
.byte 0xa2,0x23,0xf0,0xf3 @ aesmc q9,q9
|
||||
vmov.32 d1[1], r9
|
||||
rev r10,r10
|
||||
.byte 0x2c,0x83,0xb0,0xf3 @ aese q4,q14
|
||||
.byte 0x88,0x83,0xb0,0xf3 @ aesmc q4,q4
|
||||
.byte 0x2c,0xa3,0xb0,0xf3 @ aese q5,q14
|
||||
.byte 0x8a,0xa3,0xb0,0xf3 @ aesmc q5,q5
|
||||
vmov.32 d3[1], r10
|
||||
rev r12,r8
|
||||
.byte 0x2c,0x23,0xf0,0xf3 @ aese q9,q14
|
||||
.byte 0xa2,0x23,0xf0,0xf3 @ aesmc q9,q9
|
||||
vmov.32 d21[1], r12
|
||||
subs r2,r2,#3
|
||||
.byte 0x2e,0x83,0xb0,0xf3 @ aese q4,q15
|
||||
.byte 0x2e,0xa3,0xb0,0xf3 @ aese q5,q15
|
||||
.byte 0x2e,0x23,0xf0,0xf3 @ aese q9,q15
|
||||
|
||||
veor q2,q2,q4
|
||||
vld1.32 {q8},[r7]! @ re-pre-load rndkey[0]
|
||||
vst1.8 {q2},[r1]!
|
||||
veor q3,q3,q5
|
||||
mov r6,r5
|
||||
vst1.8 {q3},[r1]!
|
||||
veor q11,q11,q9
|
||||
vld1.32 {q9},[r7]! @ re-pre-load rndkey[1]
|
||||
vst1.8 {q11},[r1]!
|
||||
bhs .Loop3x_ctr32
|
||||
|
||||
adds r2,r2,#3
|
||||
beq .Lctr32_done
|
||||
cmp r2,#1
|
||||
mov r12,#16
|
||||
moveq r12,#0
|
||||
|
||||
.Lctr32_tail:
|
||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x20,0x23,0xb0,0xf3 @ aese q1,q8
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
vld1.32 {q8},[r7]!
|
||||
subs r6,r6,#2
|
||||
.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x22,0x23,0xb0,0xf3 @ aese q1,q9
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
vld1.32 {q9},[r7]!
|
||||
bgt .Lctr32_tail
|
||||
|
||||
.byte 0x20,0x03,0xb0,0xf3 @ aese q0,q8
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x20,0x23,0xb0,0xf3 @ aese q1,q8
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
.byte 0x22,0x03,0xb0,0xf3 @ aese q0,q9
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x22,0x23,0xb0,0xf3 @ aese q1,q9
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
vld1.8 {q2},[r0],r12
|
||||
.byte 0x28,0x03,0xb0,0xf3 @ aese q0,q12
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x28,0x23,0xb0,0xf3 @ aese q1,q12
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
vld1.8 {q3},[r0]
|
||||
.byte 0x2a,0x03,0xb0,0xf3 @ aese q0,q13
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x2a,0x23,0xb0,0xf3 @ aese q1,q13
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
veor q2,q2,q7
|
||||
.byte 0x2c,0x03,0xb0,0xf3 @ aese q0,q14
|
||||
.byte 0x80,0x03,0xb0,0xf3 @ aesmc q0,q0
|
||||
.byte 0x2c,0x23,0xb0,0xf3 @ aese q1,q14
|
||||
.byte 0x82,0x23,0xb0,0xf3 @ aesmc q1,q1
|
||||
veor q3,q3,q7
|
||||
.byte 0x2e,0x03,0xb0,0xf3 @ aese q0,q15
|
||||
.byte 0x2e,0x23,0xb0,0xf3 @ aese q1,q15
|
||||
|
||||
cmp r2,#1
|
||||
veor q2,q2,q0
|
||||
veor q3,q3,q1
|
||||
vst1.8 {q2},[r1]!
|
||||
beq .Lctr32_done
|
||||
vst1.8 {q3},[r1]
|
||||
|
||||
.Lctr32_done:
|
||||
vldmia sp!,{d8-d15}
|
||||
ldmia sp!,{r4-r10,pc}
|
||||
.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
|
||||
#endif
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# $NetBSD: bf.inc,v 1.1 2016/10/17 00:24:13 joerg Exp $
|
||||
|
||||
CPPFLAGS+= -DBF_PTR
|
||||
|
||||
.include "${.CURDIR}/bf.inc"
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
.PATH.S: ${.PARSEDIR}
|
||||
.include "../../bn.inc"
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
.PATH.S: ${.PARSEDIR}
|
||||
.include "../../crypto.inc"
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# $NetBSD: des.inc,v 1.1 2016/10/17 00:24:13 joerg Exp $
|
||||
|
||||
.PATH.S: ${.PARSEDIR}
|
||||
CPPFLAGS+= -DDES_INT -DDES_UNROLL
|
||||
.include "${.CURDIR}/des.inc"
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
#include "arm_arch.h"
|
||||
|
||||
.text
|
||||
.fpu neon
|
||||
.code 32
|
||||
.global gcm_init_v8
|
||||
.type gcm_init_v8,%function
|
||||
.align 4
|
||||
gcm_init_v8:
|
||||
vld1.64 {q9},[r1] @ load input H
|
||||
vmov.i8 q11,#0xe1
|
||||
vshl.i64 q11,q11,#57 @ 0xc2.0
|
||||
vext.8 q3,q9,q9,#8
|
||||
vshr.u64 q10,q11,#63
|
||||
vdup.32 q9,d18[1]
|
||||
vext.8 q8,q10,q11,#8 @ t0=0xc2....01
|
||||
vshr.u64 q10,q3,#63
|
||||
vshr.s32 q9,q9,#31 @ broadcast carry bit
|
||||
vand q10,q10,q8
|
||||
vshl.i64 q3,q3,#1
|
||||
vext.8 q10,q10,q10,#8
|
||||
vand q8,q8,q9
|
||||
vorr q3,q3,q10 @ H<<<=1
|
||||
veor q12,q3,q8 @ twisted H
|
||||
vst1.64 {q12},[r0]! @ store Htable[0]
|
||||
|
||||
@ calculate H^2
|
||||
vext.8 q8,q12,q12,#8 @ Karatsuba pre-processing
|
||||
.byte 0xa8,0x0e,0xa8,0xf2 @ pmull q0,q12,q12
|
||||
veor q8,q8,q12
|
||||
.byte 0xa9,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q12
|
||||
.byte 0xa0,0x2e,0xa0,0xf2 @ pmull q1,q8,q8
|
||||
|
||||
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
|
||||
veor q10,q0,q2
|
||||
veor q1,q1,q9
|
||||
veor q1,q1,q10
|
||||
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
|
||||
|
||||
vmov d4,d3 @ Xh|Xm - 256-bit result
|
||||
vmov d3,d0 @ Xm is rotated Xl
|
||||
veor q0,q1,q10
|
||||
|
||||
vext.8 q10,q0,q0,#8 @ 2nd phase
|
||||
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
|
||||
veor q10,q10,q2
|
||||
veor q14,q0,q10
|
||||
|
||||
vext.8 q9,q14,q14,#8 @ Karatsuba pre-processing
|
||||
veor q9,q9,q14
|
||||
vext.8 q13,q8,q9,#8 @ pack Karatsuba pre-processed
|
||||
vst1.64 {q13-q14},[r0] @ store Htable[1..2]
|
||||
|
||||
bx lr
|
||||
.size gcm_init_v8,.-gcm_init_v8
|
||||
.global gcm_gmult_v8
|
||||
.type gcm_gmult_v8,%function
|
||||
.align 4
|
||||
gcm_gmult_v8:
|
||||
vld1.64 {q9},[r0] @ load Xi
|
||||
vmov.i8 q11,#0xe1
|
||||
vld1.64 {q12-q13},[r1] @ load twisted H, ...
|
||||
vshl.u64 q11,q11,#57
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q9,q9
|
||||
#endif
|
||||
vext.8 q3,q9,q9,#8
|
||||
|
||||
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
|
||||
veor q9,q9,q3 @ Karatsuba pre-processing
|
||||
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
|
||||
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
|
||||
|
||||
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
|
||||
veor q10,q0,q2
|
||||
veor q1,q1,q9
|
||||
veor q1,q1,q10
|
||||
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
|
||||
|
||||
vmov d4,d3 @ Xh|Xm - 256-bit result
|
||||
vmov d3,d0 @ Xm is rotated Xl
|
||||
veor q0,q1,q10
|
||||
|
||||
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
|
||||
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
|
||||
veor q10,q10,q2
|
||||
veor q0,q0,q10
|
||||
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q0,q0
|
||||
#endif
|
||||
vext.8 q0,q0,q0,#8
|
||||
vst1.64 {q0},[r0] @ write out Xi
|
||||
|
||||
bx lr
|
||||
.size gcm_gmult_v8,.-gcm_gmult_v8
|
||||
.global gcm_ghash_v8
|
||||
.type gcm_ghash_v8,%function
|
||||
.align 4
|
||||
gcm_ghash_v8:
|
||||
vstmdb sp!,{d8-d15} @ 32-bit ABI says so
|
||||
vld1.64 {q0},[r0] @ load [rotated] Xi
|
||||
@ "[rotated]" means that
|
||||
@ loaded value would have
|
||||
@ to be rotated in order to
|
||||
@ make it appear as in
|
||||
@ alorithm specification
|
||||
subs r3,r3,#32 @ see if r3 is 32 or larger
|
||||
mov r12,#16 @ r12 is used as post-
|
||||
@ increment for input pointer;
|
||||
@ as loop is modulo-scheduled
|
||||
@ r12 is zeroed just in time
|
||||
@ to preclude oversteping
|
||||
@ inp[len], which means that
|
||||
@ last block[s] are actually
|
||||
@ loaded twice, but last
|
||||
@ copy is not processed
|
||||
vld1.64 {q12-q13},[r1]! @ load twisted H, ..., H^2
|
||||
vmov.i8 q11,#0xe1
|
||||
vld1.64 {q14},[r1]
|
||||
moveq r12,#0 @ is it time to zero r12?
|
||||
vext.8 q0,q0,q0,#8 @ rotate Xi
|
||||
vld1.64 {q8},[r2]! @ load [rotated] I[0]
|
||||
vshl.u64 q11,q11,#57 @ compose 0xc2.0 constant
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q8,q8
|
||||
vrev64.8 q0,q0
|
||||
#endif
|
||||
vext.8 q3,q8,q8,#8 @ rotate I[0]
|
||||
blo .Lodd_tail_v8 @ r3 was less than 32
|
||||
vld1.64 {q9},[r2],r12 @ load [rotated] I[1]
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q9,q9
|
||||
#endif
|
||||
vext.8 q7,q9,q9,#8
|
||||
veor q3,q3,q0 @ I[i]^=Xi
|
||||
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
|
||||
veor q9,q9,q7 @ Karatsuba pre-processing
|
||||
.byte 0x8f,0xce,0xa9,0xf2 @ pmull2 q6,q12,q7
|
||||
b .Loop_mod2x_v8
|
||||
|
||||
.align 4
|
||||
.Loop_mod2x_v8:
|
||||
vext.8 q10,q3,q3,#8
|
||||
subs r3,r3,#32 @ is there more data?
|
||||
.byte 0x86,0x0e,0xac,0xf2 @ pmull q0,q14,q3 @ H^2.lo·Xi.lo
|
||||
movlo r12,#0 @ is it time to zero r12?
|
||||
|
||||
.byte 0xa2,0xae,0xaa,0xf2 @ pmull q5,q13,q9
|
||||
veor q10,q10,q3 @ Karatsuba pre-processing
|
||||
.byte 0x87,0x4e,0xad,0xf2 @ pmull2 q2,q14,q3 @ H^2.hi·Xi.hi
|
||||
veor q0,q0,q4 @ accumulate
|
||||
.byte 0xa5,0x2e,0xab,0xf2 @ pmull2 q1,q13,q10 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
|
||||
vld1.64 {q8},[r2],r12 @ load [rotated] I[i+2]
|
||||
|
||||
veor q2,q2,q6
|
||||
moveq r12,#0 @ is it time to zero r12?
|
||||
veor q1,q1,q5
|
||||
|
||||
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
|
||||
veor q10,q0,q2
|
||||
veor q1,q1,q9
|
||||
vld1.64 {q9},[r2],r12 @ load [rotated] I[i+3]
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q8,q8
|
||||
#endif
|
||||
veor q1,q1,q10
|
||||
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
|
||||
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q9,q9
|
||||
#endif
|
||||
vmov d4,d3 @ Xh|Xm - 256-bit result
|
||||
vmov d3,d0 @ Xm is rotated Xl
|
||||
vext.8 q7,q9,q9,#8
|
||||
vext.8 q3,q8,q8,#8
|
||||
veor q0,q1,q10
|
||||
.byte 0x8e,0x8e,0xa8,0xf2 @ pmull q4,q12,q7 @ H·Ii+1
|
||||
veor q3,q3,q2 @ accumulate q3 early
|
||||
|
||||
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
|
||||
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
|
||||
veor q3,q3,q10
|
||||
veor q9,q9,q7 @ Karatsuba pre-processing
|
||||
veor q3,q3,q0
|
||||
.byte 0x8f,0xce,0xa9,0xf2 @ pmull2 q6,q12,q7
|
||||
bhs .Loop_mod2x_v8 @ there was at least 32 more bytes
|
||||
|
||||
veor q2,q2,q10
|
||||
vext.8 q3,q8,q8,#8 @ re-construct q3
|
||||
adds r3,r3,#32 @ re-construct r3
|
||||
veor q0,q0,q2 @ re-construct q0
|
||||
beq .Ldone_v8 @ is r3 zero?
|
||||
.Lodd_tail_v8:
|
||||
vext.8 q10,q0,q0,#8
|
||||
veor q3,q3,q0 @ inp^=Xi
|
||||
veor q9,q8,q10 @ q9 is rotated inp^Xi
|
||||
|
||||
.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
|
||||
veor q9,q9,q3 @ Karatsuba pre-processing
|
||||
.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
|
||||
.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
|
||||
|
||||
vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
|
||||
veor q10,q0,q2
|
||||
veor q1,q1,q9
|
||||
veor q1,q1,q10
|
||||
.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase of reduction
|
||||
|
||||
vmov d4,d3 @ Xh|Xm - 256-bit result
|
||||
vmov d3,d0 @ Xm is rotated Xl
|
||||
veor q0,q1,q10
|
||||
|
||||
vext.8 q10,q0,q0,#8 @ 2nd phase of reduction
|
||||
.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
|
||||
veor q10,q10,q2
|
||||
veor q0,q0,q10
|
||||
|
||||
.Ldone_v8:
|
||||
#ifndef __ARMEB__
|
||||
vrev64.8 q0,q0
|
||||
#endif
|
||||
vext.8 q0,q0,q0,#8
|
||||
vst1.64 {q0},[r0] @ write out Xi
|
||||
|
||||
vldmia sp!,{d8-d15} @ 32-bit ABI says so
|
||||
bx lr
|
||||
.size gcm_ghash_v8,.-gcm_ghash_v8
|
||||
.asciz "GHASH for ARMv8, CRYPTOGAMS by <appro@openssl.org>"
|
||||
.align 2
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
.PATH.S: ${.PARSEDIR}
|
||||
#MODES_SRCS = ghashv8-armx.S
|
||||
#MODESCPPFLAGS = -DGHASH_ASM
|
||||
.include "../../modes.inc"
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.PATH.S: ${.PARSEDIR}
|
||||
CPPFLAGS+= -DRC4_CHUNK="unsigned long" -DRC4_INT="unsigned char"
|
||||
.include "../../rc4.inc"
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.if ${MACHINE_ARCH:M*armv4*} == ""
|
||||
.PATH.S: ${.PARSEDIR}
|
||||
#SHA_SRCS = sha1-armv8.S
|
||||
#SHACPPFLAGS = -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM
|
||||
.endif
|
||||
.include "../../sha.inc"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue