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Revamped QVSS (VCB01) support. (from Charles Dickman)

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This commit is contained in:
matt 2015-07-05 03:07:21 +00:00
parent 7e4aa81e25
commit e95f8d8cf9
8 changed files with 2966 additions and 1244 deletions
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2191
sys/arch/vax/uba/qv.c
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sys/arch/vax/uba/qv_ic.h Normal file
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/* $NetBSD: qv_ic.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles H. Dickman
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* registers */
#define QV_IC_DR 0 /* data register */
#define QV_IC_SR 2 /* status register */
/* commands */
#define QV_IC_RESET 0x00
#define QV_IC_CIMR 0x28
#define QV_IC_SIMR 0x38
#define QV_IC_CLRIRR 0x40
#define QV_IC_SIRR 0x58
#define QV_IC_MODE 0x80
#define QV_IC_ARM 0xa1
#define QV_IC_DISARM 0xa2
#define QV_IC_ACREG 0xc0
#define QV_IC_RMEM 0xe0
#define RMEM_BC_1 0x00
#define RMEM_BC_2 0x08
#define RMEM_BC_3 0x10
#define RMEM_BC_4 0x18
/* vectors */
#define QV_DUART_VEC 0
#define QV_SYNC_VEC 1
#define QV_MOUSE_VEC 2
#define QV_CURS_VEC 3
#define QV_MBA_VEC 4
#define QV_MBB_VEC 5
#define QV_MBC_VEC 6
#define QV_IC_ENA 1
#define QV_IC_DIS 0
void qv_ic_init(struct uba_attach_args *, bus_size_t);
void qv_ic_setvec(struct uba_attach_args *, bus_size_t, int, int);
void qv_ic_enable(struct uba_attach_args *, bus_size_t, int, int);
void qv_ic_arm(struct uba_attach_args *, bus_size_t, int);
void qv_ic_force(struct uba_attach_args *, bus_size_t, int);

284
sys/arch/vax/uba/qvareg.h Normal file
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/* $NetBSD: qvareg.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/*
* Copyright (c) 2015 Charles H. Dickman. All rights reserved.
* Derived from sgimips port
* Copyright (c) 1996, 1997 Philip L. Budne.
* Copyright (c) 1993 Philip A. Nelson.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Philip A. Nelson.
* 4. The name of Philip A. Nelson may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY PHILIP NELSON ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL PHILIP NELSON BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* scnreg.h: definitions for qvss scn2681 DUART
*/
/*
* register offsets
*/
/* per-channel regs (channel B's at SCN_REG(8-11)) */
#define CH_MR(x) SCN_REG(0 + 8*(x)) /* rw mode register */
#define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */
#define CH_CSR(x) SCN_REG(1 + 8*(x)) /* wo clock select reg */
#define CH_CR(x) SCN_REG(2 + 8*(x)) /* wo command reg */
#define CH_DAT(x) SCN_REG(3 + 8*(x)) /* rw data reg */
/* duart-wide regs */
#define DU_IPCR SCN_REG(4) /* ro input port change reg */
#define DU_ACR SCN_REG(4) /* wo aux control reg */
#define DU_ISR SCN_REG(5) /* ro interrupt stat reg */
#define DU_IMR SCN_REG(5) /* wo interrupt mask reg */
#define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */
#define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */
/* SCN_REG(8-11) channel b (see above) */
/* SCN_REG(12): reserved */
#define DU_IP SCN_REG(13) /* ro input port */
#define DU_OPCR SCN_REG(13) /* wo output port cfg reg */
#define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */
#define DU_OPSET SCN_REG(14) /* wo output port set */
#define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */
#define DU_OPCLR SCN_REG(15) /* wo output port reset */
struct qvaux_ch_regs {
bus_addr_t qr_mr;
bus_addr_t qr_sr;
bus_addr_t qr_csr;
bus_addr_t qr_cr;
bus_addr_t qr_dat;
};
struct qvaux_regs {
bus_addr_t qr_ipcr;
bus_addr_t qr_acr;
bus_addr_t qr_isr;
bus_addr_t qr_imr;
bus_addr_t qr_ctur;
bus_addr_t qr_ctlr;
bus_addr_t qr_ip;
bus_addr_t qr_opcr;
bus_addr_t qr_cstrt;
bus_addr_t qr_opset;
bus_addr_t qr_cstop;
bus_addr_t qr_opclr;
struct qvaux_ch_regs qr_ch_regs[2];
bus_addr_t qr_firstreg;
bus_addr_t qr_winsize;
};
/*
* Data Values
*/
/*
* MR (mode register) -- per channel
*/
/* MR0 (scn26c92 only) need to use CR_CMD_MR0 before access */
#define MR0_MODE 0x07 /* extended baud rate mode (MR0A only) */
#define MR0_TXINT 0x30 /* Tx int threshold */
#define MR0_RXINT 0x40 /* Rx int threshold (along with MR1_FFULL) */
#define MR0_RXWD 0x80 /* Rx watchdog (8 byte-times after last rx) */
#define MR0_MODE_0 0x00 /* Normal mode */
#define MR0_MODE_1 0x01 /* Extended mode 1 */
#define MR0_MODE_2 0x04 /* Extended mode 2 */
#define MR0_TXINT_EMPTY 0x00 /* TxInt when 8 FIFO bytes empty (default) */
#define MR0_TXINT_4 0x10 /* TxInt when 4 or more FIFO bytes empty */
#define MR0_TXINT_6 0x20 /* TxInt when 6 or more FIFO bytes empty */
#define MR0_TXINT_TXRDY 0x30 /* TxInt when 1 or more FIFO bytes empty */
/* MR1 (need to use CR_CMD_MR1 before each access) */
#define MR1_CS5 0x00
#define MR1_CS6 0x01
#define MR1_CS7 0x02
#define MR1_CS8 0x03
#define MR1_PEVEN 0x00
#define MR1_PODD 0x04
#define MR1_PNONE 0x10
#define MR1_RXBLK 0x20 /* "block" error mode */
#define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */
#define MR1_RXRTS 0x80 /* auto RTS input flow ctrl */
/* MR2 (any access to MR after MR1) */
#define MR2_STOP 0x0f /* mask for stop bits */
#define MR2_STOP1 0x07
#define MR2_STOP2 0x0f
#define MR2_TXCTS 0x10 /* transmitter follows CTS */
#define MR2_TXRTS 0x20 /* RTS follows transmitter */
#define MR2_MODE 0xc0 /* mode mask */
/*
* IP (input port)
*/
#define IP_IP0 0x01
#define IP_IP1 0x02
#define IP_IP2 0x04
#define IP_IP3 0x08
#define IP_IP4 0x10
#define IP_IP5 0x20
#define IP_IP6 0x40
/* D7 is always 1 */
/*
* ACR (Aux Control Register)
*/
#define ACR_DELTA_IP0 0x01 /* enable IP0 delta interrupt */
#define ACR_DELTA_IP1 0x02 /* enable IP1 delta interrupt */
#define ACR_DELTA_IP2 0x04 /* enable IP2 delta interrupt */
#define ACR_DELTA_IP3 0x08 /* enable IP3 delta interrupt */
#define ACR_CT 0x70 /* counter/timer mode (ACT_CT_xxx) */
#define ACR_BRG 0x80 /* baud rate generator speed set */
/* counter/timer mode */
#define ACR_CT_CEXT 0x00 /* counter: external (IP2) */
#define ACR_CT_CTXA 0x10 /* counter: TxCA x 1 */
#define ACR_CT_CTXB 0x20 /* counter: TxCB x 1 */
#define ACR_CT_CCLK 0x30 /* counter: X1/CLK div 16 */
#define ACR_CT_TEXT1 0x40 /* timer: external (IP2) */
#define ACR_CT_TEXT16 0x50 /* timer: external (IP2) div 16 */
#define ACR_CT_TCLK1 0x60 /* timer: X1/CLK */
#define ACR_CT_TCLK16 0x70 /* timer: X1/CLK div 16 */
/*
* IPCR (Input Port Change Register) -- per channel
*/
#define IPCR_IP0 0x01
#define IPCR_IP1 0x02
#define IPCR_IP2 0x04
#define IPCR_IP3 0x08
#define IPCR_DELTA_IP0 0x10
#define IPCR_DELTA_IP1 0x20
#define IPCR_DELTA_IP2 0x40
#define IPCR_DELTA_IP3 0x80
/*
* output port config register
* if bit(s) clear OP line follows OP register OPn bit
*/
#define OPCR_OP7_TXRDYB 0x80 /* OP7: TxRDYB */
#define OPCR_OP6_TXRDYA 0x40 /* OP6: TxRDYA */
#define OPCR_OP5_RXRDYB 0x20 /* OP5: ch B RxRDY/FFULL */
#define OPCR_OP4_RXRDYA 0x10 /* OP4: ch A RxRDY/FFULL */
#define OPCR_OP3 0xC0 /* OP3: mask */
#define OPCR_OP2 0x03 /* OP2: mask */
/*
* output port
*/
#define OP_OP0 0x01
#define OP_OP1 0x02
#define OP_OP2 0x04
#define OP_OP3 0x08
#define OP_OP4 0x10
#define OP_OP5 0x20
#define OP_OP6 0x40
#define OP_OP7 0x80
/*
* CR (command register) -- per channel
*/
/* bits (may be or'ed together, with a command) */
#define CR_ENA_RX 0x01
#define CR_DIS_RX 0x02
#define CR_ENA_TX 0x04
#define CR_DIS_TX 0x08
/* commands */
#define CR_CMD_NOP 0x00
#define CR_CMD_MR1 0x10
#define CR_CMD_RESET_RX 0x20
#define CR_CMD_RESET_TX 0x30
#define CR_CMD_RESET_ERR 0x40
#define CR_CMD_RESET_BRK 0x50
#define CR_CMD_START_BRK 0x60
#define CR_CMD_STOP_BRK 0x70
/* 2692-only commands */
#define CR_CMD_RTS_ON 0x80 /* raise RTS */
#define CR_CMD_RTS_OFF 0x90 /* lower RTS */
#define CR_CMD_TIM_ON 0xa0 /* enable timeout mode */
#define CR_CMD_TIM_OFF 0xc0 /* reset timeout mode */
#define CR_CMD_PDN_ON 0xe0 /* power down mode on */
#define CR_CMD_PDN_RUN 0xf0 /* power down mode off (normal run) */
/* 26C92-only commands */
#define CR_CMD_MR0 0xb0 /* MR0 select */
/*
* CSR (clock select register) -- per channel
*/
#define CSR_B75 0x0
#define CSR_B110 0x1
#define CSR_B134 0x2
#define CSR_B150 0x3
#define CSR_B300 0x4
#define CSR_B600 0x5
#define CSR_B1200 0x6
#define CSR_B2000 0x7
#define CSR_B2400 0x8
#define CSR_B4800 0x9
#define CSR_B7200 0xa
#define CSR_B9600 0xb
#define CSR_B19200 0xc
/*
* SR (status register) -- per channel
*/
#define SR_RX_RDY 0x01
#define SR_RX_FFULL 0x02 /* rx fifo full */
#define SR_TX_RDY 0x04 /* tx room for more */
#define SR_TX_EMPTY 0x08 /* tx dry */
#define SR_OVERRUN 0x10
/* bits cleared by reset error (see MR1 error mode bit) */
#define SR_PARITY 0x20 /* received parity error */
#define SR_FRAME 0x40 /* received framing error */
#define SR_BREAK 0x80 /* received break */
/*
* Interrupt Mask Register (IMR) and ISR (Interrupt Status Register)
*/
#define INT_TXA 0x01 /* Tx Ready A */
#define INT_RXA 0x02 /* Rx Ready/FIFO Full A */
#define INT_BRKA 0x04 /* Delta Break A */
#define INT_CTR 0x08 /* counter ready */
#define INT_TXB 0x10 /* Tx Ready B */
#define INT_RXB 0x20 /* Rx Ready/FIFO Full B */
#define INT_BRKB 0x40 /* Delta Break B */
#define INT_IP 0x80 /* input port change */

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/* $NetBSD: qvaux.c,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles H. Dickman
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/callout.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <sys/kauth.h>
#include <sys/bus.h>
#include <dev/qbus/ubavar.h>
#include <vax/uba/qvareg.h>
#include <vax/uba/qvavar.h>
#include <vax/uba/qvkbdvar.h>
#include <dev/cons.h>
#include "qv.h"
#include "qvkbd.h"
#include "qvms.h"
#include "qv_ic.h"
#define QVAUX_DELAY(x) /* nothing */
#define control inline
static control uint
qvaux_read1(struct qvaux_softc *sc, u_int off)
{
u_int rv;
rv = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off);
QVAUX_DELAY(1);
return rv;
}
static control u_int
qvaux_read2(struct qvaux_softc *sc, u_int off)
{
u_int rv;
rv = bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
QVAUX_DELAY(1);
return rv;
}
static control void
qvaux_write1(struct qvaux_softc *sc, u_int off, u_int val)
{
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, val);
bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg,
sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE |
BUS_SPACE_BARRIER_READ);
QVAUX_DELAY(10);
}
static control void
qvaux_write2(struct qvaux_softc *sc, u_int off, u_int val)
{
bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val);
bus_space_barrier(sc->sc_iot, sc->sc_ioh, sc->sc_qr.qr_firstreg,
sc->sc_qr.qr_winsize, BUS_SPACE_BARRIER_WRITE |
BUS_SPACE_BARRIER_READ);
QVAUX_DELAY(10);
}
#include "ioconf.h"
/* Flags used to monitor modem bits, make them understood outside driver */
#define DML_DTR TIOCM_DTR
#define DML_DCD TIOCM_CD
#define DML_RI TIOCM_RI
#define DML_BRK 0100000 /* no equivalent, we will mask */
static const struct speedtab qvauxspeedtab[] =
{
{ 0, 0 },
{ 75, CSR_B75 },
{ 110, CSR_B110 },
{ 134, CSR_B134 },
{ 150, CSR_B150 },
{ 300, CSR_B300 },
{ 600, CSR_B600 },
{ 1200, CSR_B1200 },
{ 2000, CSR_B2000 },
{ 2400, CSR_B2400 },
{ 4800, CSR_B4800 },
{ 7200, CSR_B7200 },
{ 9600, CSR_B9600 },
{ 19200, CSR_B19200 },
{ -1, -1 }
};
int qvaux_match(device_t, cfdata_t, void *);
static void qvaux_attach(device_t , device_t , void *);
static void qvauxstart(struct tty *);
static int qvauxparam(struct tty *, struct termios *);
static unsigned qvauxmctl(struct qvaux_softc *, int, int, int);
//static void qvauxscan(void *);
int qvauxgetc(struct qvaux_linestate *);
void qvauxputc(struct qvaux_linestate *, int);
static dev_type_open(qvauxopen);
static dev_type_close(qvauxclose);
static dev_type_read(qvauxread);
static dev_type_write(qvauxwrite);
static dev_type_ioctl(qvauxioctl);
static dev_type_stop(qvauxstop);
static dev_type_tty(qvauxtty);
static dev_type_poll(qvauxpoll);
const struct cdevsw qvaux_cdevsw = {
qvauxopen, qvauxclose, qvauxread, qvauxwrite, qvauxioctl,
qvauxstop, qvauxtty, qvauxpoll, nommap, ttykqfilter, nodiscard, D_TTY
};
int qvaux_timer; /* true if timer started */
struct callout qvauxscan_ch;
static struct cnm_state qvaux_cnm_state;
CFATTACH_DECL_NEW(qvaux, sizeof(struct qvaux_softc),
qvaux_match, qvaux_attach, NULL, NULL);
#if NQVKBD > 0 || NQVMS > 0
static int
qvaux_print(void *aux, const char *name)
{
struct qvauxkm_attach_args *daa = aux;
if (name == NULL) {
aprint_normal(" line %d", daa->daa_line);
}
return QUIET;
}
#endif
int
qvaux_match(device_t parent, cfdata_t match, void *aux)
{
/* always match since we are physically part of parent */
return 1;
}
/*ARGSUSED*/
static void
qvaux_attach(device_t parent, device_t self, void *aux)
{
struct qvaux_softc *sc = device_private(self);
struct uba_attach_args *ua = aux;
#if NQVKBD > 0 || NQVMS > 0
struct qvauxkm_attach_args daa;
#endif
/* set floating DUART vector and enable interrupts */
qv_ic_setvec(ua, QVA_QVIC, QV_DUART_VEC, ua->ua_cvec);
qv_ic_arm(ua, QVA_QVIC, QV_IC_ENA);
bus_space_write_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR,
bus_space_read_2(ua->ua_iot, ua->ua_ioh, QVA_QVCSR) | (1 << 6));
sc->sc_dev = self;
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
/* device register access structure */
sc->sc_qr.qr_ipcr = DU_IPCR;
sc->sc_qr.qr_acr = DU_ACR;
sc->sc_qr.qr_isr = DU_ISR;
sc->sc_qr. qr_imr = DU_IMR;
sc->sc_qr.qr_ctur = DU_CTUR;
sc->sc_qr.qr_ctlr = DU_CTLR;
sc->sc_qr.qr_ip = DU_IP;
sc->sc_qr.qr_opcr = DU_OPCR;
sc->sc_qr.qr_cstrt = DU_IMR;
sc->sc_qr.qr_opset = DU_OPSET;
sc->sc_qr.qr_cstop = DU_CSTOP;
sc->sc_qr.qr_opclr = DU_OPCLR;
sc->sc_qr.qr_ch_regs[0].qr_mr = CH_MR(0);
sc->sc_qr.qr_ch_regs[0].qr_sr = CH_SR(0);
sc->sc_qr.qr_ch_regs[0].qr_csr = CH_CSR(0);
sc->sc_qr.qr_ch_regs[0].qr_cr = CH_CR(0);
sc->sc_qr.qr_ch_regs[0].qr_dat = CH_DAT(0);
sc->sc_qr.qr_ch_regs[1].qr_mr = CH_MR(1);
sc->sc_qr.qr_ch_regs[1].qr_sr = CH_SR(1);
sc->sc_qr.qr_ch_regs[1].qr_csr = CH_CSR(1);
sc->sc_qr.qr_ch_regs[1].qr_cr = CH_CR(1);
sc->sc_qr.qr_ch_regs[1].qr_dat = CH_DAT(1);
sc->sc_qr.qr_firstreg = QVA_FIRSTREG;
sc->sc_qr.qr_winsize = QVA_WINSIZE;
/* register DUART interrupt handler */
uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
qvauxint, sc, &sc->sc_tintrcnt);
qv_ic_enable(ua, QVA_QVIC, QV_DUART_VEC, QV_IC_ENA);
qvauxattach(sc, ua->ua_evcnt, -1);
#if NQVKBD > 0
/* XXX set line parameters */
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_csr,
(CSR_B4800 << 4) | CSR_B4800);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_CMD_MR1 | CR_ENA_RX);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR1_CS8 | MR1_PNONE);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_mr, MR2_STOP1);
daa.daa_line = 0;
daa.daa_flags = 0;
config_found(self, &daa, qvaux_print);
#endif
#if NQVMS > 0
/* XXX set line parameters */
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_csr,
(CSR_B4800 << 4) | CSR_B4800);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_CMD_MR1 | CR_ENA_RX);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR1_CS8 | MR1_PODD);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_mr, MR2_STOP1);
daa.daa_line = 1;
daa.daa_flags = 0;
config_found(self, &daa, qvaux_print);
#endif
}
void
qvauxattach(struct qvaux_softc *sc, struct evcnt *parent_evcnt, int consline)
{
int n;
dev_t dev;
/* Initialize our softc structure. */
for (n = 0; n < NQVAUXLINE; n++) {
sc->sc_qvaux[n].qvaux_sc = sc;
sc->sc_qvaux[n].qvaux_line = n;
sc->sc_qvaux[n].qvaux_tty = tty_alloc();
dev = sc->sc_qvaux[n].qvaux_tty->t_dev;
sc->sc_qvaux[n].qvaux_tty->t_dev = makedev(major(dev),n);
}
evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
device_xname(sc->sc_dev), "rintr");
evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, parent_evcnt,
device_xname(sc->sc_dev), "tintr");
/* Console magic keys */
cn_init_magic(&qvaux_cnm_state);
cn_set_magic("\047\001"); /* default magic is BREAK */
/* VAX will change it in MD code */
sc->sc_rxint = sc->sc_brk = 0;
sc->sc_consline = consline;
sc->sc_imr = INT_RXA | INT_RXB;
qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[0].qr_cr, CR_ENA_TX | CR_ENA_RX);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[1].qr_cr, CR_ENA_TX | CR_ENA_RX);
DELAY(10000);
printf("\n");
}
/* DUART Interrupt entry */
void
qvauxint(void *arg)
{
struct qvaux_softc *sc = arg;
int isr;
isr = qvaux_read2(sc, sc->sc_qr.qr_isr);
if (isr & (INT_RXA | INT_RXB | INT_BRKA | INT_BRKB))
qvauxrint(arg);
isr = qvaux_read2(sc, sc->sc_qr.qr_isr);
if (isr & (INT_TXA | INT_TXB) & sc->sc_imr)
qvauxxint(arg);
}
/* Receiver Interrupt */
void
qvauxrint(void *arg)
{
struct qvaux_softc *sc = arg;
struct tty *tp;
int cc, mcc, line;
unsigned stat[2];
int overrun = 0;
//printf(" qvauxrint ");
sc->sc_rxint++;
// determine source and loop until all are no longer active
for (;;) {
stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr);
stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr);
if ((stat[0] & SR_RX_RDY) == 0) {
if ((stat[1] & SR_RX_RDY) == 0)
break;
else
line = 1;
}
else
line = 0;
cc = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[line].qr_dat) & 0xFF;
tp = sc->sc_qvaux[line].qvaux_tty;
/* Must be caught early */
if (sc->sc_qvaux[line].qvaux_catch &&
(*sc->sc_qvaux[line].qvaux_catch)(sc->sc_qvaux[line]
.qvaux_private, cc)) {
continue;
}
if (stat[line] & SR_BREAK) // do SR error bits need to be
// cleared by an error reset?
mcc = CNC_BREAK;
else
mcc = cc;
cn_check_magic(tp->t_dev, mcc, qvaux_cnm_state);
if (!(tp->t_state & TS_ISOPEN)) {
cv_broadcast(&tp->t_rawcv);
continue;
}
if ((stat[line] & SR_OVERRUN) && overrun == 0) { // ?
log(LOG_WARNING, "%s: silo overflow, line %d\n",
device_xname(sc->sc_dev), line);
overrun = 1;
}
if (stat[line] & SR_FRAME) // ?
cc |= TTY_FE;
if (stat[line] & SR_PARITY) // ?
cc |= TTY_PE;
(*tp->t_linesw->l_rint)(cc, tp);
}
}
/* Transmitter Interrupt */
void
qvauxxint(void *arg)
{
struct qvaux_softc *sc = arg;
struct tty *tp;
struct clist *cl;
int line, ch, stat[2];
for (;;) {
stat[0] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[0].qr_sr);
stat[1] = qvaux_read2(sc, sc->sc_qr.qr_ch_regs[1].qr_sr);
if (((stat[0] & SR_TX_RDY) == 0)
|| ((sc->sc_imr & INT_TXA) == 0)) {
if (((stat[1] & SR_TX_RDY) == 0)
|| ((sc->sc_imr & INT_TXB) == 0))
break;
else
line = 1;
}
else
line = 0;
tp = sc->sc_qvaux[line].qvaux_tty;
cl = &tp->t_outq;
tp->t_state &= ~TS_BUSY;
/* Just send out a char if we have one */
/* As long as we can fill the chip buffer, we just loop here */
// no fifo, just holding register
if (cl->c_cc) {
tp->t_state |= TS_BUSY;
ch = getc(cl);
qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_dat, ch);
continue;
}
/* Nothing to send, clear the tx flags */
sc->sc_imr &= ~((line) ? (INT_TXB) : (INT_TXA));
qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
if (sc->sc_qvaux[line].qvaux_catch)
continue;
if (tp->t_state & TS_FLUSH)
tp->t_state &= ~TS_FLUSH;
else
ndflush (&tp->t_outq, cl->c_cc);
(*tp->t_linesw->l_start)(tp);
}
}
int
qvauxopen(dev_t dev, int flag, int mode, struct lwp *l)
{
const int line = QVA_PORT(minor(dev));
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
struct tty *tp;
int error = 0;
if (sc == NULL || line >= NQVAUXLINE)
return ENXIO;
/* if some other device is using the line, it's busy */
if (sc->sc_qvaux[line].qvaux_catch)
return EBUSY;
tp = sc->sc_qvaux[line].qvaux_tty;
if (tp == NULL)
return (ENODEV);
tp->t_oproc = qvauxstart;
tp->t_param = qvauxparam;
tp->t_dev = dev;
if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
return (EBUSY);
if ((tp->t_state & TS_ISOPEN) == 0) {
ttychars(tp);
if (tp->t_ispeed == 0) {
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
tp->t_cflag = TTYDEF_CFLAG;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
}
(void) qvauxparam(tp, &tp->t_termios);
ttsetwater(tp);
}
/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
if (qvauxmctl(sc, line, DML_DTR, DMBIS) & DML_DCD)
tp->t_state |= TS_CARR_ON;
mutex_spin_enter(&tty_lock);
while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
!(tp->t_state & TS_CARR_ON)) {
tp->t_wopen++;
error = ttysleep(tp, &tp->t_rawcv, true, 0);
tp->t_wopen--;
if (error)
break;
}
mutex_spin_exit(&tty_lock);
if (error)
return (error);
return ((*tp->t_linesw->l_open)(dev, tp));
}
/*ARGSUSED*/
int
qvauxclose(dev_t dev, int flag, int mode, struct lwp *l)
{
const int line = QVA_PORT(minor(dev));
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
struct tty *tp = sc->sc_qvaux[line].qvaux_tty;
(*tp->t_linesw->l_close)(tp, flag);
/* Make sure a BREAK state is not left enabled. */
(void) qvauxmctl(sc, line, DML_BRK, DMBIC);
/* Do a hangup if so required. */
if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN))
(void) qvauxmctl(sc, line, 0, DMSET);
return ttyclose(tp);
}
int
qvauxread(dev_t dev, struct uio *uio, int flag)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
return ((*tp->t_linesw->l_read)(tp, uio, flag));
}
int
qvauxwrite(dev_t dev, struct uio *uio, int flag)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
return ((*tp->t_linesw->l_write)(tp, uio, flag));
}
int
qvauxpoll(dev_t dev, int events, struct lwp *l)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
struct tty *tp = sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
return ((*tp->t_linesw->l_poll)(tp, events, l));
}
/*ARGSUSED*/
int
qvauxioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev))); // only one controller
const int line = QVA_PORT(minor(dev));
struct tty *tp = sc->sc_qvaux[line].qvaux_tty;
int error;
error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
if (error >= 0)
return (error);
error = ttioctl(tp, cmd, data, flag, l);
if (error >= 0)
return (error);
switch (cmd) {
case TIOCSBRK:
(void) qvauxmctl(sc, line, DML_BRK, DMBIS);
break;
case TIOCCBRK:
(void) qvauxmctl(sc, line, DML_BRK, DMBIC);
break;
case TIOCSDTR:
(void) qvauxmctl(sc, line, DML_DTR, DMBIS);
break;
case TIOCCDTR:
(void) qvauxmctl(sc, line, DML_DTR, DMBIC);
break;
case TIOCMSET:
(void) qvauxmctl(sc, line, *(int *)data, DMSET);
break;
case TIOCMBIS:
(void) qvauxmctl(sc, line, *(int *)data, DMBIS);
break;
case TIOCMBIC:
(void) qvauxmctl(sc, line, *(int *)data, DMBIC);
break;
case TIOCMGET:
*(int *)data = (qvauxmctl(sc, line, 0, DMGET) & ~DML_BRK);
break;
default:
return (EPASSTHROUGH);
}
return (0);
}
struct tty *
qvauxtty(dev_t dev)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(dev)));
return sc->sc_qvaux[QVA_PORT(minor(dev))].qvaux_tty;
}
/*ARGSUSED*/
void
qvauxstop(struct tty *tp, int flag)
{
if ((tp->t_state & (TS_BUSY | TS_TTSTOP)) == TS_BUSY)
tp->t_state |= TS_FLUSH;
}
void
qvauxstart(struct tty *tp)
{
struct qvaux_softc *sc;
int line;
int s;
s = spltty();
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) {
splx(s);
return;
}
if (!ttypull(tp)) {
splx(s);
return;
}
line = QVA_PORT(minor(tp->t_dev));
sc = device_lookup_private(&qvaux_cd, QVA_I2C(minor(tp->t_dev)));
tp->t_state |= TS_BUSY;
sc->sc_imr |= ((line) ? (INT_TXB) : (INT_TXA));
qvaux_write2(sc, sc->sc_qr.qr_imr, sc->sc_imr);
qvauxxint(sc);
splx(s);
}
static int
qvauxparam(struct tty *tp, struct termios *t)
{
struct qvaux_softc *sc = device_lookup_private(&qvaux_cd,
QVA_I2C(minor(tp->t_dev)));
const int line = QVA_PORT(minor(tp->t_dev));
int cflag = t->c_cflag;
int ispeed = ttspeedtab(t->c_ispeed, qvauxspeedtab);
int ospeed = ttspeedtab(t->c_ospeed, qvauxspeedtab);
unsigned mr1, mr2;
int s;
/* check requested parameters */
if (ospeed < 0 || ispeed < 0)
return (EINVAL);
tp->t_ispeed = t->c_ispeed;
tp->t_ospeed = t->c_ospeed;
tp->t_cflag = cflag;
if (ospeed == 0) {
(void) qvauxmctl(sc, line, 0, DMSET); /* hang up line */
return (0);
}
s = spltty();
/* XXX This is wrong. Flush output or the chip gets very confused. */
//ttywait(tp);
//lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line;
qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_csr,
(ispeed << 4) | ospeed);
mr1 = mr2 = 0;
switch (cflag & CSIZE)
{
case CS5:
mr1 |= MR1_CS5;
break;
case CS6:
mr1 |= MR1_CS6;
break;
case CS7:
mr1 |= MR1_CS7;
break;
default:
mr1 |= MR1_CS8;
break;
}
if (cflag & PARENB) {
if (cflag & PARODD)
mr1 |= MR1_PODD;
else
mr1 |= MR1_PEVEN;
}
else
mr1 |= MR1_PNONE;
if (cflag & CSTOPB)
mr2 |= MR2_STOP2;
else
mr2 |= MR2_STOP1;
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
CR_CMD_MR1 | CR_ENA_RX); // reset to mr1
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr1);
qvaux_write2(sc, sc->sc_qr.qr_ch_regs[line].qr_mr, mr2);
qvaux_write2(sc, sc->sc_qr.qr_acr, ACR_BRG);
(void) splx(s);
DELAY(10000);
return (0);
}
// QVSS has no modem control signals
static unsigned
qvauxmctl(struct qvaux_softc *sc, int line, int bits, int how)
{
/* unsigned status; */
unsigned mbits;
unsigned bit;
int s;
s = spltty();
mbits = 0;
bit = (1 << line);
#if 0
/* external signals as seen from the port */
status = qvaux_read1(sc, sc->sc_dr.dr_dcd) | sc->sc_dsr;
if (status & bit)
mbits |= DML_DCD;
status = qvaux_read1(sc, sc->sc_dr.dr_ring);
if (status & bit)
mbits |= DML_RI;
/* internal signals/state delivered to port */
status = qvaux_read1(sc, sc->sc_dr.dr_dtr);
if (status & bit)
mbits |= DML_DTR;
#endif
if (sc->sc_brk & bit)
mbits |= DML_BRK;
switch (how)
{
case DMSET:
mbits = bits;
break;
case DMBIS:
mbits |= bits;
break;
case DMBIC:
mbits &= ~bits;
break;
case DMGET:
(void) splx(s);
return (mbits);
}
#if 0
if (mbits & DML_DTR) {
qvaux_write1(sc, sc->sc_dr.dr_dtr,
qvaux_read1(sc, sc->sc_dr.dr_dtr) | bit);
} else {
qvaux_write1(sc, sc->sc_dr.dr_dtr,
qvaux_read1(sc, sc->sc_dr.dr_dtr) & ~bit);
}
#endif
if (mbits & DML_BRK) {
sc->sc_brk |= bit;
qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
CR_CMD_START_BRK);
} else {
sc->sc_brk &= ~bit;
qvaux_write1(sc, sc->sc_qr.qr_ch_regs[line].qr_cr,
CR_CMD_STOP_BRK);
}
(void) splx(s);
return (mbits);
}
/*
* Called after an ubareset. The QVSS card is reset, but the only thing
* that must be done is to start the receiver and transmitter again.
* No DMA setup to care about.
*/
void
qvauxreset(device_t dev)
{
struct qvaux_softc *sc = device_private(dev);
struct tty *tp;
int i;
for (i = 0; i < NQVAUXLINE; i++) {
tp = sc->sc_qvaux[i].qvaux_tty;
if (((tp->t_state & TS_ISOPEN) == 0) || (tp->t_wopen == 0))
continue;
qvauxparam(tp, &tp->t_termios);
qvauxmctl(sc, i, DML_DTR, DMSET);
tp->t_state &= ~TS_BUSY;
qvauxstart(tp); /* Kick off transmitter again */
}
}
#if NQVKBD > 0 || NQVMS > 0
int
qvauxgetc(struct qvaux_linestate *ls)
{
#if 0
int line = ls->qvaux_line;
int s;
u_short rbuf;
s = spltty();
for (;;) {
for(; (dz->csr & DZ_CSR_RX_DONE) == 0;);
rbuf = dz->rbuf;
if (((rbuf >> 8) & 3) == line) {
splx(s);
return (rbuf & 0xff);
}
}
#endif
return 0;
}
void
qvauxputc(struct qvaux_linestate *ls, int ch)
{
//int line;
int s;
/* if the qvaux has already been attached, the MI
driver will do the transmitting: */
if (ls && ls->qvaux_sc) {
s = spltty();
// line = ls->qvaux_line;
putc(ch, &ls->qvaux_tty->t_outq);
qvauxstart(ls->qvaux_tty);
splx(s);
return;
}
/* use qvauxcnputc to do the transmitting: */
//qvauxcnputc(makedev(cdevsw_lookup_major(&qvaux_cdevsw), 0), ch);
}
#endif /* NQVKBD > 0 || NQVMS > 0 */

128
sys/arch/vax/uba/qvavar.h Normal file
View File

@ -0,0 +1,128 @@
/* $NetBSD: qvavar.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles H. Dickman
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996, 1997 Philip L. Budne.
* Copyright (c) 1993 Philip A. Nelson.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Philip A. Nelson.
* 4. The name of Philip A. Nelson may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY PHILIP NELSON ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL PHILIP NELSON BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* qvavar.h: definitions for qvss scn2681 DUART
*/
#ifndef _VAX_UBA_QVVAR_H_
#define _VAX_UBA_QVVAR_H_
/* Constants. */
#ifdef COMDEF_SPEED
#undef TTYDEF_SPEED
#define TTYDEF_SPEED COMDEF_SPEED /* default baud rate */
#endif
#define SCN_SIZE 0x10 /* address space for port */
#define SCN_CONSOLE 0 /* minor number of console */
#define SCN_CONSDUART 0
#define SCN_CONSCHAN 0
#define CH_SZ 16
#define DUART_SZ 32
#define SCN_REG(n) ((n) << 1) /* DUART bytes are word aligned */
#define QVA_FIRSTREG SCN_REG(0)
#define QVA_WINSIZE (SCN_REG(16) - SCN_REG(0))
/* A QVAUX is SCN2681 DUART */
#define NQVAUXLINE 2
#define QVA_C2I(c) (0) /* convert controller # to index */
#define QVA_I2C(c) (0) /* convert minor to controller # */
#define QVA_PORT(u) ((u)&01) /* extract the port # */
#define QVA_QVCSR (-32) /* offset to VCB01 CSR */
#define QVA_QVIC (QVA_QVCSR + 12) /* offset to VCB01 IC */
struct qvaux_softc {
device_t sc_dev; /* Autoconf blaha */
struct evcnt sc_rintrcnt; /* recevive interrupt counts */
struct evcnt sc_tintrcnt; /* transmit interrupt counts */
struct qvaux_regs sc_qr; /* reg pointers */
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
int sc_consline; /* console line, or -1 XXX */
int sc_rxint; /* Receive interrupt count XXX */
u_char sc_brk; /* Break asserted on some lines */
u_char sc_dsr; /* DSR set bits if no mdm ctrl */
int sc_imr; /* interrupts that are enabled */
struct qvaux_linestate {
struct qvaux_softc *qvaux_sc; /* backpointer to softc */
int qvaux_line; /* channel number */
void *qvaux_private; /* sub-driver data pointer */
int (*qvaux_catch)(void *, int); /* Fast catch recv */
struct tty *qvaux_tty; /* what we work on */
#ifdef notyet
void * qvaux_mem; /* pointers to clist output */
void * qvaux_end; /* allowing pdma action */
#endif
} sc_qvaux[NQVAUXLINE];
};
void qvauxattach(struct qvaux_softc *, struct evcnt *, int);
void qvauxint(void *);
void qvauxrint(void *);
void qvauxxint(void *);
void qvauxreset(device_t);
#endif /* _VAX_UBA_QVVAR_H_ */

315
sys/arch/vax/uba/qvkbd.c Normal file
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/* $NetBSD: qvkbd.c,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/* Copyright (c) 2015 Charles H. Dickman. All rights reserved.
* Derived from dzkbd.c
*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)kbd.c 8.2 (Berkeley) 10/30/93
*/
/*
* LK200/LK400 keyboard attached to line 0 of the QVSS aux port
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/ioctl.h>
#include <sys/syslog.h>
#include <sys/malloc.h>
#include <sys/intr.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wskbdvar.h>
#include <dev/wscons/wsksymdef.h>
#include <dev/wscons/wsksymvar.h>
#include <dev/dec/wskbdmap_lk201.h>
#include <sys/bus.h>
#include <vax/uba/qvareg.h>
#include <vax/uba/qvavar.h>
#include <vax/uba/qvkbdvar.h>
#include <dev/dec/lk201reg.h>
#include <dev/dec/lk201var.h>
#include "locators.h"
struct qvkbd_internal {
struct qvaux_linestate *qvi_ls;
struct lk201_state qvi_ks;
};
struct qvkbd_internal qvkbd_console_internal;
struct qvkbd_softc {
struct device qvkbd_dev; /* required first: base device */
struct qvkbd_internal *sc_itl;
int sc_enabled;
int kbd_type;
device_t sc_wskbddev;
};
static int qvkbd_input(void *, int);
static int qvkbd_match(device_t, cfdata_t, void *);
static void qvkbd_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(qvkbd, sizeof(struct qvkbd_softc),
qvkbd_match, qvkbd_attach, NULL, NULL);
static int qvkbd_enable(void *, int);
static void qvkbd_set_leds(void *, int);
static int qvkbd_ioctl(void *, u_long, void *, int, struct lwp *);
const struct wskbd_accessops qvkbd_accessops = {
qvkbd_enable,
qvkbd_set_leds,
qvkbd_ioctl,
};
static void qvkbd_cngetc(void *, u_int *, int *);
static void qvkbd_cnpollc(void *, int);
int qvkbd_cnattach(struct qvaux_linestate *);
const struct wskbd_consops qvkbd_consops = {
qvkbd_cngetc,
qvkbd_cnpollc,
};
static int qvkbd_sendchar(void *, u_char);
const struct wskbd_mapdata qvkbd_keymapdata = {
lkkbd_keydesctab,
#ifdef DZKBD_LAYOUT
DZKBD_LAYOUT,
#else
KB_US | KB_LK401,
#endif
};
/*
* kbd_match: how is this qvaux line configured?
*/
static int
qvkbd_match(device_t parent, cfdata_t cf, void *aux)
{
struct qvauxkm_attach_args *daa = aux;
/* Exact match is better than wildcard. */
if (cf->cf_loc[QVAUXCF_LINE] == daa->daa_line) {
//printf("qvkbd_match: return 2\n");
return 2;
}
/* This driver accepts wildcard. */
if (cf->cf_loc[QVAUXCF_LINE] == QVAUXCF_LINE_DEFAULT) {
//printf("qvkbd_match: return 1\n");
return 1;
}
//printf("qvkbd_match: return 0\n");
return 0;
}
static void
qvkbd_attach(device_t parent, device_t self, void *aux)
{
struct qvaux_softc *qvaux = device_private(parent);
struct qvkbd_softc *qvkbd = device_private(self);
struct qvauxkm_attach_args *daa = aux;
struct qvaux_linestate *ls;
struct qvkbd_internal *qvi;
struct wskbddev_attach_args a;
int isconsole;
qvaux->sc_qvaux[daa->daa_line].qvaux_catch = qvkbd_input;
qvaux->sc_qvaux[daa->daa_line].qvaux_private = qvkbd;
ls = &qvaux->sc_qvaux[daa->daa_line];
isconsole = (daa->daa_flags & QVAUXKBD_CONSOLE);
if (isconsole) {
qvi = &qvkbd_console_internal;
} else {
qvi = malloc(sizeof(struct qvkbd_internal),
M_DEVBUF, M_NOWAIT);
qvi->qvi_ks.attmt.sendchar = qvkbd_sendchar;
qvi->qvi_ks.attmt.cookie = ls;
}
qvi->qvi_ls = ls;
qvkbd->sc_itl = qvi;
printf("\n");
if (!isconsole) {
DELAY(100000);
lk201_init(&qvi->qvi_ks);
}
/* XXX should identify keyboard ID here XXX */
/* XXX layout and the number of LED is varying XXX */
/* XXX ID done during kb init XXX */
// qvkbd->kbd_type = WSKBD_TYPE_LK201;
qvkbd->sc_enabled = 1;
a.console = isconsole;
a.keymap = &qvkbd_keymapdata;
a.accessops = &qvkbd_accessops;
a.accesscookie = qvkbd;
qvkbd->sc_wskbddev = config_found(self, &a, wskbddevprint);
}
int
qvkbd_cnattach(struct qvaux_linestate *ls)
{
qvkbd_console_internal.qvi_ks.attmt.sendchar = qvkbd_sendchar;
qvkbd_console_internal.qvi_ks.attmt.cookie = ls;
lk201_init(&qvkbd_console_internal.qvi_ks);
qvkbd_console_internal.qvi_ls = ls;
wskbd_cnattach(&qvkbd_consops, &qvkbd_console_internal,
&qvkbd_keymapdata);
return 0;
}
static int
qvkbd_enable(void *v, int on)
{
struct qvkbd_softc *sc = v;
sc->sc_enabled = on;
return 0;
}
static int
qvkbd_sendchar(void *v, u_char c)
{
struct qvaux_linestate *ls = v;
int s;
s = spltty();
qvauxputc(ls, c);
splx(s);
return (0);
}
static void
qvkbd_cngetc(void *v, u_int *type, int *data)
{
struct qvkbd_internal *qvi = v;
int c;
do {
c = qvauxgetc(qvi->qvi_ls);
} while (!lk201_decode(&qvi->qvi_ks, 0, c, type, data));
}
static void
qvkbd_cnpollc(void *v, int on)
{
#if 0
struct qvkbd_internal *qvi = v;
#endif
}
static void
qvkbd_set_leds(void *v, int leds)
{
struct qvkbd_softc *sc = (struct qvkbd_softc *)v;
lk201_set_leds(&sc->sc_itl->qvi_ks, leds);
}
static int
qvkbd_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l)
{
struct qvkbd_softc *sc = (struct qvkbd_softc *)v;
switch (cmd) {
case WSKBDIO_GTYPE:
*(int *)data = sc->kbd_type;
return 0;
case WSKBDIO_SETLEDS:
lk201_set_leds(&sc->sc_itl->qvi_ks, *(int *)data);
return 0;
case WSKBDIO_GETLEDS:
/* XXX don't dig in kbd internals */
*(int *)data = sc->sc_itl->qvi_ks.leds_state;
return 0;
case WSKBDIO_COMPLEXBELL:
lk201_bell(&sc->sc_itl->qvi_ks,
(struct wskbd_bell_data *)data);
return 0;
case WSKBDIO_SETKEYCLICK:
lk201_set_keyclick(&sc->sc_itl->qvi_ks, *(int *)data);
return 0;
case WSKBDIO_GETKEYCLICK:
/* XXX don't dig in kbd internals */
*(int *)data = sc->sc_itl->qvi_ks.kcvol;
return 0;
}
return (EPASSTHROUGH);
}
static int
qvkbd_input(void *v, int data)
{
struct qvkbd_softc *sc = (struct qvkbd_softc *)v;
u_int type;
int val;
int decode;
do {
decode = lk201_decode(&sc->sc_itl->qvi_ks, 1,
data, &type, &val);
if (decode != LKD_NODATA)
wskbd_input(sc->sc_wskbddev, type, val);
} while (decode == LKD_MORE);
return(1);
}

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/* $NetBSD: qvkbdvar.h,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles H. Dickman
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _VAX_UBA_QVKBDVAR_H_
#define _VAX_UBA_QVKBDVAR_H_
struct qvauxkm_attach_args {
int daa_line; /* Line to search */
int daa_flags; /* Console etc...*/
#define QVAUXKBD_CONSOLE 1
};
/* These functions must be present for the keyboard/mouse to work */
int qvauxgetc(struct qvaux_linestate *);
void qvauxputc(struct qvaux_linestate *, int);
void qvauxsetlpr(struct qvaux_linestate *, int);
/* Exported functions */
int qvauxkbd_cnattach(struct qvaux_linestate *);
#endif /* _VAX_UBA_QVKBDVAR_H_ */

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/* $NetBSD: qvms.c,v 1.1 2015/07/05 03:07:21 matt Exp $ */
/* Copyright (c) 2015 Charles H. Dickman. All rights reserved.
* Derived from dzms.c
*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ms.c 8.1 (Berkeley) 6/11/93
*/
/*
* VSXXX mice attached to line 1 of the QVSS
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: qvms.c,v 1.1 2015/07/05 03:07:21 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/ioctl.h>
#include <sys/syslog.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/tty.h>
#include <sys/bus.h>
#include <vax/uba/qvareg.h>
#include <vax/uba/qvavar.h>
#include <vax/uba/qvkbdvar.h>
#include <dev/dec/lk201.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wsmousevar.h>
#include "locators.h"
struct qvms_softc { /* driver status information */
struct device qvms_dev; /* required first: base device */
struct qvaux_linestate *qvms_ls;
int sc_enabled; /* input enabled? */
int sc_selftest;
int inputstate;
u_int buttons;
int dx, dy;
device_t sc_wsmousedev;
};
static int qvms_match(device_t, cfdata_t, void *);
static void qvms_attach(device_t, device_t, void *);
static int qvms_input(void *, int);
CFATTACH_DECL_NEW(qvms, sizeof(struct qvms_softc),
qvms_match, qvms_attach, NULL, NULL);
static int qvms_enable(void *);
static int qvms_ioctl(void *, u_long, void *, int, struct lwp *);
static void qvms_disable(void *);
const struct wsmouse_accessops qvms_accessops = {
qvms_enable,
qvms_ioctl,
qvms_disable,
};
static int
qvms_match(device_t parent, cfdata_t cf, void *aux)
{
struct qvauxkm_attach_args *daa = aux;
/* Exact match is better than wildcard. */
if (cf->cf_loc[QVAUXCF_LINE] == daa->daa_line)
return 2;
/* This driver accepts wildcard. */
if (cf->cf_loc[QVAUXCF_LINE] == QVAUXCF_LINE_DEFAULT)
return 1;
return 0;
}
static void
qvms_attach(device_t parent, device_t self, void *aux)
{
struct qvaux_softc *qvaux = device_private(parent);
struct qvms_softc *qvms = device_private(self);
struct qvauxkm_attach_args *daa = aux;
struct qvaux_linestate *ls;
struct wsmousedev_attach_args a;
qvaux->sc_qvaux[daa->daa_line].qvaux_catch = qvms_input;
qvaux->sc_qvaux[daa->daa_line].qvaux_private = qvms;
ls = &qvaux->sc_qvaux[daa->daa_line];
qvms->qvms_ls = ls;
printf("\n");
a.accessops = &qvms_accessops;
a.accesscookie = qvms;
qvms->sc_enabled = 0;
qvms->sc_selftest = 0;
qvms->sc_wsmousedev = config_found(self, &a, wsmousedevprint);
}
static int
qvms_enable(void *v)
{
struct qvms_softc *sc = v;
if (sc->sc_enabled)
return EBUSY;
sc->sc_selftest = 4; /* wait for 4 byte reply upto 1/2 sec */
qvauxputc(sc->qvms_ls, MOUSE_SELF_TEST);
(void)tsleep(qvms_enable, TTIPRI, "qvmsopen", hz / 2);
if (sc->sc_selftest != 0) {
sc->sc_selftest = 0;
return ENXIO;
}
DELAY(150);
qvauxputc(sc->qvms_ls, MOUSE_INCREMENTAL);
sc->sc_enabled = 1;
sc->inputstate = 0;
return 0;
}
static void
qvms_disable(void *v)
{
struct qvms_softc *sc = v;
sc->sc_enabled = 0;
}
static int
qvms_ioctl(void *v, u_long cmd, void *data, int flag, struct lwp *l)
{
if (cmd == WSMOUSEIO_GTYPE) {
*(u_int *)data = WSMOUSE_TYPE_VSXXX;
return 0;
}
return EPASSTHROUGH;
}
static int
qvms_input(void *vsc, int data)
{
struct qvms_softc *sc = vsc;
if (sc->sc_enabled == 0) {
if (sc->sc_selftest > 0) {
sc->sc_selftest -= 1;
if (sc->sc_selftest == 0)
wakeup(qvms_enable);
}
return (1);
}
#define WSMS_BUTTON1 0x01
#define WSMS_BUTTON2 0x02
#define WSMS_BUTTON3 0x04
if ((data & MOUSE_START_FRAME) != 0)
sc->inputstate = 1;
else
sc->inputstate++;
if (sc->inputstate == 1) {
sc->buttons = 0;
if ((data & LEFT_BUTTON) != 0)
sc->buttons |= WSMS_BUTTON1;
if ((data & MIDDLE_BUTTON) != 0)
sc->buttons |= WSMS_BUTTON2;
if ((data & RIGHT_BUTTON) != 0)
sc->buttons |= WSMS_BUTTON3;
sc->dx = data & MOUSE_X_SIGN;
sc->dy = data & MOUSE_Y_SIGN;
} else if (sc->inputstate == 2) {
if (sc->dx == 0)
sc->dx = -data;
else
sc->dx = data;
} else if (sc->inputstate == 3) {
sc->inputstate = 0;
if (sc->dy == 0)
sc->dy = -data;
else
sc->dy = data;
wsmouse_input(sc->sc_wsmousedev,
sc->buttons,
sc->dx, sc->dy, 0, 0,
WSMOUSE_INPUT_DELTA);
}
return(1);
}