an alternative clock implementation for Loongson2F and SM502, mostly
Gdium-specific. This supports Loongson2F frequency scaling. The problem is that Gdium has no CPU clock independent high resolution timer we can use as a timecounter so we use one of the SM502's PWMs to generate a 100Hz timer interrupt, use the cp0 counter to measure time and adjust for frequency changes. Other Loongson-based machines will need something similar but hopefully less hackish.
This commit is contained in:
macallan
parent
e89302ed7b
commit
e9495f5c0f
@ -3,7 +3,17 @@
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define voyagerbus {}
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# the graphics part
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device voyagerfb: wsemuldisplaydev, rasops8, rasops16, rasops32, vcons, videomode, iic, i2c_bitbang
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device voyagerfb: wsemuldisplaydev, rasops8, rasops16, vcons, videomode, iic, i2c_bitbang
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attach voyagerfb at voyagerbus
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file dev/pci/voyager/voyagerfb.c voyagerfb
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file dev/pci/voyager/voyagerfb.c voyagerfb needs-flag
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defflag opt_voyagerfb.h VOYAGERFB_DEBUG
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# a clock timer
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device pwmclock
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attach pwmclock at voyagerbus
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file dev/pci/voyager/pwmclock.c pwmclock needs-flag
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# the audio part
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device vac: audiobus, auconv, mulaw
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attach vac at voyagerbus
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file dev/pci/voyager/vac.c vac needs-flag
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355
sys/dev/pci/voyager/pwmclock.c
Normal file
355
sys/dev/pci/voyager/pwmclock.c
Normal file
@ -0,0 +1,355 @@
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/* $NetBSD: pwmclock.c,v 1.1 2011/12/13 14:39:37 macallan Exp $ */
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/*
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* Copyright (c) 2011 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pwmclock.c,v 1.1 2011/12/13 14:39:37 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/cpu.h>
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#include <sys/timetc.h>
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#include <sys/sysctl.h>
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#include <dev/pci/voyagervar.h>
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#include <dev/ic/sm502reg.h>
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#include <mips/mips3_clock.h>
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#include <mips/locore.h>
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#include <mips/bonito/bonitoreg.h>
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#include <mips/bonito/bonitovar.h>
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#ifdef PWMCLOCK_DEBUG
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#define DPRINTF aprint_error
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#else
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#define DPRINTF while (0) printf
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#endif
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int pwmclock_intr(void *);
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struct pwmclock_softc {
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device_t sc_dev;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_regh;
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uint32_t sc_reg, sc_last;
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uint32_t sc_scale[8];
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uint32_t sc_count; /* should probably be 64 bit */
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int sc_step;
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int sc_step_wanted;
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};
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static int pwmclock_match(device_t, cfdata_t, void *);
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static void pwmclock_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(pwmclock, sizeof(struct pwmclock_softc),
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pwmclock_match, pwmclock_attach, NULL, NULL);
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static void pwmclock_start(void);
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static u_int get_pwmclock_timecount(struct timecounter *);
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struct pwmclock_softc *pwmclock;
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extern void (*initclocks_ptr)(void);
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extern struct clockframe cf;
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/* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */
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static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1};
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static int scale_d[] = {0, 4, 8, 2, 8, 4, 8, 1};
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#define scale(x, f) (x * scale_d[f] / scale_m[f])
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void pwmclock_set_speed(struct pwmclock_softc *, int);
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static int pwmclock_cpuspeed_temp(SYSCTLFN_ARGS);
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static int pwmclock_cpuspeed_cur(SYSCTLFN_ARGS);
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static int pwmclock_cpuspeed_available(SYSCTLFN_ARGS);
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static struct timecounter pwmclock_timecounter = {
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get_pwmclock_timecount, /* get_timecount */
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0, /* no poll_pps */
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0xffffffff, /* counter_mask */
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0, /* frequency */
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"pwm", /* name */
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100, /* quality */
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NULL, /* tc_priv */
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NULL /* tc_next */
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};
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static int
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pwmclock_match(device_t parent, cfdata_t match, void *aux)
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{
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struct voyager_attach_args *vaa = (struct voyager_attach_args *)aux;
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if (strcmp(vaa->vaa_name, "pwmclock") == 0) return 100;
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return 0;
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}
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static uint32_t
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pwmclock_wait_edge(struct pwmclock_softc *sc)
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{
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/* clear interrupt */
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bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg);
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while ((bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1) & SM502_PWM_INTR_PENDING) == 0);
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return mips3_cp0_count_read();
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}
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static void
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pwmclock_attach(device_t parent, device_t self, void *aux)
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{
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struct pwmclock_softc *sc = device_private(self);
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struct voyager_attach_args *vaa = aux;
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const struct sysctlnode *sysctl_node, *me, *freq;
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uint32_t reg, last, curr, diff, acc;
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int i, clk;
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sc->sc_dev = self;
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sc->sc_memt = vaa->vaa_tag;
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sc->sc_regh = vaa->vaa_regh;
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aprint_normal("\n");
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voyager_establish_intr(parent, 22, pwmclock_intr, sc);
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reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */
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reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR | SM502_PWM_INTR_PENDING;
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sc->sc_reg = reg;
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pwmclock = sc;
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initclocks_ptr = pwmclock_start;
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/* ok, let's see how far the cycle counter gets between interrupts */
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aprint_normal_dev(sc->sc_dev, "calibrating CPU timer...\n");
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for (clk = 1; clk < 8; clk++) {
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REGVAL(LS2F_CHIPCFG0) = (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | clk;
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bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg);
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acc = 0;
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last = pwmclock_wait_edge(sc);
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for (i = 0; i < 16; i++) {
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curr = pwmclock_wait_edge(sc);
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diff = curr - last;
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acc += diff;
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last = curr;
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}
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sc->sc_scale[clk] = (acc >> 4) / 5000;
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}
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for (clk = 1; clk < 8; clk++) {
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aprint_normal_dev(sc->sc_dev, "%d/8: %d\n", clk + 1, sc->sc_scale[clk]);
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}
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sc->sc_step = 7;
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sc->sc_step_wanted = 7;
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/* now setup sysctl */
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if (sysctl_createv(NULL, 0, NULL,
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&me,
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CTLFLAG_READWRITE, CTLTYPE_NODE, "loongson", NULL, NULL,
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0, NULL, 0, CTL_MACHDEP, CTL_CREATE, CTL_EOL) != 0)
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aprint_error_dev(sc->sc_dev, "couldn't create 'loongson' node\n");
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if (sysctl_createv(NULL, 0, NULL,
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&freq,
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CTLFLAG_READWRITE, CTLTYPE_NODE, "frequency", NULL, NULL,
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0, NULL, 0, CTL_MACHDEP, me->sysctl_num, CTL_CREATE, CTL_EOL) != 0)
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aprint_error_dev(sc->sc_dev, "couldn't create 'frequency' node\n");
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if (sysctl_createv(NULL, 0, NULL,
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&sysctl_node,
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CTLFLAG_READWRITE | CTLFLAG_OWNDESC,
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CTLTYPE_INT, "target", "CPU speed", pwmclock_cpuspeed_temp,
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0, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num,
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CTL_CREATE, CTL_EOL) == 0) {
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} else
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aprint_error_dev(sc->sc_dev, "couldn't create 'target' node\n");
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if (sysctl_createv(NULL, 0, NULL,
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&sysctl_node,
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CTLFLAG_READWRITE,
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CTLTYPE_INT, "current", NULL, pwmclock_cpuspeed_cur,
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1, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num,
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CTL_CREATE, CTL_EOL) == 0) {
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} else
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aprint_error_dev(sc->sc_dev, "couldn't create 'current' node\n");
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if (sysctl_createv(NULL, 0, NULL,
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&sysctl_node,
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CTLFLAG_READWRITE,
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CTLTYPE_STRING, "available", NULL, pwmclock_cpuspeed_available,
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2, sc, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num,
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CTL_CREATE, CTL_EOL) == 0) {
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} else
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aprint_error_dev(sc->sc_dev, "couldn't create 'available' node\n");
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}
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void
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pwmclock_set_speed(struct pwmclock_softc *sc, int speed)
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{
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if ((speed < 1) || (speed > 7))
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return;
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sc->sc_step_wanted = speed;
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DPRINTF("%s: %d\n", __func__, speed);
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}
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/*
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* the PWM interrupt handler
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* we don't have a CPU clock independent, high resolution counter so we're
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* stuck with a PWM that can't count and a CP0 counter that slows down or
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* speeds up with the actual CPU speed. In order to still get halfway
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* accurate time we do the following:
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* - only change CPU speed in the timer interrupt
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* - each timer interrupt we measure how many CP0 cycles passed since last
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* time, adjust for CPU speed since we can be sure it didn't change, use
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* that to update a separate counter
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* - when reading the time counter we take the number of CP0 ticks since
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* the last timer interrupt, scale it to CPU clock, return that plus the
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* interrupt updated counter mentioned above to get something close to
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* CP0 running at full speed
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* - when changing CPU speed do it as close to taking the time from CP0 as
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* possible to keep the period of time we spend with CP0 running at the
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* wrong frequency as short as possible - hopefully short enough to stay
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* insignificant compared to other noise since switching speeds isn't
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* going to happen all that often
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*/
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int
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pwmclock_intr(void *cookie)
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{
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struct pwmclock_softc *sc = cookie;
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uint32_t reg, now, diff;
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/* is it us? */
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reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1);
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if ((reg & SM502_PWM_INTR_PENDING) == 0)
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return 0;
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/* yes, it's us, so clear the interrupt */
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bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg);
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/*
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* this looks kinda funny but what we want here is this:
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* - reading the counter and changing the CPU clock should be as
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* close together as possible in order to remain halfway accurate
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* - we need to use the previous sc_step in order to scale the
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* interval passed since the last clock interrupt correctly, so
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* we only change sc_step after doing that
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*/
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if (sc->sc_step_wanted != sc->sc_step) {
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REGVAL(LS2F_CHIPCFG0) =
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(REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) |
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sc->sc_step_wanted;
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}
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now = mips3_cp0_count_read();
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diff = now - sc->sc_last;
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sc->sc_count += scale(diff, sc->sc_step);
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sc->sc_last = now;
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if (sc->sc_step_wanted != sc->sc_step) {
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sc->sc_step = sc->sc_step_wanted;
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}
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hardclock(&cf);
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return 1;
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}
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static void
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pwmclock_start()
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{
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struct pwmclock_softc *sc = pwmclock;
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sc->sc_count = 0;
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sc->sc_last = mips3_cp0_count_read();
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pwmclock_timecounter.tc_frequency = curcpu()->ci_cpu_freq / 2;
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tc_init(&pwmclock_timecounter);
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bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_PWM1, sc->sc_reg);
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}
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static u_int
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get_pwmclock_timecount(struct timecounter *tc)
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{
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struct pwmclock_softc *sc = pwmclock;
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uint32_t now, diff;
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now = mips3_cp0_count_read();
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diff = now - sc->sc_last;
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return sc->sc_count + scale(diff, sc->sc_step);
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}
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static int
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pwmclock_cpuspeed_temp(SYSCTLFN_ARGS)
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{
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struct sysctlnode node = *rnode;
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struct pwmclock_softc *sc = node.sysctl_data;
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int mhz, i;
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mhz = sc->sc_scale[sc->sc_step_wanted];
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node.sysctl_data = &mhz;
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if (sysctl_lookup(SYSCTLFN_CALL(&node)) == 0) {
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int new_reg;
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new_reg = *(int *)node.sysctl_data;
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i = 1;
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while ((i < 8) && (sc->sc_scale[i] != new_reg))
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i++;
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if (i > 7)
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return EINVAL;
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pwmclock_set_speed(sc, i);
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return 0;
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}
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return EINVAL;
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}
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static int
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pwmclock_cpuspeed_cur(SYSCTLFN_ARGS)
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{
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struct sysctlnode node = *rnode;
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struct pwmclock_softc *sc = node.sysctl_data;
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int mhz;
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mhz = sc->sc_scale[sc->sc_step];
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node.sysctl_data = &mhz;
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return sysctl_lookup(SYSCTLFN_CALL(&node));
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}
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static int
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pwmclock_cpuspeed_available(SYSCTLFN_ARGS)
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{
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struct sysctlnode node = *rnode;
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struct pwmclock_softc *sc = node.sysctl_data;
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char buf[128];
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snprintf(buf, 128, "%d %d %d %d %d %d %d", sc->sc_scale[1],
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sc->sc_scale[2], sc->sc_scale[3], sc->sc_scale[4],
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sc->sc_scale[5], sc->sc_scale[6], sc->sc_scale[7]);
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node.sysctl_data = buf;
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return(sysctl_lookup(SYSCTLFN_CALL(&node)));
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}
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SYSCTL_SETUP(sysctl_ams_setup, "sysctl obio subtree setup")
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{
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sysctl_createv(NULL, 0, NULL, NULL,
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CTLFLAG_PERMANENT,
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CTLTYPE_NODE, "machdep", NULL,
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NULL, 0, NULL, 0,
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CTL_MACHDEP, CTL_EOL);
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}
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Loading…
Reference in New Issue
Block a user