import the original openbsd "schizo" PCI driver as found on US-III systems.
This commit is contained in:
mrg
parent
6f91da5c30
commit
e8f7f45249
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@ -0,0 +1,789 @@
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/* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
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/*
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* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2003 Henric Jungheim
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/reboot.h>
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#define _SPARC_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/psl.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <sparc64/dev/iommureg.h>
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#include <sparc64/dev/iommuvar.h>
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#include <sparc64/dev/schizoreg.h>
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#include <sparc64/dev/schizovar.h>
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#include <sparc64/sparc64/cache.h>
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#ifdef DEBUG
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#define SDB_PROM 0x01
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#define SDB_BUSMAP 0x02
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#define SDB_INTR 0x04
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#define SDB_CONF 0x08
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int schizo_debug = ~0;
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#define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0)
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#else
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#define DPRINTF(l, s)
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#endif
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extern struct sparc_pci_chipset _sparc_pci_chipset;
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int schizo_match(struct device *, void *, void *);
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void schizo_attach(struct device *, struct device *, void *);
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void schizo_init(struct schizo_softc *, int);
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void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *);
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int schizo_print(void *, const char *);
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void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int,
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int (*handler)(void *), void *, int, char *);
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int schizo_ue(void *);
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int schizo_ce(void *);
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int schizo_safari_error(void *);
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int schizo_pci_error(void *);
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pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int,
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pci_chipset_tag_t);
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bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *);
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bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *);
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bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *);
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bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *,
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int, int, int);
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bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *);
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pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int);
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void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
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int schizo_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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int schizo_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t,
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bus_size_t, int, bus_space_handle_t *);
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paddr_t schizo_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t,
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int, int);
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bus_addr_t schizo_bus_addr(bus_space_tag_t, bus_space_tag_t,
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bus_space_handle_t);
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void *schizo_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int,
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int (*)(void *), void *, const char *);
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int schizo_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *);
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int
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schizo_match(struct device *parent, void *match, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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char *str;
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if (strcmp(ma->ma_name, "pci") != 0)
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return (0);
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str = getpropstring(ma->ma_node, "model");
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if (strcmp(str, "schizo") == 0)
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return (1);
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str = getpropstring(ma->ma_node, "compatible");
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if (strcmp(str, "pci108e,8001") == 0)
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return (1);
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if (strcmp(str, "pci108e,8002") == 0) /* XMITS */
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return (1);
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if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */
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return (1);
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return (0);
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}
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void
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schizo_attach(struct device *parent, struct device *self, void *aux)
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{
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struct schizo_softc *sc = (struct schizo_softc *)self;
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struct mainbus_attach_args *ma = aux;
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int busa;
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char *str;
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str = getpropstring(ma->ma_node, "compatible");
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if (strcmp(str, "pci108e,a801") == 0)
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sc->sc_tomatillo = 1;
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sc->sc_node = ma->ma_node;
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sc->sc_dmat = ma->ma_dmatag;
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sc->sc_bust = ma->ma_bustag;
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sc->sc_ctrl = ma->ma_reg[1].ur_paddr - 0x10000UL;
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sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
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if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
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busa = 1;
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else
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busa = 0;
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if (bus_space_map(sc->sc_bust, sc->sc_ctrl,
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sizeof(struct schizo_regs), 0, &sc->sc_ctrlh)) {
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printf(": failed to map registers\n");
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return;
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}
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/* enable schizo ecc error interrupts */
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schizo_write(sc, SCZ_ECCCTRL, schizo_read(sc, SCZ_ECCCTRL) |
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SCZ_ECCCTRL_EE_INTEN | SCZ_ECCCTRL_UE_INTEN |
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SCZ_ECCCTRL_CE_INTEN);
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schizo_init(sc, busa);
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}
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void
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schizo_init(struct schizo_softc *sc, int busa)
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{
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struct schizo_pbm *pbm;
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struct pcibus_attach_args pba;
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int *busranges = NULL, nranges;
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u_int64_t match, reg;
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pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (pbm == NULL)
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panic("schizo: can't alloc schizo pbm");
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pbm->sp_sc = sc;
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pbm->sp_bus_a = busa;
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pbm->sp_regt = sc->sc_bust;
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if (getprop(sc->sc_node, "ranges", sizeof(struct schizo_range),
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&pbm->sp_nrange, (void **)&pbm->sp_range))
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panic("schizo: can't get ranges");
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if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
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(void **)&busranges))
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panic("schizo: can't get bus-range");
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printf(": \"%s\", version %d, ign %x, bus %c %d to %d\n",
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sc->sc_tomatillo ? "Tomatillo" : "Schizo",
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getpropint(sc->sc_node, "version#", 0), sc->sc_ign,
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busa ? 'A' : 'B', busranges[0], busranges[1]);
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if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh,
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busa ? offsetof(struct schizo_regs, pbm_a) :
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offsetof(struct schizo_regs, pbm_b),
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sizeof(struct schizo_pbm_regs),
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&pbm->sp_regh)) {
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panic("schizo: unable to create PBM handle");
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}
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printf("%s: ", sc->sc_dv.dv_xname);
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schizo_init_iommu(sc, pbm);
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match = schizo_read(sc, busa ? SCZ_PCIA_IO_MATCH : SCZ_PCIB_IO_MATCH);
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pbm->sp_confpaddr = match & ~0x8000000000000000UL;
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pbm->sp_memt = schizo_alloc_mem_tag(pbm);
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pbm->sp_iot = schizo_alloc_io_tag(pbm);
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pbm->sp_cfgt = schizo_alloc_config_tag(pbm);
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pbm->sp_dmat = schizo_alloc_dma_tag(pbm);
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if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh))
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panic("schizo: could not map config space");
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pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node,
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&_sparc_pci_chipset);
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pbm->sp_pc->bustag = pbm->sp_cfgt;
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pbm->sp_pc->bushandle = pbm->sp_cfgh;
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pba.pba_busname = "pci";
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pba.pba_domain = pci_ndomains++;
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pba.pba_bus = busranges[0];
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pba.pba_bridgetag = NULL;
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pba.pba_pc = pbm->sp_pc;
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#if 0
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pba.pba_flags = pbm->sp_flags;
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#endif
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pba.pba_dmat = pbm->sp_dmat;
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pba.pba_memt = pbm->sp_memt;
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pba.pba_iot = pbm->sp_iot;
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pba.pba_pc->conf_read = schizo_conf_read;
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pba.pba_pc->conf_write = schizo_conf_write;
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pba.pba_pc->intr_map = schizo_intr_map;
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free(busranges, M_DEVBUF);
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schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5);
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/* clear out the bus errors */
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schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL));
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schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR));
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schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG,
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schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG));
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reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);
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/* enable/disable error interrupts and arbiter */
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reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT | SCZ_PCICTRL_ARB;
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reg &= ~SCZ_PCICTRL_SBH_INT;
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schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);
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reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);
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reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |
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SCZ_PCIDIAG_D_INTSYNC);
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schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
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if (busa)
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
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pbm, SCZ_PCIERR_A_INO, "pci_a");
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else
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
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pbm, SCZ_PCIERR_B_INO, "pci_b");
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/* double mapped */
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO,
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"ue");
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO,
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"ce");
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schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
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SCZ_SERR_INO, "safari");
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config_found(&sc->sc_dv, &pba, schizo_print);
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}
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int
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schizo_ue(void *vsc)
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{
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struct schizo_softc *sc = vsc;
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panic("%s: uncorrectable error", sc->sc_dv.dv_xname);
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return (1);
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}
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int
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schizo_ce(void *vsc)
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{
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struct schizo_softc *sc = vsc;
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panic("%s: correctable error", sc->sc_dv.dv_xname);
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return (1);
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}
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int
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schizo_pci_error(void *vpbm)
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{
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struct schizo_pbm *sp = vpbm;
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struct schizo_softc *sc = sp->sp_sc;
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u_int64_t afsr, afar, ctrl;
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u_int32_t csr;
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afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR);
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afar = schizo_pbm_read(sp, SCZ_PCI_AFAR);
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ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL);
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csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG);
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printf("%s: pci bus %c error\n", sc->sc_dv.dv_xname,
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sp->sp_bus_a ? 'A' : 'B');
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printf("PCIAFSR=%lb\n", afsr, SCZ_PCIAFSR_BITS);
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printf("PCIAFAR=%lx\n", afar);
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printf("PCICTRL=%lb\n", ctrl, SCZ_PCICTRL_BITS);
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printf("PCICSR=%b\n", csr, PCI_COMMAND_STATUS_BITS);
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if (ctrl & SCZ_PCICTRL_MMU_ERR) {
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u_int32_t ctrl, tfar;
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ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL);
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printf("IOMMUCTRL=%lx\n", ctrl);
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if ((ctrl & TOM_IOMMU_ERR) == 0)
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goto clear_error;
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if (sc->sc_tomatillo) {
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tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR);
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printf("IOMMUTFAR=%lx\n", tfar);
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}
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/* These are non-fatal if target abort was signalled. */
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if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR ||
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ctrl & TOM_IOMMU_ILLTSBTBW_ERR ||
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ctrl & TOM_IOMMU_BADVA_ERR) {
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if (csr & PCI_STATUS_TARGET_TARGET_ABORT) {
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schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl);
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goto clear_error;
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}
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}
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}
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panic("%s: fatal", sc->sc_dv.dv_xname);
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clear_error:
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schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr);
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schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl);
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schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr);
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return (1);
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}
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int
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schizo_safari_error(void *vsc)
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{
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struct schizo_softc *sc = vsc;
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printf("%s: safari error\n", sc->sc_dv.dv_xname);
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printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG));
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printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR));
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printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR));
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printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR));
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printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR));
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panic("%s: fatal", sc->sc_dv.dv_xname);
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return (1);
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}
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void
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schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm)
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{
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struct iommu_state *is = &pbm->sp_is;
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int *vdma = NULL, nitem, tsbsize = 7;
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u_int32_t iobase = -1;
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vaddr_t va;
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char *name;
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va = (vaddr_t)pbm->sp_flush[0x40];
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is->is_bustag = pbm->sp_regt;
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if (bus_space_subregion(is->is_bustag, pbm->sp_regh,
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offsetof(struct schizo_pbm_regs, iommu),
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sizeof(struct iommureg), &is->is_iommu)) {
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panic("schizo: unable to create iommu handle");
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}
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is->is_sb[0] = &pbm->sp_sb;
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is->is_sb[0]->sb_bustag = is->is_bustag;
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is->is_sb[0]->sb_flush = (void *)(va & ~0x3f);
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if (bus_space_subregion(is->is_bustag, pbm->sp_regh,
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offsetof(struct schizo_pbm_regs, strbuf),
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sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb)) {
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panic("schizo: unable to create streaming buffer handle");
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is->is_sb[0]->sb_flush = NULL;
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}
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#if 1
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/* XXX disable the streaming buffers for now */
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bus_space_write_8(is->is_bustag, is->is_sb[0]->sb_sb,
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STRBUFREG(strbuf_ctl),
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bus_space_read_8(is->is_bustag, is->is_sb[0]->sb_sb,
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STRBUFREG(strbuf_ctl)) & ~STRBUF_EN);
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is->is_sb[0]->sb_flush = NULL;
|
||||
#endif
|
||||
|
||||
name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
|
||||
if (name == NULL)
|
||||
panic("couldn't malloc iommu name");
|
||||
snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname);
|
||||
|
||||
/*
|
||||
* Separate the men from the boys. If the `virtual-dma'
|
||||
* property exists, use it.
|
||||
*/
|
||||
if (!getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem,
|
||||
(void **)&vdma)) {
|
||||
/* Damn. Gotta use these values. */
|
||||
iobase = vdma[0];
|
||||
#define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break
|
||||
switch (vdma[1]) {
|
||||
TSBCASE(1); TSBCASE(2); TSBCASE(3);
|
||||
TSBCASE(4); TSBCASE(5); TSBCASE(6);
|
||||
default:
|
||||
printf("bogus tsb size %x, using 7\n", vdma[1]);
|
||||
TSBCASE(7);
|
||||
}
|
||||
#undef TSBCASE
|
||||
DPRINTF(SDB_BUSMAP, ("schizo_iommu_init: iobase=0x%x\n", iobase));
|
||||
free(vdma, M_DEVBUF);
|
||||
} else {
|
||||
DPRINTF(SDB_BUSMAP, ("schizo_iommu_init: getprop failed, "
|
||||
"using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize));
|
||||
}
|
||||
|
||||
iommu_init(name, is, tsbsize, iobase);
|
||||
}
|
||||
|
||||
int
|
||||
schizo_print(void *aux, const char *p)
|
||||
{
|
||||
if (p == NULL)
|
||||
return (UNCONF);
|
||||
return (QUIET);
|
||||
}
|
||||
|
||||
pcireg_t
|
||||
schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
|
||||
{
|
||||
return (bus_space_read_4(pc->bustag, pc->bushandle,
|
||||
PCITAG_OFFSET(tag) + reg));
|
||||
}
|
||||
|
||||
void
|
||||
schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
|
||||
{
|
||||
bus_space_write_4(pc->bustag, pc->bushandle,
|
||||
PCITAG_OFFSET(tag) + reg, data);
|
||||
}
|
||||
|
||||
/*
|
||||
* Bus-specific interrupt mapping
|
||||
*/
|
||||
int
|
||||
schizo_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
|
||||
{
|
||||
struct schizo_pbm *sp = pa->pa_pc->cookie;
|
||||
struct schizo_softc *sc = sp->sp_sc;
|
||||
u_int dev;
|
||||
|
||||
if (*ihp != (pci_intr_handle_t)-1) {
|
||||
*ihp |= sc->sc_ign;
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* We didn't find a PROM mapping for this interrupt. Try to
|
||||
* construct one ourselves based on the swizzled interrupt pin
|
||||
* and the interrupt mapping for PCI slots documented in the
|
||||
* UltraSPARC-IIi User's Manual.
|
||||
*/
|
||||
|
||||
if (pa->pa_intrpin == 0)
|
||||
return (-1);
|
||||
|
||||
/*
|
||||
* This deserves some documentation. Should anyone
|
||||
* have anything official looking, please speak up.
|
||||
*/
|
||||
dev = pa->pa_device - 1;
|
||||
|
||||
*ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT;
|
||||
*ihp |= (dev << 2) & INTMAP_PCISLOT;
|
||||
*ihp |= sc->sc_ign;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl,
|
||||
int (*handler)(void *), void *arg, int ino, char *what)
|
||||
{
|
||||
struct intrhand *ih;
|
||||
volatile u_int64_t *map, *clr;
|
||||
struct schizo_pbm_regs *pbmreg;
|
||||
char *name;
|
||||
int nlen;
|
||||
|
||||
pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh);
|
||||
map = &pbmreg->imap[ino];
|
||||
clr = &pbmreg->iclr[ino];
|
||||
ino |= sc->sc_ign;
|
||||
|
||||
nlen = strlen(sc->sc_dv.dv_xname) + 1 + strlen(what) + 1;
|
||||
name = malloc(nlen, M_DEVBUF, M_WAITOK);
|
||||
snprintf(name, nlen, "%s:%s", sc->sc_dv.dv_xname, what);
|
||||
|
||||
ih = bus_intr_allocate(pbm->sp_regt, handler, arg, ino, ipl,
|
||||
map, clr, name);
|
||||
if (ih == NULL) {
|
||||
printf("set_intr failed...\n");
|
||||
free(name, M_DEVBUF);
|
||||
return;
|
||||
}
|
||||
|
||||
intr_establish(ih->ih_pil, ih);
|
||||
}
|
||||
|
||||
bus_space_tag_t
|
||||
schizo_alloc_mem_tag(struct schizo_pbm *sp)
|
||||
{
|
||||
return (schizo_alloc_bus_tag(sp, "mem",
|
||||
0x02, /* 32-bit mem space (where's the #define???) */
|
||||
ASI_PRIMARY, ASI_PRIMARY_LITTLE));
|
||||
}
|
||||
|
||||
bus_space_tag_t
|
||||
schizo_alloc_io_tag(struct schizo_pbm *sp)
|
||||
{
|
||||
return (schizo_alloc_bus_tag(sp, "io",
|
||||
0x01, /* IO space (where's the #define???) */
|
||||
ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED));
|
||||
}
|
||||
|
||||
bus_space_tag_t
|
||||
schizo_alloc_config_tag(struct schizo_pbm *sp)
|
||||
{
|
||||
return (schizo_alloc_bus_tag(sp, "cfg",
|
||||
0x00, /* Config space (where's the #define???) */
|
||||
ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED));
|
||||
}
|
||||
|
||||
bus_space_tag_t
|
||||
schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int ss,
|
||||
int asi, int sasi)
|
||||
{
|
||||
struct schizo_softc *sc = pbm->sp_sc;
|
||||
struct sparc_bus_space_tag *bt;
|
||||
|
||||
bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (bt == NULL)
|
||||
panic("schizo: could not allocate bus tag");
|
||||
|
||||
snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)",
|
||||
sc->sc_dv.dv_xname, name, ss, asi);
|
||||
|
||||
bt->cookie = pbm;
|
||||
bt->parent = sc->sc_bust;
|
||||
bt->default_type = ss;
|
||||
bt->asi = asi;
|
||||
bt->sasi = sasi;
|
||||
bt->sparc_bus_map = schizo_bus_map;
|
||||
bt->sparc_bus_mmap = schizo_bus_mmap;
|
||||
bt->sparc_bus_addr = schizo_bus_addr;
|
||||
bt->sparc_intr_establish = schizo_intr_establish;
|
||||
return (bt);
|
||||
}
|
||||
|
||||
bus_dma_tag_t
|
||||
schizo_alloc_dma_tag(struct schizo_pbm *pbm)
|
||||
{
|
||||
struct schizo_softc *sc = pbm->sp_sc;
|
||||
bus_dma_tag_t dt, pdt = sc->sc_dmat;
|
||||
|
||||
dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (dt == NULL)
|
||||
panic("schizo: could not alloc dma tag");
|
||||
|
||||
dt->_cookie = pbm;
|
||||
dt->_parent = pdt;
|
||||
dt->_dmamap_create = schizo_dmamap_create;
|
||||
dt->_dmamap_destroy = iommu_dvmamap_destroy;
|
||||
dt->_dmamap_load = iommu_dvmamap_load;
|
||||
dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
|
||||
dt->_dmamap_unload = iommu_dvmamap_unload;
|
||||
dt->_dmamap_sync = iommu_dvmamap_sync;
|
||||
dt->_dmamem_alloc = iommu_dvmamem_alloc;
|
||||
dt->_dmamem_free = iommu_dvmamem_free;
|
||||
dt->_dmamem_map = iommu_dvmamem_map;
|
||||
dt->_dmamem_unmap = iommu_dvmamem_unmap;
|
||||
return (dt);
|
||||
}
|
||||
|
||||
pci_chipset_tag_t
|
||||
schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc)
|
||||
{
|
||||
pci_chipset_tag_t npc;
|
||||
|
||||
npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT);
|
||||
if (npc == NULL)
|
||||
panic("schizo: could not allocate pci_chipset_tag_t");
|
||||
memcpy(npc, pc, sizeof *pc);
|
||||
npc->cookie = pbm;
|
||||
npc->rootnode = node;
|
||||
return (npc);
|
||||
}
|
||||
|
||||
int
|
||||
schizo_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size,
|
||||
int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
|
||||
bus_dmamap_t *dmamp)
|
||||
{
|
||||
struct schizo_pbm *sp = t->_cookie;
|
||||
|
||||
return (iommu_dvmamap_create(t, t0, &sp->sp_sb, size, nsegments,
|
||||
maxsegsz, boundary, flags, dmamp));
|
||||
}
|
||||
|
||||
int
|
||||
schizo_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset,
|
||||
bus_size_t size, int flags, bus_space_handle_t *hp)
|
||||
{
|
||||
struct schizo_pbm *pbm = t->cookie;
|
||||
int i, ss;
|
||||
|
||||
DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d",
|
||||
t->default_type,
|
||||
(unsigned long long)offset,
|
||||
(unsigned long long)size,
|
||||
flags));
|
||||
|
||||
ss = t->default_type;
|
||||
DPRINTF(SDB_BUSMAP, (" cspace %d", ss));
|
||||
|
||||
if (t->parent == 0 || t->parent->sparc_bus_map == 0) {
|
||||
printf("\nschizo_bus_map: invalid parent");
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & BUS_SPACE_MAP_PROMADDRESS) {
|
||||
return ((*t->parent->sparc_bus_map)
|
||||
(t, t0, offset, size, flags, hp));
|
||||
}
|
||||
|
||||
for (i = 0; i < pbm->sp_nrange; i++) {
|
||||
bus_addr_t paddr;
|
||||
|
||||
if (((pbm->sp_range[i].cspace >> 24) & 0x03) != ss)
|
||||
continue;
|
||||
|
||||
paddr = pbm->sp_range[i].phys_lo + offset;
|
||||
paddr |= ((bus_addr_t)pbm->sp_range[i].phys_hi) << 32;
|
||||
return ((*t->parent->sparc_bus_map)
|
||||
(t, t0, paddr, size, flags, hp));
|
||||
}
|
||||
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
paddr_t
|
||||
schizo_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr,
|
||||
off_t off, int prot, int flags)
|
||||
{
|
||||
bus_addr_t offset = paddr;
|
||||
struct schizo_pbm *pbm = t->cookie;
|
||||
int i, ss;
|
||||
|
||||
ss = t->default_type;
|
||||
|
||||
DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n",
|
||||
prot, flags, (unsigned long long)paddr));
|
||||
|
||||
if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) {
|
||||
printf("\nschizo_bus_mmap: invalid parent");
|
||||
return (-1);
|
||||
}
|
||||
|
||||
for (i = 0; i < pbm->sp_nrange; i++) {
|
||||
bus_addr_t paddr;
|
||||
|
||||
if (((pbm->sp_range[i].cspace >> 24) & 0x03) != ss)
|
||||
continue;
|
||||
|
||||
paddr = pbm->sp_range[i].phys_lo + offset;
|
||||
paddr |= ((bus_addr_t)pbm->sp_range[i].phys_hi<<32);
|
||||
return ((*t->parent->sparc_bus_mmap)
|
||||
(t, t0, paddr, off, prot, flags));
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
bus_addr_t
|
||||
schizo_bus_addr(bus_space_tag_t t, bus_space_tag_t t0, bus_space_handle_t h)
|
||||
{
|
||||
struct schizo_pbm *pbm = t->cookie;
|
||||
bus_addr_t addr;
|
||||
int i, ss;
|
||||
|
||||
ss = t->default_type;
|
||||
|
||||
if (t->parent == 0 || t->parent->sparc_bus_addr == 0) {
|
||||
printf("\nschizo_bus_addr: invalid parent");
|
||||
return (-1);
|
||||
}
|
||||
|
||||
t = t->parent;
|
||||
|
||||
addr = ((*t->sparc_bus_addr)(t, t0, h));
|
||||
if (addr == -1)
|
||||
return (-1);
|
||||
|
||||
for (i = 0; i < pbm->sp_nrange; i++) {
|
||||
if (((pbm->sp_range[i].cspace >> 24) & 0x03) != ss)
|
||||
continue;
|
||||
|
||||
return (BUS_ADDR_PADDR(addr) - pbm->sp_range[i].phys_lo);
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
void *
|
||||
schizo_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle,
|
||||
int level, int flags, int (*handler)(void *), void *arg, const char *what)
|
||||
{
|
||||
struct schizo_pbm *pbm = t->cookie;
|
||||
struct intrhand *ih = NULL;
|
||||
volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL;
|
||||
int ino;
|
||||
long vec = INTVEC(ihandle);
|
||||
|
||||
vec = INTVEC(ihandle);
|
||||
ino = INTINO(vec);
|
||||
|
||||
if (level == IPL_NONE)
|
||||
level = INTLEV(vec);
|
||||
if (level == IPL_NONE) {
|
||||
printf(": no IPL, setting IPL 2.\n");
|
||||
level = 2;
|
||||
}
|
||||
|
||||
if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) {
|
||||
struct schizo_pbm_regs *pbmreg;
|
||||
|
||||
pbmreg = bus_space_vaddr(pbm->sp_regt, pbm->sp_regh);
|
||||
intrmapptr = &pbmreg->imap[ino];
|
||||
intrclrptr = &pbmreg->iclr[ino];
|
||||
if (INTIGN(vec) == 0)
|
||||
ino |= (*intrmapptr) & INTMAP_IGN;
|
||||
else
|
||||
ino |= vec & INTMAP_IGN;
|
||||
}
|
||||
|
||||
ih = bus_intr_allocate(t0, handler, arg, ino, level, intrmapptr,
|
||||
intrclrptr, what);
|
||||
if (ih == NULL)
|
||||
return (NULL);
|
||||
|
||||
intr_establish(ih->ih_pil, ih);
|
||||
|
||||
if (intrmapptr != NULL) {
|
||||
u_int64_t intrmap;
|
||||
|
||||
intrmap = *intrmapptr;
|
||||
intrmap |= INTMAP_V;
|
||||
*intrmapptr = intrmap;
|
||||
intrmap = *intrmapptr;
|
||||
ih->ih_number |= intrmap & INTMAP_INR;
|
||||
}
|
||||
|
||||
return (ih);
|
||||
}
|
||||
|
||||
const struct cfattach schizo_ca = {
|
||||
sizeof(struct schizo_softc), schizo_match, schizo_attach
|
||||
};
|
||||
|
||||
struct cfdriver schizo_cd = {
|
||||
NULL, "schizo", DV_DULL
|
||||
};
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
/* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
struct schizo_pbm_regs {
|
||||
volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */
|
||||
struct iommureg iommu; /* 0x0200 - 0x03ff */
|
||||
volatile u_int64_t _unused2[384];
|
||||
volatile u_int64_t imap[64];
|
||||
volatile u_int64_t _unused3[64];
|
||||
volatile u_int64_t iclr[64];
|
||||
volatile u_int64_t _unused4[320];
|
||||
volatile u_int64_t ctrl;
|
||||
volatile u_int64_t __unused0;
|
||||
volatile u_int64_t afsr;
|
||||
volatile u_int64_t afar;
|
||||
volatile u_int64_t _unused5[252];
|
||||
struct iommu_strbuf strbuf;
|
||||
volatile u_int64_t strbuf_ctxflush;
|
||||
volatile u_int64_t _unused6[4012];
|
||||
volatile u_int64_t iommu_tag;
|
||||
volatile u_int64_t _unused7[15];
|
||||
volatile u_int64_t iommu_data;
|
||||
volatile u_int64_t _unused8[63];
|
||||
volatile u_int64_t istat[2];
|
||||
volatile u_int64_t _unused9[2814];
|
||||
volatile u_int64_t strbuf_ctxmatch;
|
||||
volatile u_int64_t _unused10[122879];
|
||||
};
|
||||
|
||||
struct schizo_regs {
|
||||
volatile u_int64_t _unused0[8];
|
||||
volatile u_int64_t pcia_mem_match;
|
||||
volatile u_int64_t pcia_mem_mask;
|
||||
volatile u_int64_t pcia_io_match;
|
||||
volatile u_int64_t pcia_io_mask;
|
||||
volatile u_int64_t pcib_mem_match;
|
||||
volatile u_int64_t pcib_mem_mask;
|
||||
volatile u_int64_t pcib_io_match;
|
||||
volatile u_int64_t pcib_io_mask;
|
||||
volatile u_int64_t _unused1[8176];
|
||||
|
||||
volatile u_int64_t control_status;
|
||||
volatile u_int64_t error_control;
|
||||
volatile u_int64_t interrupt_control;
|
||||
volatile u_int64_t safari_errlog;
|
||||
volatile u_int64_t eccctrl;
|
||||
volatile u_int64_t _unused3[1];
|
||||
volatile u_int64_t ue_afsr;
|
||||
volatile u_int64_t ue_afar;
|
||||
volatile u_int64_t ce_afsr;
|
||||
volatile u_int64_t ce_afar;
|
||||
|
||||
volatile u_int64_t _unused4[253942];
|
||||
struct schizo_pbm_regs pbm_a;
|
||||
struct schizo_pbm_regs pbm_b;
|
||||
};
|
||||
|
||||
#define SCZ_PCIA_MEM_MATCH 0x00040
|
||||
#define SCZ_PCIA_MEM_MASK 0x00048
|
||||
#define SCZ_PCIA_IO_MATCH 0x00050
|
||||
#define SCZ_PCIA_IO_MASK 0x00058
|
||||
#define SCZ_PCIB_MEM_MATCH 0x00060
|
||||
#define SCZ_PCIB_MEM_MASK 0x00068
|
||||
#define SCZ_PCIB_IO_MATCH 0x00070
|
||||
#define SCZ_PCIB_IO_MASK 0x00078
|
||||
#define SCZ_CONTROL_STATUS 0x10000
|
||||
#define SCZ_SAFARI_INTCTRL 0x10010
|
||||
#define SCZ_SAFARI_ERRLOG 0x10018
|
||||
#define SCZ_ECCCTRL 0x10020
|
||||
#define SCZ_UE_AFSR 0x10030
|
||||
#define SCZ_UE_AFAR 0x10038
|
||||
#define SCZ_CE_AFSR 0x10040
|
||||
#define SCZ_CE_AFAR 0x10048
|
||||
|
||||
/* These are relative to the PBM */
|
||||
#define SCZ_PCI_IOMMU_CTRL 0x00200
|
||||
#define SCZ_PCI_IOMMU_TSBBASE 0x00208
|
||||
#define SCZ_PCI_IOMMU_FLUSH 0x00210
|
||||
#define SCZ_PCI_IOMMU_CTXFLUSH 0x00218
|
||||
#define TOM_PCI_IOMMU_TFAR 0x00220
|
||||
#define SCZ_PCI_IMAP_BASE 0x01000
|
||||
#define SCZ_PCI_ICLR_BASE 0x01400
|
||||
#define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */
|
||||
#define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */
|
||||
#define SCZ_PCI_CTRL 0x02000
|
||||
#define SCZ_PCI_AFSR 0x02010
|
||||
#define SCZ_PCI_AFAR 0x02018
|
||||
#define SCZ_PCI_DIAG 0x02020
|
||||
#define SCZ_PCI_ESTAR 0x02028
|
||||
#define SCZ_PCI_STRBUF_CTRL 0x02800
|
||||
#define SCZ_PCI_STRBUF_FLUSH 0x02808
|
||||
#define SCZ_PCI_STRBUF_FSYNC 0x02810
|
||||
#define SCZ_PCI_STRBUF_CTXFLUSH 0x02818
|
||||
#define SCZ_PCI_IOMMU_TAG 0x0a580
|
||||
#define SCZ_PCI_IOMMU_DATA 0x0a600
|
||||
#define SCZ_PCI_STRBUF_CTXMATCH 0x10000
|
||||
|
||||
#define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL
|
||||
#define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL
|
||||
#define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL
|
||||
|
||||
#define SCZ_UEAFSR_PPIO 0x8000000000000000UL
|
||||
#define SCZ_UEAFSR_PDRD 0x4000000000000000UL
|
||||
#define SCZ_UEAFSR_PDWR 0x2000000000000000UL
|
||||
#define SCZ_UEAFSR_SPIO 0x1000000000000000UL
|
||||
#define SCZ_UEAFSR_SDMA 0x0800000000000000UL
|
||||
#define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL
|
||||
#define SCZ_UEAFSR_BMSK 0x000003ff00000000UL
|
||||
#define SCZ_UEAFSR_QOFF 0x00000000c0000000UL
|
||||
#define SCZ_UEAFSR_AID 0x000000001f000000UL
|
||||
#define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL
|
||||
#define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL
|
||||
#define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL
|
||||
#define SCZ_UEAFSR_MTAG 0x000000000000e000UL
|
||||
#define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL
|
||||
|
||||
#define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */
|
||||
#define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */
|
||||
#define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */
|
||||
#define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */
|
||||
#define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */
|
||||
#define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */
|
||||
#define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */
|
||||
#define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */
|
||||
#define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */
|
||||
#define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */
|
||||
#define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */
|
||||
#define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */
|
||||
#define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */
|
||||
#define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */
|
||||
|
||||
#define SCZ_CEAFSR_PPIO 0x8000000000000000UL
|
||||
#define SCZ_CEAFSR_PDRD 0x4000000000000000UL
|
||||
#define SCZ_CEAFSR_PDWR 0x2000000000000000UL
|
||||
#define SCZ_CEAFSR_SPIO 0x1000000000000000UL
|
||||
#define SCZ_CEAFSR_SDMA 0x0800000000000000UL
|
||||
#define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL
|
||||
#define SCZ_CEAFSR_BMSK 0x000003ff00000000UL
|
||||
#define SCZ_CEAFSR_QOFF 0x00000000c0000000UL
|
||||
#define SCZ_CEAFSR_AID 0x000000001f000000UL
|
||||
#define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL
|
||||
#define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL
|
||||
#define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL
|
||||
#define SCZ_CEAFSR_MTAG 0x000000000000e000UL
|
||||
#define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL
|
||||
|
||||
#define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */
|
||||
#define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */
|
||||
#define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */
|
||||
#define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */
|
||||
#define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */
|
||||
#define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */
|
||||
#define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */
|
||||
#define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */
|
||||
#define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */
|
||||
#define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */
|
||||
#define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */
|
||||
#define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */
|
||||
#define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */
|
||||
#define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */
|
||||
|
||||
#define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */
|
||||
#define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */
|
||||
#define TOM_PCICTRL_DTO_INT (1UL << 61UL) /* discard intr en */
|
||||
#define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */
|
||||
#define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */
|
||||
#define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */
|
||||
#define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */
|
||||
#define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */
|
||||
#define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */
|
||||
#define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */
|
||||
#define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */
|
||||
#define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */
|
||||
#define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */
|
||||
#define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */
|
||||
#define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */
|
||||
#define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */
|
||||
#define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */
|
||||
#define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */
|
||||
#define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST"
|
||||
|
||||
#define SCZ_PCIAFSR_PMA 0x8000000000000000UL
|
||||
#define SCZ_PCIAFSR_PTA 0x4000000000000000UL
|
||||
#define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL
|
||||
#define SCZ_PCIAFSR_PPERR 0x1000000000000000UL
|
||||
#define SCZ_PCIAFSR_PTTO 0x0800000000000000UL
|
||||
#define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL
|
||||
#define SCZ_PCIAFSR_SMA 0x0200000000000000UL
|
||||
#define SCZ_PCIAFSR_STA 0x0100000000000000UL
|
||||
#define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL
|
||||
#define SCZ_PCIAFSR_SPERR 0x0040000000000000UL
|
||||
#define SCZ_PCIAFSR_STTO 0x0020000000000000UL
|
||||
#define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL
|
||||
#define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL
|
||||
#define SCZ_PCIAFSR_BLK 0x0000000080000000UL
|
||||
#define SCZ_PCIAFSR_CFG 0x0000000040000000UL
|
||||
#define SCZ_PCIAFSR_MEM 0x0000000020000000UL
|
||||
#define SCZ_PCIAFSR_IO 0x0000000010000000UL
|
||||
|
||||
#define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO"
|
||||
|
||||
#define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */
|
||||
#define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */
|
||||
#define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */
|
||||
#define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */
|
||||
#define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */
|
||||
#define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */
|
||||
#define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */
|
||||
#define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */
|
||||
#define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */
|
||||
|
||||
#define TOM_IOMMU_ERR (1UL << 24)
|
||||
#define TOM_IOMMU_ERR_MASK (3UL << 25)
|
||||
#define TOM_IOMMU_PROT_ERR (0UL << 25)
|
||||
#define TOM_IOMMU_INV_ERR (1UL << 25)
|
||||
#define TOM_IOMMU_TO_ERR (2UL << 25)
|
||||
#define TOM_IOMMU_ECC_ERR (3UL << 25)
|
||||
#define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27)
|
||||
#define TOM_IOMMU_BADVA_ERR (1UL << 28)
|
||||
|
||||
#define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL)
|
||||
#define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL)
|
||||
|
||||
#define SCZ_UE_INO 0x30 /* uncorrectable error */
|
||||
#define SCZ_CE_INO 0x31 /* correctable ecc error */
|
||||
#define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */
|
||||
#define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */
|
||||
#define SCZ_SERR_INO 0x34 /* safari interface error */
|
||||
|
||||
struct schizo_range {
|
||||
u_int32_t cspace;
|
||||
u_int32_t child_hi;
|
||||
u_int32_t child_lo;
|
||||
u_int32_t phys_hi;
|
||||
u_int32_t phys_lo;
|
||||
u_int32_t size_hi;
|
||||
u_int32_t size_lo;
|
||||
};
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/* $OpenBSD: schizovar.h,v 1.10 2007/01/14 16:19:49 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Jason L. Wright (jason@thought.net)
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
struct schizo_pbm {
|
||||
struct schizo_softc *sp_sc;
|
||||
|
||||
struct schizo_range *sp_range;
|
||||
pci_chipset_tag_t sp_pc;
|
||||
int sp_nreg;
|
||||
int sp_nrange;
|
||||
int sp_nintmap;
|
||||
|
||||
bus_space_tag_t sp_memt;
|
||||
bus_space_tag_t sp_iot;
|
||||
bus_space_tag_t sp_regt;
|
||||
bus_space_handle_t sp_regh;
|
||||
bus_space_tag_t sp_cfgt;
|
||||
bus_space_handle_t sp_cfgh;
|
||||
bus_dma_tag_t sp_dmat;
|
||||
int sp_bus;
|
||||
int sp_flags;
|
||||
int sp_bus_a;
|
||||
bus_addr_t sp_confpaddr;
|
||||
struct iommu_state sp_is;
|
||||
struct strbuf_ctl sp_sb;
|
||||
char sp_flush[0x80];
|
||||
};
|
||||
|
||||
struct schizo_softc {
|
||||
struct device sc_dv;
|
||||
int sc_node;
|
||||
int sc_ign;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
bus_space_tag_t sc_bust;
|
||||
bus_addr_t sc_ctrl;
|
||||
bus_space_handle_t sc_ctrlh;
|
||||
|
||||
int sc_tomatillo;
|
||||
};
|
||||
|
||||
#define schizo_read(sc,r) \
|
||||
bus_space_read_8((sc)->sc_bust, (sc)->sc_ctrlh, (r))
|
||||
#define schizo_write(sc,r,v) \
|
||||
bus_space_write_8((sc)->sc_bust, (sc)->sc_ctrlh, (r), (v))
|
||||
#define schizo_pbm_read(pbm,r) \
|
||||
bus_space_read_8((pbm)->sp_regt, (pbm)->sp_regh, (r))
|
||||
#define schizo_pbm_write(pbm,r,v) \
|
||||
bus_space_write_8((pbm)->sp_regt, (pbm)->sp_regh, (r), (v))
|
||||
#define schizo_cfg_read(pbm,r) \
|
||||
bus_space_read_4((pbm)->sp_cfgt, (pbm)->sp_cfgh, (r))
|
||||
#define schizo_cfg_write(pbm,r,v) \
|
||||
bus_space_write_4((pbm)->sp_cfgt, (pbm)->sp_cfgh, (r), (v))
|
||||
Loading…
Reference in New Issue