add the missing bits to allow X to run in 24bit with the wsfb driver
still no hardware acceleration though
This commit is contained in:
macallan
parent
dbd4d2db70
commit
e8eb2869bf
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@ -1,4 +1,4 @@
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/* $NetBSD: cgtwelve.c,v 1.2 2010/04/08 16:49:34 macallan Exp $ */
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/* $NetBSD: cgtwelve.c,v 1.3 2010/04/14 04:37:11 macallan Exp $ */
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/*-
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* Copyright (c) 2010 Michael Lorenz
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@ -29,7 +29,7 @@
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/* a console driver for the Sun CG12 / Matrox SG3 graphics board */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cgtwelve.c,v 1.2 2010/04/08 16:49:34 macallan Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cgtwelve.c,v 1.3 2010/04/14 04:37:11 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -62,8 +62,12 @@ __KERNEL_RCSID(0, "$NetBSD: cgtwelve.c,v 1.2 2010/04/08 16:49:34 macallan Exp $"
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struct cgtwelve_softc {
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device_t sc_dev;
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bus_space_tag_t sc_tag;
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bus_space_handle_t sc_regh;
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bus_addr_t sc_paddr;
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void *sc_fbaddr;
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void *sc_shadow;
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uint8_t *sc_wids;
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void *sc_int;
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int sc_width;
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int sc_height;
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int sc_stride;
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@ -79,6 +83,15 @@ static int cgtwelve_ioctl(void *, void *, u_long, void *, int,
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static paddr_t cgtwelve_mmap(void *, void *, off_t, int);
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static void cgtwelve_init_screen(void *, struct vcons_screen *, int,
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long *);
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static void cgtwelve_write_wid(struct cgtwelve_softc *, int, uint8_t);
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static void cgtwelve_select_ovl(struct cgtwelve_softc *, int);
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#define CG12_SEL_OVL 0
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#define CG12_SEL_ENABLE 1
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#define CG12_SEL_8BIT 2
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#define CG12_SEL_24BIT 3
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#define CG12_SEL_WID 4
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static void cgtwelve_write_dac(struct cgtwelve_softc *, int, int, int, int);
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static void cgtwelve_setup(struct cgtwelve_softc *, int);
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CFATTACH_DECL_NEW(cgtwelve, sizeof(struct cgtwelve_softc),
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cgtwelve_match, cgtwelve_attach, NULL, NULL);
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@ -143,6 +156,8 @@ cgtwelve_attach(device_t parent, device_t self, void *args)
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sc->sc_dev = self;
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sc->sc_tag = sa->sa_bustag;
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sc->sc_paddr = sbus_bus_addr(sa->sa_bustag, sa->sa_slot, sa->sa_offset);
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/* read geometry information from the device tree */
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sc->sc_width = prom_getpropint(sa->sa_node, "width", 1152);
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sc->sc_height = prom_getpropint(sa->sa_node, "height", 900);
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@ -164,6 +179,40 @@ cgtwelve_attach(device_t parent, device_t self, void *args)
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aprint_normal_dev(self, "%d x %d\n", sc->sc_width, sc->sc_height);
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset + CG12_OFF_REGISTERS,
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0xc0000, 0, &sc->sc_regh) != 0) {
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aprint_error("%s: couldn't map registers\n",
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device_xname(sc->sc_dev));
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return;
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}
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset + CG12_OFF_WID, 0x100000,
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BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_LARGE,
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&bh) != 0) {
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aprint_error("%s: couldn't map WID\n",
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device_xname(sc->sc_dev));
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return;
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}
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sc->sc_wids = bus_space_vaddr(sa->sa_bustag, bh);
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset + CG12_OFF_INTEN, 0x400000,
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BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_LARGE,
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&bh) != 0) {
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aprint_error("%s: couldn't map colour fb\n",
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device_xname(sc->sc_dev));
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return;
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}
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sc->sc_int = bus_space_vaddr(sa->sa_bustag, bh);
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cgtwelve_setup(sc, 1);
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sc->sc_shadow = kmem_alloc(sc->sc_fbsize, KM_SLEEP);
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isconsole = fb_is_console(node);
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@ -176,8 +225,6 @@ cgtwelve_attach(device_t parent, device_t self, void *args)
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vcons_init_screen(&sc->vd, &cgtwelve_console_screen, 1, &defattr);
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cgtwelve_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
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memset(sc->sc_fbaddr, 0, sc->sc_fbsize);
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ri = &cgtwelve_console_screen.scr_ri;
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cgtwelve_defscreendesc.nrows = ri->ri_rows;
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@ -196,11 +243,9 @@ cgtwelve_attach(device_t parent, device_t self, void *args)
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aa.accesscookie = &sc->vd;
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config_found(self, &aa, wsemuldisplaydevprint);
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#if 0
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset + CG12_OFF_REGISTERS,
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0xc0000, 0, &bh) == 0) {
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#if 0
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{
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bus_space_handle_r bh = sc->sc_regh;
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int i, j;
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bus_space_write_4(sa->sa_bustag, bh, CG12_EIC_RESET, 0);
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@ -260,12 +305,157 @@ cgtwelve_attach(device_t parent, device_t self, void *args)
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}
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printf("\n");
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}
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bus_space_unmap(sa->sa_bustag, bh, 0xc0000);
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}
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panic("poof");
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#endif
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}
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/* 0 - overlay plane, 1 - enable plane, 2 - 8bit fb, 3 - 24bit fb, 4 - WIDs */
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static void
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cgtwelve_select_ovl(struct cgtwelve_softc *sc, int which)
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{
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switch(which) {
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case 0:
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_RDMSK_HOST, CG12_PLN_RD_OVERLAY);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_WRMSK_HOST, CG12_PLN_WR_OVERLAY);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_SL_HOST, CG12_PLN_SL_OVERLAY);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HPAGE, CG12_HPAGE_OVERLAY);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HACCESS, CG12_HACCESS_OVERLAY);
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break;
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case 1:
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_RDMSK_HOST, CG12_PLN_RD_ENABLE);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_WRMSK_HOST, CG12_PLN_WR_ENABLE);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_SL_HOST, CG12_PLN_SL_ENABLE);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HPAGE, CG12_HPAGE_ENABLE);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HACCESS, CG12_HACCESS_ENABLE);
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break;
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case 2:
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_RDMSK_HOST, CG12_PLN_RD_8BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_WRMSK_HOST, CG12_PLN_WR_8BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_SL_HOST, CG12_PLN_SL_8BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HPAGE, CG12_HPAGE_8BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HACCESS, CG12_HACCESS_8BIT);
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break;
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case 3:
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_RDMSK_HOST, CG12_PLN_RD_24BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_WRMSK_HOST, CG12_PLN_WR_24BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_SL_HOST, CG12_PLN_SL_24BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HPAGE, CG12_HPAGE_24BIT);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HACCESS, CG12_HACCESS_24BIT);
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break;
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case 4:
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_RDMSK_HOST, CG12_PLN_RD_WID);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_WRMSK_HOST, CG12_PLN_WR_WID);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12DPU_PLN_SL_HOST, CG12_PLN_SL_WID);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HPAGE, CG12_HPAGE_WID);
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bus_space_write_4(sc->sc_tag, sc->sc_regh,
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CG12APU_HACCESS, CG12_HACCESS_WID);
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break;
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}
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}
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static void
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cgtwelve_write_wid(struct cgtwelve_softc *sc, int idx, uint8_t wid)
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{
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bus_space_write_4(sc->sc_tag, sc->sc_regh, CG12_WSC_ADDR, idx << 16);
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bus_space_write_4(sc->sc_tag, sc->sc_regh, CG12_WSC_DATA,
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((uint32_t)wid) << 16);
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}
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static void
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cgtwelve_write_dac(struct cgtwelve_softc *sc, int idx, int r, int g, int b)
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{
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uint32_t lo = (idx & 0xff);
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uint32_t hi = (idx >> 8) & 0xff;
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lo |= lo << 8 | lo << 16;
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hi |= hi << 8 | hi << 16;
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bus_space_write_4(sc->sc_tag, sc->sc_regh, CG12DAC_ADDR0, lo);
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bus_space_write_4(sc->sc_tag, sc->sc_regh, CG12DAC_ADDR1, hi);
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bus_space_write_4(sc->sc_tag, sc->sc_regh, CG12DAC_DATA,
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b << 16 | g << 8 | r);
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}
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static void
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cgtwelve_setup(struct cgtwelve_softc *sc, int depth)
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{
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int i;
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/* first let's put some stuff into the WID table */
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cgtwelve_write_wid(sc, 0, CG12_WID_8_BIT);
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cgtwelve_write_wid(sc, 1, CG12_WID_24_BIT);
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/* a linear ramp for the gamma table */
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for (i = 0; i < 256; i++)
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cgtwelve_write_dac(sc, i + 0x100, i, i, i);
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switch(depth) {
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case 1:
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/* setup the console */
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/* first, make the overlay all opaque */
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cgtwelve_select_ovl(sc, CG12_SEL_ENABLE);
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memset(sc->sc_fbaddr, 0xff, 0x20000);
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/* now write the right thing into the WID plane */
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cgtwelve_select_ovl(sc, CG12_SEL_WID);
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memset(sc->sc_wids, 0, 0x100000);
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/* now clean the plane */
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cgtwelve_select_ovl(sc, CG12_SEL_OVL);
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memset(sc->sc_fbaddr, 0, 0x20000);
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break;
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case 24:
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case 32:
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/* setup the 24bit fb for X */
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/*
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* first clean the 24bit fb - for aesthetic reasons do it while
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* it's still not visible ( we hope... )
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*/
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cgtwelve_select_ovl(sc, CG12_SEL_24BIT);
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memset(sc->sc_int, 0x80, 0x400000);
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/* now write the right thing into the WID plane */
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cgtwelve_select_ovl(sc, CG12_SEL_WID);
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memset(sc->sc_wids, 1, 0x100000);
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/* hide the overlay */
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cgtwelve_select_ovl(sc, CG12_SEL_ENABLE);
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memset(sc->sc_fbaddr, 0, 0x20000);
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/* now clean the plane */
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cgtwelve_select_ovl(sc, CG12_SEL_OVL);
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memset(sc->sc_fbaddr, 0, 0x20000);
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/* and make sure we can write the 24bit fb */
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cgtwelve_select_ovl(sc, CG12_SEL_24BIT);
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break;
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}
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}
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static void
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cgtwelve_init_screen(void *cookie, struct vcons_screen *scr,
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@ -297,11 +487,57 @@ static int
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cgtwelve_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
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struct lwp *l)
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{
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struct vcons_data *vd = v;
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struct cgtwelve_softc *sc = vd->cookie;
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struct wsdisplay_fbinfo *wdf;
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struct vcons_screen *ms = vd->active;
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switch (cmd) {
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case WSDISPLAYIO_GTYPE:
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*(u_int *)data = WSDISPLAY_TYPE_SUNCG12;
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return 0;
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case WSDISPLAYIO_GINFO:
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wdf = (void *)data;
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wdf->height = sc->sc_height;
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wdf->width = sc->sc_width;
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wdf->depth = 32;
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wdf->cmsize = 256;
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return 0;
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case FBIOGVIDEO:
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case WSDISPLAYIO_GVIDEO:
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*(int *)data = 1;
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return 0;
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case WSDISPLAYIO_SVIDEO:
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case FBIOSVIDEO:
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/* when we figure out how to do this... */
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/*cgtwelve_set_video(sc, *(int *)data);*/
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return 0;
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case WSDISPLAYIO_LINEBYTES:
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{
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int *ret = (int *)data;
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*ret = sc->sc_width << 2;
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}
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return 0;
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case WSDISPLAYIO_SMODE:
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{
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int new_mode = *(int*)data;
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if (new_mode != sc->sc_mode)
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{
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sc->sc_mode = new_mode;
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if (new_mode == WSDISPLAYIO_MODE_EMUL)
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{
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cgtwelve_setup(sc, 1);
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vcons_redraw_screen(ms);
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} else {
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cgtwelve_setup(sc, 32);
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}
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}
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}
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}
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return EPASSTHROUGH;
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@ -310,15 +546,13 @@ cgtwelve_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
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static paddr_t
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cgtwelve_mmap(void *v, void *vs, off_t offset, int prot)
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{
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struct cgtwelve_softc *sc = v;
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struct vcons_data *vd = v;
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struct cgtwelve_softc *sc = vd->cookie;
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/* regular fb mapping at 0 */
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if ((offset >= 0) && (offset < sc->sc_fbsize)) {
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#if 0
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return bus_space_mmap(sc->sc_tag, sc->sc_paddr,
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CG12_FB_MONO + offset, prot,
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BUS_SPACE_MAP_LINEAR);
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#endif
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if ((offset >= 0) && (offset < 0x400000)) {
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return bus_space_mmap(sc->sc_tag, sc->sc_paddr + CG12_OFF_INTEN,
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offset, prot, BUS_SPACE_MAP_LINEAR);
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}
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return -1;
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|
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@ -1,4 +1,4 @@
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/* $NetBSD: cgtwelvereg.h,v 1.1 2010/03/24 00:33:06 macallan Exp $ */
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/* $NetBSD: cgtwelvereg.h,v 1.2 2010/04/14 04:37:11 macallan Exp $ */
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/*-
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* Copyright (c) 2010 Michael Lorenz
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@ -26,7 +26,10 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* some hardware constants for the CG12 / Matrox SG3 */
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/*
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* some hardware constants for the CG12 / Matrox SG3
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* mostly from SMI's cg12reg.h
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*/
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#ifndef CG12REG_H
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#define CG12REG_H
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@ -34,4 +37,261 @@
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/* SBus offsets known so far */
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#define CG12_FB_MONO 0x780000
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#define CG12_OFF_PROM 0x000000
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#define CG12_OFF_USSC 0x040000
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#define CG12_OFF_REGISTERS 0x040000
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#define CG12_OFF_DPU 0x040100
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#define CG12_OFF_APU 0x040200
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#define CG12_OFF_DAC 0x040300
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#define CG12_OFF_DAC_ADDR0 0x040300
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#define CG12_OFF_DAC_ADDR1 0x040400
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#define CG12_OFF_DAC_CTRL 0x040500
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#define CG12_OFF_DAC_PRIME 0x040600
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#define CG12_OFF_EIC 0x040700
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#define CG12_OFF_WSC 0x040800
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#define CG12_OFF_WSC_DATA 0x040800
|
||||
#define CG12_OFF_WSC_ADDR 0x040900
|
||||
#define CG12_OFF_DRAM 0x400000
|
||||
#define CG12_OFF_SHMEM CG12_OFF_DRAM + 0x0E0000
|
||||
#define CG12_OFF_DISPLAY 0x600000
|
||||
#define CG12_OFF_WID 0x600000
|
||||
#define CG12_OFF_OVERLAY0 0x700000
|
||||
#define CG12_OFF_OVERLAY1 0x780000
|
||||
#define CG12_OFF_INTEN 0x800000
|
||||
#define CG12_OFF_DEPTH 0xC00000
|
||||
|
||||
#define CG12_OFF_CTL CG12_OFF_USSC /* 0x040000 */
|
||||
|
||||
#define CG12_PROM_SIZE 0x010000
|
||||
#define CG12_USSC_SIZE 0x000060 /* ### check up */
|
||||
#define CG12_DPU_SIZE 0x000080
|
||||
#define CG12_APU_SIZE 0x000100
|
||||
#define CG12_DAC_SIZE 0x000400
|
||||
#define CG12_EIC_SIZE 0x000040
|
||||
#define CG12_WSC_SIZE 0x000200
|
||||
#define CG12_WSC_ADDR_SIZE 0x000100
|
||||
#define CG12_WSC_DATA_SIZE 0x000100
|
||||
#define CG12_DRAM_SIZE 0x100000
|
||||
#define CG12_COLOR24_SIZE 0x400000
|
||||
#define CG12_COLOR8_SIZE 0x100000
|
||||
#define CG12_ZBUF_SIZE 0x200000
|
||||
#define CG12_WID_SIZE 0x100000
|
||||
#define CG12_OVERLAY_SIZE 0x020000
|
||||
#define CG12_ENABLE_SIZE 0x020000
|
||||
|
||||
#define CG12_SHMEM_SIZE 0x020000
|
||||
#define CG12_FBCTL_SIZE 0x842000
|
||||
#define CG12_PMCTL_SIZE 0x041000
|
||||
|
||||
/* DPU registers, all register offsets are relative to CG12_OFF_REGISTERS */
|
||||
#define CG12DPU_R0 0x0100
|
||||
#define CG12DPU_R1 0x0104
|
||||
#define CG12DPU_R2 0x0108
|
||||
#define CG12DPU_R3 0x010c
|
||||
#define CG12DPU_R4 0x0110
|
||||
#define CG12DPU_R5 0x0114
|
||||
#define CG12DPU_R6 0x0118
|
||||
#define CG12DPU_R7 0x011c
|
||||
#define CG12DPU_RELOAD_CTL 0x0120
|
||||
#define CG12DPU_RELOAD_STB 0x0124
|
||||
#define CG12DPU_ALU_CTL 0x0128
|
||||
#define CG12DPU_BLU_CTL 0x012c
|
||||
#define CG12DPU_CONTROL 0x0130
|
||||
#define CG12DPU_XLEFT 0x0134
|
||||
#define CG12DPU_SHIFT_0 0x0138
|
||||
#define CG12DPU_SHIFT_1 0x013c
|
||||
#define CG12DPU_ZOOM 0x0140
|
||||
#define CG12DPU_BSR 0x0144
|
||||
#define CG12DPU_COLOUR0 0x0148
|
||||
#define CG12DPU_COLOUR1 0x014c
|
||||
#define CG12DPU_COMP_OUT 0x0150
|
||||
#define CG12DPU_PLN_RDMSK_HOST 0x0154
|
||||
#define CG12DPU_PLN_WRMSK_HOST 0x0158
|
||||
#define CG12DPU_PLN_RDMSK_LOC 0x015c
|
||||
#define CG12DPU_PLN_WRMSK_LOC 0x0160
|
||||
#define CG12DPU_SCIS_CTL 0x0164
|
||||
#define CG12DPU_CSR 0x0168
|
||||
#define CG12DPU_PLN_REG_SL 0x016c
|
||||
#define CG12DPU_PLN_SL_HOST 0x0170
|
||||
#define CG12DPU_PLN_SL_LOCAL0 0x0174
|
||||
#define CG12DPU_PLN_SL_LOCAL1 0x0178
|
||||
#define CG12DPU_BROADCAST 0x017c
|
||||
|
||||
/* APU registers */
|
||||
#define CG12APU_IMSG0 0x0200
|
||||
#define CG12APU_MSG0 0x0204
|
||||
#define CG12APU_IMSG1 0x0208
|
||||
#define CG12APU_MSG1 0x020c
|
||||
#define CG12APU_IEN0 0x0210
|
||||
#define CG12APU_IEN1 0x0214
|
||||
#define CG12APU_ICLEAR 0x0218
|
||||
#define CG12APU_ISTATUS 0x021c
|
||||
#define CG12APU_CFCNT 0x0220
|
||||
#define CG12APU_CFWPTR 0x0224
|
||||
#define CG12APU_CFRPTR 0x0228
|
||||
#define CG12APU_CFILEV0 0x022c
|
||||
#define CG12APU_CFILEV1 0x0230
|
||||
#define CG12APU_RFCNT 0x0234
|
||||
#define CG12APU_RFWPTR 0x0238
|
||||
#define CG12APU_RFRPTR 0x023c
|
||||
#define CG12APU_RFILEV0 0x0240
|
||||
#define CG12APU_RFILEV1 0x0244
|
||||
#define CG12APU_SIZE 0x0248
|
||||
#define CG12APU_RES0 0x024c
|
||||
#define CG12APU_RES1 0x0250
|
||||
#define CG12APU_RES2 0x0254
|
||||
#define CG12APU_HACCESS 0x0258
|
||||
#define CG12APU_HPAGE 0x025c
|
||||
#define CG12APU_LACCESS 0x0260
|
||||
#define CG12APU_LPAGE 0x0264
|
||||
#define CG12APU_MACCESS 0x0268
|
||||
#define CG12APU_PPAGE 0x026c
|
||||
#define CG12APU_DWG_CTL 0x0270
|
||||
/*
|
||||
* The following bits are from Matrox Athena docs, they're probably not all
|
||||
* implemented or not in the same spot on the cg12. They're here strictly
|
||||
* for testing.
|
||||
*/
|
||||
#define DWGCTL_LINE_OPEN 0x00000000
|
||||
#define DWGCTL_AUTOLINE_OPEN 0x00000001
|
||||
#define DWGCTL_LINE_CLOSED 0x00000002
|
||||
#define DWGCTL_AUTOLINE_CLOSED 0x00000003
|
||||
#define DWGCTL_TRAPEXOID 0x00000004
|
||||
#define DWGCTL_BITBLT 0x00000008
|
||||
#define DWGCTL_UPLOAD 0x00000009
|
||||
#define DWGCTL_DOWNLOAD 0x0000000a
|
||||
#define DWGCTL_WRITE 0x00000000 /* write only */
|
||||
#define DWGCTL_RASTER 0x00000010 /* read/write */
|
||||
#define DWGCTL_ANTIALIAS 0x00000020
|
||||
#define DWGCTL_BLOCKMODE 0x00000040
|
||||
#define DWGCTL_LINEAR 0x00000080 /* XY otherwise */
|
||||
#define DWGCTL_ROP_MASK 0x000f0000
|
||||
#define DWGCTL_ROP_SHIFT 16
|
||||
#define DWGCTL_TRANSLUCID_MASK 0x00f00000
|
||||
#define DWGCTL_TRANSLUCID_SHIFT 20 /* selects pattern */
|
||||
#define DWGCTL_BLTMOD_MONO 0x00000000
|
||||
#define DWGCTL_BLTMOD_PLANE 0x02000000
|
||||
#define DWGCTL_BLTMOD_COLOR 0x04000000 /* clipping usable */
|
||||
#define DWGCTL_BLTMOD_UCOLOR 0x06000000 /* no clipping */
|
||||
#define DWGCTL_AFOR 0x08000000 /* set for antialias */
|
||||
#define DWGCTL_UPLOAD_RGB 0x08000000 /* BGR otherwise */
|
||||
#define DWGCTL_AA_BG 0x10000000 /* us BG color in AA */
|
||||
#define DWGCTL_UPLOAD_24BIT 0x10000000 /* 32bit otherwise */
|
||||
#define DWGCTL_EN_PATTERN 0x20000000
|
||||
#define DWGCTL_BLT_TRANSPARENT 0x40000000 /* for color exp. */
|
||||
|
||||
#define CG12APU_SAM 0x0274
|
||||
#define CG12APU_SGN 0x0278
|
||||
#define CG12APU_LENGTH 0x027c
|
||||
#define CG12APU_DWG_R0 0x0280
|
||||
#define CG12APU_DWG_R1 0x0284
|
||||
#define CG12APU_DWG_R2 0x0288
|
||||
#define CG12APU_DWG_R3 0x028c
|
||||
#define CG12APU_DWG_R4 0x0290
|
||||
#define CG12APU_DWG_R5 0x0294
|
||||
#define CG12APU_DWG_R6 0x0298
|
||||
#define CG12APU_DWG_R7 0x029c
|
||||
#define CG12APU_RELOAD_CTL 0x02a0
|
||||
#define CG12APU_RELOAD_STB 0x02a4
|
||||
#define CG12APU_C_XLEFT 0x02a8
|
||||
#define CG12APU_C_YTOP 0x02ac
|
||||
#define CG12APU_C_XRIGHT 0x02b0
|
||||
#define CG12APU_C_YBOTTOM 0x02b4
|
||||
#define CG12APU_F_XLEFT 0x02b8
|
||||
#define CG12APU_F_XRIGHT 0x02bc
|
||||
#define CG12APU_X_DST 0x02c0
|
||||
#define CG12APU_Y_DST 0x02c4
|
||||
#define CG12APU_DST_CTL 0x02c8
|
||||
#define CG12APU_MORIGIN 0x02cc
|
||||
#define CG12APU_VSG_CTL 0x02d0
|
||||
#define CG12APU_H_SYNC 0x02d4
|
||||
#define CG12APU_H_BLANK 0x02d8
|
||||
#define CG12APU_V_SYNC 0x02dc
|
||||
#define CG12APU_V_BLANK 0x02e0
|
||||
#define CG12APU_VDPYINT 0x02e4
|
||||
#define CG12APU_VSSYNCS 0x02e8
|
||||
#define CG12APU_H_DELAYS 0x02ec
|
||||
#define CG12APU_STDADDR 0x02f0
|
||||
#define CG12APU_HPITCHES 0x02f4
|
||||
#define CG12APU_ZOOM 0x02f8
|
||||
#define CG12APU_TEST 0x02fc
|
||||
|
||||
/*
|
||||
* The "direct port access" register constants.
|
||||
* All HACCESSS values include noHSTXY, noHCLIP, and SWAP.
|
||||
*/
|
||||
|
||||
#define CG12_HPAGE_OVERLAY 0x00000700 /* overlay page */
|
||||
#define CG12_HACCESS_OVERLAY 0x00000020 /* 1bit/pixel */
|
||||
#define CG12_PLN_SL_OVERLAY 0x00000017 /* plane 23 */
|
||||
#define CG12_PLN_WR_OVERLAY 0x00800000 /* write mask */
|
||||
#define CG12_PLN_RD_OVERLAY 0xffffffff /* read mask */
|
||||
|
||||
#define CG12_HPAGE_ENABLE 0x00000700 /* overlay page */
|
||||
#define CG12_HACCESS_ENABLE 0x00000020 /* 1bit/pixel */
|
||||
#define CG12_PLN_SL_ENABLE 0x00000016 /* plane 22 */
|
||||
#define CG12_PLN_WR_ENABLE 0x00400000
|
||||
#define CG12_PLN_RD_ENABLE 0xffffffff
|
||||
|
||||
#define CG12_HPAGE_24BIT 0x00000500 /* intensity page */
|
||||
#define CG12_HACCESS_24BIT 0x00000025 /* 32bits/pixel */
|
||||
#define CG12_PLN_SL_24BIT 0x00000000 /* all planes */
|
||||
#define CG12_PLN_WR_24BIT 0x00ffffff
|
||||
#define CG12_PLN_RD_24BIT 0x00ffffff
|
||||
|
||||
#define CG12_HPAGE_8BIT 0x00000500 /* intensity page */
|
||||
#define CG12_HACCESS_8BIT 0x00000023 /* 8bits/pixel */
|
||||
#define CG12_PLN_SL_8BIT 0x00000000
|
||||
#define CG12_PLN_WR_8BIT 0x00ffffff
|
||||
#define CG12_PLN_RD_8BIT 0x000000ff
|
||||
|
||||
#define CG12_HPAGE_WID 0x00000700 /* overlay page */
|
||||
#define CG12_HACCESS_WID 0x00000023 /* 8bits/pixel */
|
||||
#define CG12_PLN_SL_WID 0x00000010 /* planes 16-23 */
|
||||
#define CG12_PLN_WR_WID 0x003f0000
|
||||
#define CG12_PLN_RD_WID 0x003f0000
|
||||
|
||||
#define CG12_HPAGE_ZBUF 0x00000000 /* depth page */
|
||||
#define CG12_HACCESS_ZBUF 0x00000024 /* 16bits/pixel */
|
||||
#define CG12_PLN_SL_ZBUF 0x00000060
|
||||
#define CG12_PLN_WR_ZBUF 0xffffffff
|
||||
#define CG12_PLN_RD_ZBUF 0xffffffff
|
||||
|
||||
/* RAMDAC registers */
|
||||
#define CG12DAC_ADDR0 0x0300
|
||||
#define CG12DAC_ADDR1 0x0400
|
||||
#define CG12DAC_CTRL 0x0500
|
||||
#define CG12DAC_DATA 0x0600
|
||||
|
||||
/* WIDs */
|
||||
#define CG12_WID_8_BIT 0 /* indexed color */
|
||||
#define CG12_WID_24_BIT 1 /* true color */
|
||||
#define CG12_WID_ENABLE_2 2 /* overlay/cursor enable has 2 colors */
|
||||
#define CG12_WID_ENABLE_3 3 /* overlay/cursor enable has 3 colors */
|
||||
#define CG12_WID_ALT_CMAP 4 /* use alternate colormap */
|
||||
#define CG12_WID_DBL_BUF_DISP_A 5 /* double buffering display A */
|
||||
#define CG12_WID_DBL_BUF_DISP_B 6 /* double buffering display A */
|
||||
#define CG12_WID_ATTRS 7 /* total no of attributes */
|
||||
|
||||
/* WSC */
|
||||
#define CG12_WSC_DATA 0x0800
|
||||
#define CG12_WSC_ADDR 0x0900
|
||||
|
||||
/* EIC registers */
|
||||
#define CG12_EIC_HOST_CONTROL 0x0700
|
||||
#define CG12_EIC_CONTROL 0x0704
|
||||
#define CG12_EIC_C30_CONTROL 0x0708
|
||||
#define CG12_EIC_INTERRUPT 0x070c
|
||||
#define CG12_EIC_DCADDRW 0x0710
|
||||
#define CG12_EIC_DCBYTEW 0x0714
|
||||
#define CG12_EIC_DCSHORTW 0x0718
|
||||
#define CG12_EIC_DCLONGW 0x071c
|
||||
#define CG12_EIC_DCFLOATW 0x0720
|
||||
#define CG12_EIC_DCADDRR 0x0724
|
||||
#define CG12_EIC_DCBYTER 0x0728
|
||||
#define CG12_EIC_DCSHORTR 0x072c
|
||||
#define CG12_EIC_DCLONGR 0x0730
|
||||
#define CG12_EIC_DCFLOATR 0x0734
|
||||
#define CG12_EIC_RESET 0x073c
|
||||
|
||||
#endif /* CG12REG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue