From e6cab2e7993e9829c7c322cf6e4a42791edec637 Mon Sep 17 00:00:00 2001 From: thorpej Date: Sun, 18 Nov 2001 18:46:20 +0000 Subject: [PATCH] Add 128b/l L2 cache ops. --- sys/arch/mips/include/cache_r4k.h | 41 +++++++++++- sys/arch/mips/mips/cache.c | 16 ++++- sys/arch/mips/mips/cache_r4k.c | 104 +++++++++++++++++++++++++++++- 3 files changed, 157 insertions(+), 4 deletions(-) diff --git a/sys/arch/mips/include/cache_r4k.h b/sys/arch/mips/include/cache_r4k.h index 355f2bb77d24..51cd87d4c319 100644 --- a/sys/arch/mips/include/cache_r4k.h +++ b/sys/arch/mips/include/cache_r4k.h @@ -1,4 +1,4 @@ -/* $NetBSD: cache_r4k.h,v 1.2 2001/11/14 18:26:21 thorpej Exp $ */ +/* $NetBSD: cache_r4k.h,v 1.3 2001/11/18 18:46:20 thorpej Exp $ */ /* * Copyright 2001 Wasabi Systems, Inc. @@ -137,6 +137,38 @@ do { \ : "memory"); \ } while (/*CONSTCOND*/0) +/* + * cache_r4k_op_32lines_128: + * + * Perform the specified cache operation on 32 128-byte + * cache lines. + */ +#define cache_r4k_op_32lines_128(va, op) \ +do { \ + __asm __volatile( \ + ".set noreorder \n\t" \ + "cache %1, 0x0000(%0); cache %1, 0x0080(%0); \n\t" \ + "cache %1, 0x0100(%0); cache %1, 0x0180(%0); \n\t" \ + "cache %1, 0x0200(%0); cache %1, 0x0280(%0); \n\t" \ + "cache %1, 0x0300(%0); cache %1, 0x0380(%0); \n\t" \ + "cache %1, 0x0400(%0); cache %1, 0x0480(%0); \n\t" \ + "cache %1, 0x0500(%0); cache %1, 0x0580(%0); \n\t" \ + "cache %1, 0x0600(%0); cache %1, 0x0680(%0); \n\t" \ + "cache %1, 0x0700(%0); cache %1, 0x0780(%0); \n\t" \ + "cache %1, 0x0800(%0); cache %1, 0x0880(%0); \n\t" \ + "cache %1, 0x0900(%0); cache %1, 0x0980(%0); \n\t" \ + "cache %1, 0x0a00(%0); cache %1, 0x0a80(%0); \n\t" \ + "cache %1, 0x0b00(%0); cache %1, 0x0b80(%0); \n\t" \ + "cache %1, 0x0c00(%0); cache %1, 0x0c80(%0); \n\t" \ + "cache %1, 0x0d00(%0); cache %1, 0x0d80(%0); \n\t" \ + "cache %1, 0x0e00(%0); cache %1, 0x0e80(%0); \n\t" \ + "cache %1, 0x0f00(%0); cache %1, 0x0f80(%0); \n\t" \ + ".set reorder" \ + : \ + : "r" (va), "i" (op) \ + : "memory"); \ +} while (/*CONSTCOND*/0) + /* * cache_r4k_op_16lines_32_2way: * @@ -204,6 +236,13 @@ void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t); void r4k_sdcache_inv_range_32(vaddr_t, vsize_t); void r4k_sdcache_wb_range_32(vaddr_t, vsize_t); +void r4k_sdcache_wbinv_all_128(void); +void r4k_sdcache_wbinv_range_128(vaddr_t, vsize_t); +void r4k_sdcache_wbinv_range_index_128(vaddr_t, vsize_t); + +void r4k_sdcache_inv_range_128(vaddr_t, vsize_t); +void r4k_sdcache_wb_range_128(vaddr_t, vsize_t); + void r4k_sdcache_wbinv_all_generic(void); void r4k_sdcache_wbinv_range_generic(vaddr_t, vsize_t); void r4k_sdcache_wbinv_range_index_generic(vaddr_t, vsize_t); diff --git a/sys/arch/mips/mips/cache.c b/sys/arch/mips/mips/cache.c index 9cd036422c8f..8a7d372085d9 100644 --- a/sys/arch/mips/mips/cache.c +++ b/sys/arch/mips/mips/cache.c @@ -1,4 +1,4 @@ -/* $NetBSD: cache.c,v 1.2 2001/11/14 18:26:22 thorpej Exp $ */ +/* $NetBSD: cache.c,v 1.3 2001/11/18 18:46:20 thorpej Exp $ */ /* * Copyright 2001 Wasabi Systems, Inc. @@ -459,7 +459,6 @@ mips_config_cache(void) case 16: case 64: - case 128: mips_cache_ops.mco_sdcache_wbinv_all = r4k_sdcache_wbinv_all_generic; mips_cache_ops.mco_sdcache_wbinv_range = @@ -472,6 +471,19 @@ mips_config_cache(void) r4k_sdcache_wb_range_generic; break; + case 128: + mips_cache_ops.mco_sdcache_wbinv_all = + r4k_sdcache_wbinv_all_128; + mips_cache_ops.mco_sdcache_wbinv_range = + r4k_sdcache_wbinv_range_128; + mips_cache_ops.mco_sdcache_wbinv_range_index = + r4k_sdcache_wbinv_range_index_128; + mips_cache_ops.mco_sdcache_inv_range = + r4k_sdcache_inv_range_128; + mips_cache_ops.mco_sdcache_wb_range = + r4k_sdcache_wb_range_128; + break; + default: panic("r4k sdcache %d way line size %d\n", mips_sdcache_ways, mips_sdcache_line_size); diff --git a/sys/arch/mips/mips/cache_r4k.c b/sys/arch/mips/mips/cache_r4k.c index fb718d0188a5..68f06c000b0b 100644 --- a/sys/arch/mips/mips/cache_r4k.c +++ b/sys/arch/mips/mips/cache_r4k.c @@ -1,4 +1,4 @@ -/* $NetBSD: cache_r4k.c,v 1.2 2001/11/14 18:26:23 thorpej Exp $ */ +/* $NetBSD: cache_r4k.c,v 1.3 2001/11/18 18:46:20 thorpej Exp $ */ /* * Copyright 2001 Wasabi Systems, Inc. @@ -328,6 +328,108 @@ r4k_sdcache_wb_range_32(vaddr_t va, vsize_t size) #undef round_line #undef trunc_line +#define round_line(x) (((x) + 127) & ~127) +#define trunc_line(x) ((x) & ~127) + +void +r4k_sdcache_wbinv_all_128(void) +{ + vaddr_t va = MIPS_PHYS_TO_KSEG0(0); + vaddr_t eva = va + mips_sdcache_size; + + while (va < eva) { + cache_r4k_op_32lines_128(va, + CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV); + va += (32 * 128); + } +} + +void +r4k_sdcache_wbinv_range_128(vaddr_t va, vsize_t size) +{ + vaddr_t eva = round_line(va + size); + + va = trunc_line(va); + + while ((eva - va) >= (32 * 128)) { + cache_r4k_op_32lines_128(va, + CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV); + va += (32 * 128); + } + + while (va < eva) { + cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB_INV); + va += 128; + } +} + +void +r4k_sdcache_wbinv_range_index_128(vaddr_t va, vsize_t size) +{ + vaddr_t eva; + + /* + * Since we're doing Index ops, we expect to not be able + * to access the address we've been given. So, get the + * bits that determine the cache index, and make a KSEG0 + * address out of them. + */ + va = MIPS_PHYS_TO_KSEG0(va & (mips_sdcache_size - 1)); + + eva = round_line(va + size); + va = trunc_line(va); + + while ((eva - va) >= (32 * 128)) { + cache_r4k_op_32lines_128(va, + CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV); + va += (32 * 128); + } + + while (va < eva) { + cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_INDEX_WB_INV); + va += 128; + } +} + +void +r4k_sdcache_inv_range_128(vaddr_t va, vsize_t size) +{ + vaddr_t eva = round_line(va + size); + + va = trunc_line(va); + + while ((eva - va) >= (32 * 128)) { + cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV); + va += (32 * 128); + } + + while (va < eva) { + cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_INV); + va += 128; + } +} + +void +r4k_sdcache_wb_range_128(vaddr_t va, vsize_t size) +{ + vaddr_t eva = round_line(va + size); + + va = trunc_line(va); + + while ((eva - va) >= (32 * 128)) { + cache_r4k_op_32lines_128(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB); + va += (32 * 128); + } + + while (va < eva) { + cache_op_r4k_line(va, CACHE_R4K_SD|CACHEOP_R4K_HIT_WB); + va += 128; + } +} + +#undef round_line +#undef trunc_line + #define round_line(x) (((x) + mips_sdcache_line_size - 1) & ~(mips_sdcache_line_size - 1)) #define trunc_line(x) ((x) & ~(mips_sdcache_line_size - 1))