diff --git a/sys/arch/sh3/conf/files.sh3 b/sys/arch/sh3/conf/files.sh3 index a6ffdc2a2bb0..b773bb3415cb 100644 --- a/sys/arch/sh3/conf/files.sh3 +++ b/sys/arch/sh3/conf/files.sh3 @@ -1,4 +1,4 @@ -# $NetBSD: files.sh3,v 1.14 2001/11/20 14:34:22 lukem Exp $ +# $NetBSD: files.sh3,v 1.15 2002/02/11 18:03:05 uch Exp $ # # new style config file for sh3 architecture # @@ -23,6 +23,9 @@ file arch/sh3/sh3/sh3_machdep.c file arch/sh3/sh3/sys_machdep.c file arch/sh3/sh3/trap.c file arch/sh3/sh3/vm_machdep.c +file arch/sh3/sh3/cache.c +file arch/sh3/sh3/cache_sh3.c +file arch/sh3/sh3/cache_sh4.c file dev/clock_subr.c file dev/cninit.c file dev/cons.c diff --git a/sys/arch/sh3/include/cache.h b/sys/arch/sh3/include/cache.h new file mode 100644 index 000000000000..2c3dd6dfc5f3 --- /dev/null +++ b/sys/arch/sh3/include/cache.h @@ -0,0 +1,179 @@ +/* $NetBSD: cache.h,v 1.1 2002/02/11 18:03:05 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Cache configurations. + * + * SH3 I/D unified virtual-index physical-tag cache. + * SH4 I/D separated virtual-index physical-tag cache. + * + * + * size line-size entry way + * SH7708 4/8K 16B 128 2/4 P0, P2, U0 write-through/back selectable + * P1 write-through + * SH7709 4/8K 16B 128 2/4 write-through/back selectable + * SH7709A 16K 16B 256 4 write-through/back selectable + * + * SH7750 I$ D$ line-size entry way + * 8K 8/16K 32B 256 1 write-through/back selectable + * + * + * Cache operations. + * + * There are some rules that must be followed: + * + * I-cache Synch (all or range): + * The goal is to synchronize the instruction stream, + * so you may need to write-back dirty data cache + * blocks first. If a range is requested, and you + * can't synchronize just a range, you have to hit + * the whole thing. + * + * D-cache Write-back Invalidate range: + * If you can't WB-Inv a range, you must WB-Inv the + * entire D-cache. + * + * D-cache Invalidate: + * If you can't Inv the D-cache without doing a + * Write-back, YOU MUST PANIC. This is to catch + * errors in calling code. Callers must be aware + * of this scenario, and must handle it appropriately + * (consider the bus_dma(9) operations). + * + * D-cache Write-back: + * If you can't Write-back without doing an invalidate, + * that's fine. Then treat this as a WB-Inv. Skipping + * the invalidate is merely an optimization. + * + * All operations: + * Valid virtual addresses must be passed to the + * cache operation. + * + * + * sh_icache_sync_all Synchronize I-cache + * + * sh_icache_sync_range Synchronize I-cache range + * + * sh_icache_sync_range_index (index ops) + * + * sh_dcache_wbinv_all Write-back Invalidate D-cache + * + * sh_dcache_wbinv_range Write-back Invalidate D-cache range + * + * sh_dcache_wbinv_range_index (index ops) + * + * sh_dcache_inv_range Invalidate D-cache range + * + * sh_dcache_wb_range Write-back D-cache range + * + * If I/D unified cache (SH3), I-cache ops are writeback invalidate + * operation. + * If write-through mode, sh_dcache_wb_range is no-operation. + * + */ + +#ifndef _SH3_CACHE_H_ +#define _SH3_CACHE_H_ + +#ifdef _KERNEL +#define COMPAT_OLD_CACHE_FLUSH //XXX +#ifdef COMPAT_OLD_CACHE_FLUSH +#define cacheflush() sh_dcache_wbinv_all() +#endif /* COMPAT_OLD_CACHE_FLUSH */ + +struct sh_cache_ops { + void (*_icache_sync_all)(void); + void (*_icache_sync_range)(vaddr_t, vsize_t); + void (*_icache_sync_range_index)(vaddr_t, vsize_t); + + void (*_dcache_wbinv_all)(void); + void (*_dcache_wbinv_range)(vaddr_t, vsize_t); + void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t); + void (*_dcache_inv_range)(vaddr_t, vsize_t); + void (*_dcache_wb_range)(vaddr_t, vsize_t); +}; + +/* Cache configurations */ +#define sh_cache_enable_unified sh_cache_enable_icache +extern int sh_cache_enable_icache; +extern int sh_cache_enable_dcache; +extern int sh_cache_write_through; +extern int sh_cache_write_through_p0_u0_p3; +extern int sh_cache_write_through_p1; +extern int sh_cache_ways; +extern int sh_cache_unified; +#define sh_cache_size_unified sh_cache_size_icache +extern int sh_cache_size_icache; +extern int sh_cache_size_dcache; +extern int sh_cache_line_size; +/* Special mode */ +extern int sh_cache_ram_mode; +extern int sh_cache_index_mode_icache; +extern int sh_cache_index_mode_dcache; + +extern struct sh_cache_ops sh_cache_ops; + +#define sh_icache_sync_all() \ + (*sh_cache_ops._icache_sync_all)() + +#define sh_icache_sync_range(v, s) \ + (*sh_cache_ops._icache_sync_range)((v), (s)) + +#define sh_icache_sync_range_index(v, s) \ + (*sh_cache_ops._icache_sync_range_index)((v), (s)) + +#define sh_dcache_wbinv_all() \ + (*sh_cache_ops._dcache_wbinv_all)() + +#define sh_dcache_wbinv_range(v, s) \ + (*sh_cache_ops._dcache_wbinv_range)((v), (s)) + +#define sh_dcache_wbinv_range_index(v, s) \ + (*sh_cache_ops._dcache_wbinv_range_index)((v), (s)) + +#define sh_dcache_inv_range(v, s) \ + (*sh_cache_ops._dcache_inv_range)((v), (s)) + +#define sh_dcache_wb_range(v, s) \ + (*sh_cache_ops._dcache_wb_range)((v), (s)) + +void sh_cache_config(int); +void sh_cache_information(void); + +#endif /* _KERNEL */ +#endif /* _SH3_CACHE_H_ */ diff --git a/sys/arch/sh3/include/cache_sh3.h b/sys/arch/sh3/include/cache_sh3.h new file mode 100644 index 000000000000..30fded995dc7 --- /dev/null +++ b/sys/arch/sh3/include/cache_sh3.h @@ -0,0 +1,157 @@ +/* $NetBSD: cache_sh3.h,v 1.1 2002/02/11 18:03:05 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A + */ +#ifndef _CACHE_SH3_H_ +#define _CACHE_SH3_H_ +#ifdef _KERNEL + +#define SH3REG_CCR 0xffffffec +#define SH3_CCR_CE 0x00000001 +#define SH3_CCR_WT 0x00000002 +/* SH7708 don't have CB bit */ +#define SH3_CCR_CB 0x00000004 +#define SH3_CCR_CF 0x00000008 +/* SH7709A don't have RA bit */ +#define SH3_CCR_RA 0x00000020 + +/* SH7709A specific cache-lock control register */ +#define SH7709A_CCR2 0xa40000b0 +#define SH7709A_CCR2_W2LOCK 0x00000001 +#define SH7709A_CCR2_W2LOAD 0x00000002 +#define SH7709A_CCR2_W3LOCK 0x00000100 +#define SH7709A_CCR2_W3LOAD 0x00000200 + +#define SH3REG_CCA 0xf0000000 +/* Address specification */ +#define CCA_A 0x00000008 +#define CCA_ENTRY_SHIFT 4 +/* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */ +#define CCA_8K_ENTRY 128 +#define CCA_8K_ENTRY_MASK 0x000007f0 /* [10:4] */ +#define CCA_8K_WAY_SHIFT 11 +#define CCA_8K_WAY_MASK 0x00001800 /* [12:11] */ +/* 16KB cache (SH7709A) */ +#define CCA_16K_ENTRY 256 +#define CCA_16K_ENTRY_MASK 0x00000ff0 /* [11:4] */ +#define CCA_16K_WAY_SHIFT 12 +#define CCA_16K_WAY_MASK 0x00003000 /* [13:12] */ + +/* Data specification */ +#define CCA_U 0x00000001 +#define CCA_V 0x00000002 +#define CCA_LRU_SHIFT 4 +#define CCA_LRU_MASK 0x000003f0 /* [9:4] */ +#define CCA_TAGADDR_SHIFT 10 +#define CCA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ + +#define SH3REG_CCD 0xf1000000 +/* Address specification */ +#define CCD_L_SHIFT 2 +#define CCD_L_MASK 0x0000000c /* [3:2] */ +#define CCD_E_SHIFT 4 +#define CCD_8K_E_MASK 0x000007f0 /* [10:4] */ +#define CCD_16K_E_MASK 0x00000ff0 /* [11:4] */ +#define CCD_8K_W_SHIFT 11 +#define CCD_8K_W_MASK 0x00001800 /* [12:11] */ +#define CCD_16K_W_SHIFT 12 +#define CCD_16K_W_MASK 0x00003000 /* [13:12] */ +/* Data specification */ + +/* + * Configuration + */ +#define SH3_CACHE_LINESZ 16 +#define SH3_CACHE_NORMAL_WAY 4 +#define SH3_CACHE_RAMMODE_WAY 2 + +#define SH3_CACHE_8K_ENTRY 128 +#define SH3_CACHE_8K_WAY_NORMAL 4 +#define SH3_CACHE_8K_WAY_RAMMODE 2 + +#define SH3_CACHE_16K_ENTRY 256 +#define SH3_CACHE_16K_WAY 4 + +/* + * cache flush macro for locore level code. + */ +#define SH3_CACHE_8K_FLUSH(maxway) \ +do { \ + u_int32_t __e, __w, __wa, __a; \ + \ + for (__w = 0; __w < maxway; __w++) { \ + __wa = SH3REG_CCA | __w << CCA_8K_WAY_SHIFT; \ + for (__e = 0; __e < CCA_8K_ENTRY; __e++) { \ + __a = __wa |(__e << CCA_ENTRY_SHIFT); \ + (*(__volatile__ u_int32_t *)__a) &= \ + ~(CCA_U | CCA_V); \ + } \ + } \ +} while (/*CONSTCOND*/0) + +#define SH3_CACHE_16K_FLUSH() \ +do { \ + u_int32_t __e, __w, __wa, __a; \ + \ + for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) { \ + __wa = SH3REG_CCA | __w << CCA_16K_WAY_SHIFT; \ + for (__e = 0; __e < CCA_16K_ENTRY; __e++) { \ + __a = __wa |(__e << CCA_ENTRY_SHIFT); \ + (*(__volatile__ u_int32_t *)__a) &= \ + ~(CCA_U | CCA_V); \ + } \ + } \ +} while (/*CONSTCOND*/0) + +#define SH7708_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) +#define SH7708_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) +#define SH7708S_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) +#define SH7708S_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) +#define SH7708R_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) +#define SH7708R_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) +#define SH7709_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4) +#define SH7709_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2) +#define SH7709A_CACHE_FLUSH() SH3_CACHE_16K_FLUSH() + +#ifndef _LOCORE +extern void sh3_cache_config(int); +#endif +#endif _KERNEL +#endif /* _CACHE_SH3_H_ */ diff --git a/sys/arch/sh3/include/cache_sh4.h b/sys/arch/sh3/include/cache_sh4.h new file mode 100644 index 000000000000..abd208244a8e --- /dev/null +++ b/sys/arch/sh3/include/cache_sh4.h @@ -0,0 +1,125 @@ +/* $NetBSD: cache_sh4.h,v 1.1 2002/02/11 18:03:05 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * SH4: SH7750 SH7750S + */ + +#ifndef _CACHE_SH4_H_ +#define _CACHE_SH4_H_ +#ifdef _KERNEL + +#define SH4_ICACHE_SIZE 8192 +#define SH4_DCACHE_SIZE 16384 +#define SH4_CACHE_LINESZ 32 + +#define SH4REG_CCR 0xff00001c +#define SH4_CCR_IIX 0x00008000 +#define SH4_CCR_ICI 0x00000800 +#define SH4_CCR_ICE 0x00000100 +#define SH4_CCR_OIX 0x00000080 +#define SH4_CCR_ORA 0x00000020 +#define SH4_CCR_OCI 0x00000008 +#define SH4_CCR_CB 0x00000004 +#define SH4_CCR_WT 0x00000002 +#define SH4_CCR_OCE 0x00000001 + +#define SH4REG_QACR0 0xff000038 +#define SH4REG_QACR1 0xff00003c +#define SH4_QACR_AREA_SHIFT 2 +#define SH4_QACR_AREA_MASK 0x0000001c + +/* I-cache address/data array */ +#define SH4REG_CCIA 0xf0000000 +/* address specification */ +#define CCIA_A 0x00000008 /* associate bit */ +#define CCIA_ENTRY_SHIFT 5 /* line size 32B */ +#define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ +/* data specification */ +#define CCIA_V 0x00000001 +#define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ + +#define SH4REG_CCID 0xf1000000 +/* address specification */ +#define CCID_L_SHIFT 2 +#define CCID_L_MASK 0x1c /* line-size is 32B */ +#define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ + +/* D-cache address/data array */ +#define SH4REG_CCDA 0xf4000000 +/* address specification */ +#define CCDA_A 0x00000008 /* associate bit */ +#define CCDA_ENTRY_SHIFT 5 /* line size 32B */ +#define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ +/* data specification */ +#define CCDA_V 0x00000001 +#define CCDA_U 0x00000002 +#define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ + +#define SH4REG_CCDD 0xf5000000 + +/* Store Queue */ +#define SH4REG_SQ 0xe0000000 + +/* + * cache flush macro for locore level code. + */ +#define SH4_CACHE_FLUSH() \ +do { \ + u_int32_t __e, __a; \ + \ + /* D-cache */ \ + for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ + __a = SH4REG_CCDA | (__e << CCDA_ENTRY_SHIFT); \ + (*(__volatile__ u_int32_t *)__a) &= ~(CCDA_U | CCDA_V); \ + } \ + /* I-cache */ \ + for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ + __a = SH4REG_CCIA | (__e << CCIA_ENTRY_SHIFT); \ + (*(__volatile__ u_int32_t *)__a) &= ~(CCIA_V); \ + } \ +} while(/*CONSTCOND*/0) + +#define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() +#define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() + +#ifndef _LOCORE +extern void sh4_cache_config(int); +#endif +#endif /* _KERNEL */ +#endif /* _CACHE_SH4_H_ */ diff --git a/sys/arch/sh3/include/cpufunc.h b/sys/arch/sh3/include/cpufunc.h index 301cbec33b97..d32ee7be353c 100644 --- a/sys/arch/sh3/include/cpufunc.h +++ b/sys/arch/sh3/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.h,v 1.8 2002/02/08 06:11:16 uch Exp $ */ +/* $NetBSD: cpufunc.h,v 1.9 2002/02/11 18:03:05 uch Exp $ */ /* * Copyright (c) 1993 Charles Hannum. @@ -48,6 +48,11 @@ #include #ifdef _KERNEL + +void enable_ext_intr(void); +void disable_ext_intr(void); +static __inline void breakpoint(void); + /* * memory-mapped register access method. */ @@ -71,17 +76,9 @@ _wb_flush(); \ } -void enable_ext_intr __P((void)); -void disable_ext_intr __P((void)); -static __inline void setPageDir __P((int)); -static __inline void cache_clear __P((int)); -static __inline void breakpoint __P((void)); - static __inline void tlbflush(void) { -/* #define CACHE_FLUSH 0x80 */ - #ifdef SH4 SHREG_MMUCR = (SHREG_MMUCR | MMUCR_TF) & MMUCR_VALIDBITS; __asm __volatile("nop"); @@ -95,48 +92,8 @@ tlbflush(void) #else SHREG_MMUCR |= MMUCR_TF; #endif - -/* SHREG_CCR |= CACHE_FLUSH; */ } -static __inline void -cacheflush(void) -{ -#if 1 - volatile int *p = (int *)ram_start; - int i; - int d; - - for(i = 0; i < 512; i++){ - d = *p; - p += 8; - } -#else -#define CACHE_FLUSH 0x809 - - SHREG_CCR |= CACHE_FLUSH; - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); - __asm __volatile("nop"); -#endif -} - -static __inline void -setPageDir(pagedir) - int pagedir; -{ - - PageDirReg = pagedir; - tlbflush(); -#ifdef SH4 - SHREG_TTB = pagedir; -#endif -} /* XXXX ought to be in psl.h with spl() functions */ @@ -173,21 +130,11 @@ enable_intr(void) __asm __volatile("mov.l @r15+, r0"); } -static __inline void -cache_clear(va) - int va; -{ -#ifdef SH4 - __asm __volatile("ocbp @%0" :: "r"(va)); -#endif -} - static __inline void breakpoint() { __asm __volatile ("trapa #0xc3"); } -#endif - +#endif /* _KERNEL */ #endif /* !_SH3_CPUFUNC_H_ */ diff --git a/sys/arch/sh3/sh3/cache.c b/sys/arch/sh3/sh3/cache.c new file mode 100644 index 000000000000..5a179d3b6383 --- /dev/null +++ b/sys/arch/sh3/sh3/cache.c @@ -0,0 +1,196 @@ +/* $NetBSD: cache.c,v 1.1 2002/02/11 18:03:06 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +/* + * XXX __cache_flush is used before sh_cache_config() is called. + */ +static void __cache_flush(void); +struct sh_cache_ops sh_cache_ops = { + ._icache_sync_all = (void (*)(void))__cache_flush, + ._icache_sync_range = (void (*)(vaddr_t, vsize_t))__cache_flush, + ._icache_sync_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush, + ._dcache_wbinv_all = (void (*)(void))__cache_flush, + ._dcache_wbinv_range = (void (*)(vaddr_t, vsize_t))__cache_flush, + ._dcache_wbinv_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush, + ._dcache_inv_range = (void (*)(vaddr_t, vsize_t))__cache_flush, + ._dcache_wb_range = (void (*)(vaddr_t, vsize_t))__cache_flush +}; + +int sh_cache_enable_icache; +int sh_cache_enable_dcache; +int sh_cache_write_through; +int sh_cache_write_through_p0_u0_p3; +int sh_cache_write_through_p1; +int sh_cache_unified; +int sh_cache_ways; +int sh_cache_size_icache; +int sh_cache_size_dcache; +int sh_cache_line_size; +int sh_cache_ram_mode; +int sh_cache_index_mode_icache; +int sh_cache_index_mode_dcache; + +void +sh_cache_config(int cpu_id) +{ + +#ifdef CACHE_DEBUG + printf("*** USE DEBUG CACHE FLUSH CODE ***\n"); + return; +#endif + +#if 1 /* XXX No cpu identify method. temporary. */ +#ifdef SH4 + sh4_cache_config(cpu_id); +#else + sh3_cache_config(cpu_id); +#endif +#endif /* temporary */ + +#if notyet + switch (cpu_id) { +#ifdef CPU_SH3 + case CPU_PRODUCT_SH7708: + case CPU_PRODUCT_SH7708S: + case CPU_PRODUCT_SH7708R: + case CPU_PRODUCT_SH7709: + case CPU_PRODUCT_SH7709A: + sh3_cache_config(); + break; +#endif /* CPU_SH3 */ +#ifdef CPU_SH4 + case CPU_PRODUCT_SH7750: + case CPU_PRODUCT_SH7750S: + sh4_cache_config(); + break; +#endif /* CPU_SH4 */ + default: + panic("sh_cache_config: no cache flush operation."); + break; + } +#endif + +} + +void +sh_cache_information() +{ +#ifdef CACHE_DEBUG + printf("No cache information.\n"); + return; +#endif + /* I-cache or I/D-unified cache */ + printf("%dKB/%dB ", sh_cache_size_icache >> 10, sh_cache_line_size); + if (sh_cache_ways > 1) + printf("%d-way set-associative ", sh_cache_ways); + else + printf("direct-mapped "); + if (sh_cache_unified) + printf("I/D-unified "); + else + printf("Instruction "); + printf("cache. "); + if (!sh_cache_enable_icache) + printf("DISABLED "); + if (sh_cache_unified && sh_cache_ram_mode) + printf("RAM-mode "); + if (sh_cache_index_mode_icache) + printf("INDEX-mode "); + printf("\n"); + + /* D-cache */ + if (!sh_cache_unified) { + printf("%dKB/%dB ", sh_cache_size_dcache >> 10, + sh_cache_line_size); + if (sh_cache_ways > 1) + printf("%d-way set-associative ", sh_cache_ways); + else + printf("direct-mapped "); + printf("Data cache. "); + if (!sh_cache_enable_dcache) + printf("DISABLED "); + if (sh_cache_ram_mode) + printf("RAM-mode "); + if (sh_cache_index_mode_dcache) + printf("INDEX-mode "); + printf("\n"); + } + + /* Write-through/back */ + printf("P0, U0, P3 write-%s P1 write-%s\n", + sh_cache_write_through_p0_u0_p3 ? "through" : "back", + sh_cache_write_through_p1 ? "through" : "back"); +} + +/* + * CPU-independent cache flush. + */ +void +__cache_flush() +{ + __volatile__ int *p = (int *)ram_start; + int i; + int d; + + /* Flush D-Cache */ + /* + * Access address range [13:4]. + * max: + * 16KB line-size 16B 4-way ... [11:4] * 4 + * 16KB line-size 32B 1-way ... [13:5] + */ + for(i = 0; i < 256/*entry*/ * 4/*way*/; i++) { + d = *p; + p += 4; /* next line index (16B) */ + } + + /* Flush I-Cache */ + /* + * this code flush I-cache. but can't compile.. + * __asm__ __volatile__(".space 8192"); + * + */ +} + diff --git a/sys/arch/sh3/sh3/cache_sh3.c b/sys/arch/sh3/sh3/cache_sh3.c new file mode 100644 index 000000000000..dec9ac2340d7 --- /dev/null +++ b/sys/arch/sh3/sh3/cache_sh3.c @@ -0,0 +1,236 @@ +/* $NetBSD: cache_sh3.c,v 1.1 2002/02/11 18:03:06 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#define round_line(x) (((x) + 15) & ~15) +#define trunc_line(x) ((x) & ~15) + +void sh3_cache_wbinv_all(void); +void sh3_cache_wbinv_range(vaddr_t, vsize_t); +void sh3_cache_wbinv_range_index(vaddr_t, vsize_t); +void sh3_cache_panic(vaddr_t, vsize_t); +void sh3_cache_nop(vaddr_t, vsize_t); + +int sh_cache_way_size; +int sh_cache_way_shift; +int sh_cache_entry_mask; + +static __inline__ void cache_sh3_op_line_16_nway(int, vaddr_t, u_int32_t); +static __inline__ void cache_sh3_op_8lines_16_nway(int, vaddr_t, u_int32_t); + +void +sh3_cache_config(int cpu_id) +{ + u_int32_t r; + size_t cache_size; +#if notyet + cache_size = cpu_id == CPU_PRODUCT_SH7709A ? (16 * 1024) : (8 * 1024); +#else +#ifdef SH7709A + cache_size = 16 * 1024; +#else + cache_size = 8 * 1024; +#endif +#endif /* notyet */ + r = _reg_read_4(SH3REG_CCR); + + sh_cache_unified = 1; + sh_cache_enable_unified = (r & SH3_CCR_CE); + sh_cache_line_size = 16; + sh_cache_write_through_p0_u0_p3 = r & SH3_CCR_WT; + sh_cache_write_through_p1 = !(r & SH3_CCR_CB); + sh_cache_write_through = sh_cache_write_through_p0_u0_p3 && + sh_cache_write_through_p1; + + sh_cache_ram_mode = r & SH3_CCR_RA; + if (sh_cache_ram_mode) { + /* + * In RAM-mode, way 2 and 3 are used as RAM. + */ + sh_cache_ways = 2; + sh_cache_size_unified = cache_size / 2; + } else { + sh_cache_ways = 4; + sh_cache_size_unified = cache_size; + } + + /* size enough to access foreach entries */ + sh_cache_way_size = sh_cache_size_unified / 4/*way*/; + /* mask for extracting entry select */ + sh_cache_entry_mask = (sh_cache_way_size - 1) & ~15/*line-mask*/; + /* shift for way selection (16KB/8KB) */ + sh_cache_way_shift = + /* entry bits */ + ffs(sh_cache_size_unified / (4/*way*/ * 16/*line-size*/)) - 1 + /* line bits */ + + 4; + + sh_cache_ops._icache_sync_all = sh3_cache_wbinv_all; + sh_cache_ops._icache_sync_range = sh3_cache_wbinv_range; + sh_cache_ops._icache_sync_range_index = sh3_cache_wbinv_range_index; + sh_cache_ops._dcache_wbinv_all = sh3_cache_wbinv_all; + sh_cache_ops._dcache_wbinv_range = sh3_cache_wbinv_range; + sh_cache_ops._dcache_wbinv_range_index = sh3_cache_wbinv_range_index; + /* SH3 can't invalidate without write-back */ + sh_cache_ops._dcache_inv_range = sh3_cache_panic; + if (sh_cache_write_through) { + sh_cache_ops._dcache_wb_range = sh3_cache_nop; + } else { + /* SH3 can't write-back without invalidate */ + sh_cache_ops._dcache_wb_range = sh3_cache_wbinv_range; + } +} + +/* + * cache_sh3_op_line_16_nway: (index-operation) + * + * Clear the specified bits on single 16-byte cache line. n-ways. + * + */ +void +cache_sh3_op_line_16_nway(int n, vaddr_t va, u_int32_t bits) +{ + vaddr_t cca; + int way; + + /* extract entry # */ + va &= sh_cache_entry_mask; + + /* operate for each way */ + for (way = 0; way < n; way++) { + cca = (SH3REG_CCA | way << sh_cache_way_shift | va); + _reg_write_4(cca, _reg_read_4(cca) & ~bits); + } +} + +/* + * cache_sh3_op_8lines_16_nway: (index-operation) + * + * Clear the specified bits on 8 16-byte cache lines, n-ways. + * + */ +void +cache_sh3_op_8lines_16_nway(int n, vaddr_t va, u_int32_t bits) +{ + __volatile__ u_int32_t *cca; + int way; + + /* extract entry # */ + va &= sh_cache_entry_mask; + + /* operate for each way */ + for (way = 0; way < n; way++) { + cca = (__volatile__ u_int32_t *) + (SH3REG_CCA | way << sh_cache_way_shift | va); + cca[ 0] &= ~bits; + cca[ 4] &= ~bits; + cca[ 8] &= ~bits; + cca[12] &= ~bits; + cca[16] &= ~bits; + cca[20] &= ~bits; + cca[24] &= ~bits; + cca[28] &= ~bits; + } +} + +void +sh3_cache_wbinv_all() +{ + vaddr_t va; + + for (va = 0; va < sh_cache_way_size; va += 16 * 8) + cache_sh3_op_8lines_16_nway(sh_cache_ways, va, CCA_U | CCA_V); +} + +void +sh3_cache_wbinv_range_index(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + + va = trunc_line(va); + + while ((eva - va) >= (8 * 16)) { + cache_sh3_op_8lines_16_nway(sh_cache_ways, va, CCA_U | CCA_V); + va += 16 * 8; + } + + while (va < eva) { + cache_sh3_op_line_16_nway(sh_cache_ways, va, CCA_U | CCA_V); + va += 16; + } +} + +void +sh3_cache_wbinv_range(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + vaddr_t cca; + + va = trunc_line(va); + + while (va < eva) { + cca = SH3REG_CCA | CCA_A | (va & sh_cache_entry_mask); + /* + * extract virtual tag-address. + * MMU translates it to physical address tag, + * and write to address-array. + * implicitly specified U = 0, V = 0. + */ + _reg_write_4(cca, va & CCA_TAGADDR_MASK); + va += 16; + } +} + +void +sh3_cache_panic(vaddr_t va, vsize_t size) +{ + + panic("SH3 can't invalidate without write-back"); +} + +void +sh3_cache_nop(vaddr_t va, vsize_t sz) +{ + /* NO-OP */ +} diff --git a/sys/arch/sh3/sh3/cache_sh4.c b/sys/arch/sh3/sh3/cache_sh4.c new file mode 100644 index 000000000000..14516d81b7cc --- /dev/null +++ b/sys/arch/sh3/sh3/cache_sh4.c @@ -0,0 +1,263 @@ +/* $NetBSD: cache_sh4.c,v 1.1 2002/02/11 18:03:06 uch Exp $ */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by UCHIYAMA Yasushi. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#define round_line(x) (((x) + 31) & ~31) +#define trunc_line(x) ((x) & ~31) + +void sh4_icache_sync_all(void); +void sh4_icache_sync_range(vaddr_t, vsize_t); +void sh4_icache_sync_range_index(vaddr_t, vsize_t); +void sh4_dcache_wbinv_all(void); +void sh4_dcache_wbinv_range(vaddr_t, vsize_t); +void sh4_dcache_wbinv_range_index(vaddr_t, vsize_t); +void sh4_dcache_inv_range(vaddr_t, vsize_t); +void sh4_dcache_wb_range(vaddr_t, vsize_t); + +/* must be inlined. */ +extern __inline__ void cache_sh4_op_line_32(vaddr_t, vaddr_t, u_int32_t, + u_int32_t); +extern __inline__ void cache_sh4_op_8lines_32(vaddr_t, vaddr_t, u_int32_t, + u_int32_t); + +void +sh4_cache_config(int cpu_id) +{ + u_int32_t r; + + r = _reg_read_4(SH4REG_CCR); + + sh_cache_unified = 0; + sh_cache_enable_icache = (r & SH4_CCR_ICE); + sh_cache_enable_dcache = (r & SH4_CCR_OCE); + sh_cache_ways = 1; + sh_cache_line_size = 32; + sh_cache_write_through_p0_u0_p3 = (r & SH4_CCR_WT); + sh_cache_write_through_p1 = !(r & SH4_CCR_CB); + sh_cache_write_through = sh_cache_write_through_p0_u0_p3 && + sh_cache_write_through_p1; + sh_cache_ram_mode = (r & SH4_CCR_ORA); + sh_cache_index_mode_icache = (r & SH4_CCR_IIX); + sh_cache_index_mode_dcache = (r & SH4_CCR_OIX); + + sh_cache_size_dcache = SH4_DCACHE_SIZE; + if (sh_cache_ram_mode) + sh_cache_size_dcache /= 2; + sh_cache_size_icache = SH4_ICACHE_SIZE; + + sh_cache_ops._icache_sync_all = sh4_icache_sync_all; + sh_cache_ops._icache_sync_range = sh4_icache_sync_range; + sh_cache_ops._icache_sync_range_index = sh4_icache_sync_range_index; + + sh_cache_ops._dcache_wbinv_all = sh4_dcache_wbinv_all; + sh_cache_ops._dcache_wbinv_range = sh4_dcache_wbinv_range; + sh_cache_ops._dcache_wbinv_range_index = sh4_dcache_wbinv_range_index; + sh_cache_ops._dcache_inv_range = sh4_dcache_inv_range; + sh_cache_ops._dcache_wb_range = sh4_dcache_wb_range; +} + +/* + * cache_sh4_op_line_16: (index-operation) + * + * Clear the specified bits on single 32-byte cache line. + * + */ +void +cache_sh4_op_line_32(vaddr_t va, vaddr_t base, u_int32_t mask, u_int32_t bits) +{ + vaddr_t cca; + + cca = base | (va & mask); + _reg_write_4(cca, _reg_read_4(cca) & ~bits); +} + +/* + * cache_sh4_op_8lines_16_nway: (index-operation) + * + * Clear the specified bits on 8 32-byte cache lines. + * + */ +void +cache_sh4_op_8lines_32(vaddr_t va, vaddr_t base, u_int32_t mask, u_int32_t bits) +{ + __volatile__ u_int32_t *cca = (__volatile__ u_int32_t *) + (base | (va & mask)); + + cca[ 0] &= ~bits; + cca[ 8] &= ~bits; + cca[16] &= ~bits; + cca[24] &= ~bits; + cca[32] &= ~bits; + cca[40] &= ~bits; + cca[48] &= ~bits; + cca[56] &= ~bits; +} + +void +sh4_icache_sync_all() +{ + vaddr_t va = 0; + vaddr_t eva = SH4_ICACHE_SIZE; + + sh4_dcache_wbinv_all(); + + RUN_P2; + while (va < eva) { + cache_sh4_op_8lines_32(va, SH4REG_CCIA, CCIA_ENTRY_MASK, CCIA_V); + va += 32 * 8; + } + RUN_P1; +} + +void +sh4_icache_sync_range(vaddr_t va, vsize_t sz) +{ + vaddr_t ccia; + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + sh4_dcache_wbinv_range_index(va, (eva - va)); + + RUN_P2; + while (va < eva) { + /* CCR.IIX has no effect on this entry specification */ + ccia = SH4REG_CCIA | CCIA_A | (va & CCIA_ENTRY_MASK); + _reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */ + va += 32; + } + RUN_P1; +} + +void +sh4_icache_sync_range_index(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + sh4_dcache_wbinv_range_index(va, eva - va); + + RUN_P2; + while ((eva - va) >= (8 * 32)) { + cache_sh4_op_8lines_32(va, SH4REG_CCIA, CCIA_ENTRY_MASK, CCIA_V); + va += 32 * 8; + } + + while (va < eva) { + cache_sh4_op_line_32(va, SH4REG_CCIA, CCIA_ENTRY_MASK, CCIA_V); + va += 32; + } + RUN_P1; +} + +void +sh4_dcache_wbinv_all() +{ + vaddr_t va = 0; + vaddr_t eva = SH4_DCACHE_SIZE; + + RUN_P2; + while (va < eva) { + cache_sh4_op_8lines_32(va, SH4REG_CCDA, CCDA_ENTRY_MASK, + (CCDA_U | CCDA_V)); + va += 32 * 8; + } + RUN_P1; +} + +void +sh4_dcache_wbinv_range(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + while (va < eva) { + __asm__ __volatile__("ocbp @%0" : : "r"(va)); + va += 32; + } +} + +void +sh4_dcache_wbinv_range_index(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + RUN_P2; + while ((eva - va) >= (8 * 32)) { + cache_sh4_op_8lines_32(va, SH4REG_CCDA, CCDA_ENTRY_MASK, + (CCDA_U | CCDA_V)); + va += 32 * 8; + } + + while (va < eva) { + cache_sh4_op_line_32(va, SH4REG_CCDA, CCDA_ENTRY_MASK, + (CCDA_U | CCDA_V)); + va += 32; + } + RUN_P1; +} + +void +sh4_dcache_inv_range(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + while (va < eva) { + __asm__ __volatile__("ocbi @%0" : : "r"(va)); + va += 32; + } +} + +void +sh4_dcache_wb_range(vaddr_t va, vsize_t sz) +{ + vaddr_t eva = round_line(va + sz); + va = trunc_line(va); + + while (va < eva) { + __asm__ __volatile__("ocbwb @%0" : : "r"(va)); + va += 32; + } +} diff --git a/sys/arch/sh3/sh3/sh3_machdep.c b/sys/arch/sh3/sh3/sh3_machdep.c index 48cacb2a1c1f..ac18483ed313 100644 --- a/sys/arch/sh3/sh3/sh3_machdep.c +++ b/sys/arch/sh3/sh3/sh3_machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: sh3_machdep.c,v 1.21 2002/02/03 22:28:09 thorpej Exp $ */ +/* $NetBSD: sh3_machdep.c,v 1.22 2002/02/11 18:03:06 uch Exp $ */ /*- * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. @@ -97,6 +97,8 @@ #include +#include + char cpu_model[120]; /* @@ -125,6 +127,8 @@ sh3_startup() struct pcb *pcb; char pbuf[9]; + sh_cache_config(0); /* XXX should call more early stage. */ + printf(version); sprintf(cpu_model, "Hitachi SH3"); @@ -206,6 +210,11 @@ sh3_startup() format_bytes(pbuf, sizeof(pbuf), bufpages * NBPG); printf("using %d buffers containing %s of memory\n", nbuf, pbuf); + /* + * Print cache configuration. + */ + sh_cache_information(); + /* * Set up buffers, so they can be used to read disk labels. */