Clean up deleted files.
This commit is contained in:
mycroft
parent
fe9e2f3d60
commit
e62d58d280
|
|
@ -1,263 +0,0 @@
|
|||
/* $Id: a.out.gnu.h,v 1.2 1993/08/02 17:26:41 mycroft Exp $ */
|
||||
|
||||
#ifndef __A_OUT_GNU_H__
|
||||
#define __A_OUT_GNU_H__
|
||||
|
||||
#define __GNU_EXEC_MACROS__
|
||||
|
||||
#ifndef __STRUCT_EXEC_OVERRIDE__
|
||||
|
||||
struct exec
|
||||
{
|
||||
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
|
||||
unsigned a_text; /* length of text, in bytes */
|
||||
unsigned a_data; /* length of data, in bytes */
|
||||
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
|
||||
unsigned a_syms; /* length of symbol table data in file, in bytes */
|
||||
unsigned a_entry; /* start address */
|
||||
unsigned a_trsize; /* length of relocation info for text, in bytes */
|
||||
unsigned a_drsize; /* length of relocation info for data, in bytes */
|
||||
};
|
||||
|
||||
#endif /* __STRUCT_EXEC_OVERRIDE__ */
|
||||
|
||||
/* these go in the N_MACHTYPE field */
|
||||
enum machine_type {
|
||||
#if defined (M_OLDSUN2)
|
||||
M__OLDSUN2 = M_OLDSUN2,
|
||||
#else
|
||||
M_OLDSUN2 = 0,
|
||||
#endif
|
||||
#if defined (M_68010)
|
||||
M__68010 = M_68010,
|
||||
#else
|
||||
M_68010 = 1,
|
||||
#endif
|
||||
#if defined (M_68020)
|
||||
M__68020 = M_68020,
|
||||
#else
|
||||
M_68020 = 2,
|
||||
#endif
|
||||
#if defined (M_SPARC)
|
||||
M__SPARC = M_SPARC,
|
||||
#else
|
||||
M_SPARC = 3,
|
||||
#endif
|
||||
/* skip a bunch so we don't run into any of sun's numbers */
|
||||
M_386 = 100,
|
||||
};
|
||||
|
||||
#if !defined (N_MAGIC)
|
||||
#define N_MAGIC(exec) ((exec).a_info & 0xffff)
|
||||
#endif
|
||||
#define N_MACHTYPE(exec) ((enum machine_type)(((exec).a_info >> 16) & 0xff))
|
||||
#define N_FLAGS(exec) (((exec).a_info >> 24) & 0xff)
|
||||
#define N_SET_INFO(exec, magic, type, flags) \
|
||||
((exec).a_info = ((magic) & 0xffff) \
|
||||
| (((int)(type) & 0xff) << 16) \
|
||||
| (((flags) & 0xff) << 24))
|
||||
#define N_SET_MAGIC(exec, magic) \
|
||||
((exec).a_info = (((exec).a_info & 0xffff0000) | ((magic) & 0xffff)))
|
||||
|
||||
#define N_SET_MACHTYPE(exec, machtype) \
|
||||
((exec).a_info = \
|
||||
((exec).a_info&0xff00ffff) | ((((int)(machtype))&0xff) << 16))
|
||||
|
||||
#define N_SET_FLAGS(exec, flags) \
|
||||
((exec).a_info = \
|
||||
((exec).a_info&0x00ffffff) | (((flags) & 0xff) << 24))
|
||||
|
||||
/* Code indicating object file or impure executable. */
|
||||
#define OMAGIC 0407
|
||||
/* Code indicating pure executable. */
|
||||
#define NMAGIC 0410
|
||||
/* Code indicating demand-paged executable. */
|
||||
#define ZMAGIC 0413
|
||||
|
||||
#if !defined (N_BADMAG)
|
||||
#define N_BADMAG(x) \
|
||||
(N_MAGIC(x) != OMAGIC && N_MAGIC(x) != NMAGIC \
|
||||
&& N_MAGIC(x) != ZMAGIC)
|
||||
#endif
|
||||
|
||||
#define _N_BADMAG(x) \
|
||||
(N_MAGIC(x) != OMAGIC && N_MAGIC(x) != NMAGIC \
|
||||
&& N_MAGIC(x) != ZMAGIC)
|
||||
|
||||
#define _N_HDROFF(x) (1024 - sizeof (struct exec))
|
||||
|
||||
#if !defined (N_TXTOFF)
|
||||
#define N_TXTOFF(x) \
|
||||
(N_MAGIC(x) == ZMAGIC ? _N_HDROFF((x)) + sizeof (struct exec) : sizeof (struct exec))
|
||||
#endif
|
||||
|
||||
#if !defined (N_DATOFF)
|
||||
#define N_DATOFF(x) (N_TXTOFF(x) + (x).a_text)
|
||||
#endif
|
||||
|
||||
#if !defined (N_TRELOFF)
|
||||
#define N_TRELOFF(x) (N_DATOFF(x) + (x).a_data)
|
||||
#endif
|
||||
|
||||
#if !defined (N_DRELOFF)
|
||||
#define N_DRELOFF(x) (N_TRELOFF(x) + (x).a_trsize)
|
||||
#endif
|
||||
|
||||
#if !defined (N_SYMOFF)
|
||||
#define N_SYMOFF(x) (N_DRELOFF(x) + (x).a_drsize)
|
||||
#endif
|
||||
|
||||
#if !defined (N_STROFF)
|
||||
#define N_STROFF(x) (N_SYMOFF(x) + (x).a_syms)
|
||||
#endif
|
||||
|
||||
/* Address of text segment in memory after it is loaded. */
|
||||
#if !defined (N_TXTADDR)
|
||||
#define N_TXTADDR(x) 0
|
||||
#endif
|
||||
|
||||
/* Address of data segment in memory after it is loaded.
|
||||
Note that it is up to you to define SEGMENT_SIZE
|
||||
on machines not listed here. */
|
||||
#if defined(vax) || defined(hp300) || defined(pyr)
|
||||
#define SEGMENT_SIZE page_size
|
||||
#endif
|
||||
#ifdef sony
|
||||
#define SEGMENT_SIZE 0x2000
|
||||
#endif /* Sony. */
|
||||
#ifdef is68k
|
||||
#define SEGMENT_SIZE 0x20000
|
||||
#endif
|
||||
#if defined(m68k) && defined(PORTAR)
|
||||
#define PAGE_SIZE 0x400
|
||||
#define SEGMENT_SIZE PAGE_SIZE
|
||||
#endif
|
||||
|
||||
#define _N_SEGMENT_ROUND(x) (((x) + SEGMENT_SIZE - 1) & ~(SEGMENT_SIZE - 1))
|
||||
|
||||
#define _N_TXTENDADDR(x) (N_TXTADDR(x)+(x).a_text)
|
||||
|
||||
#ifndef N_DATADDR
|
||||
#define N_DATADDR(x) \
|
||||
(N_MAGIC(x)==OMAGIC? (_N_TXTENDADDR(x)) \
|
||||
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
|
||||
#endif
|
||||
|
||||
/* Address of bss segment in memory after it is loaded. */
|
||||
#if !defined (N_BSSADDR)
|
||||
#define N_BSSADDR(x) (N_DATADDR(x) + (x).a_data)
|
||||
#endif
|
||||
|
||||
#if !defined (N_NLIST_DECLARED)
|
||||
struct nlist {
|
||||
union {
|
||||
char *n_name;
|
||||
struct nlist *n_next;
|
||||
long n_strx;
|
||||
} n_un;
|
||||
unsigned char n_type;
|
||||
char n_other;
|
||||
short n_desc;
|
||||
unsigned long n_value;
|
||||
};
|
||||
#endif /* no N_NLIST_DECLARED. */
|
||||
|
||||
#if !defined (N_UNDF)
|
||||
#define N_UNDF 0
|
||||
#endif
|
||||
#if !defined (N_ABS)
|
||||
#define N_ABS 2
|
||||
#endif
|
||||
#if !defined (N_TEXT)
|
||||
#define N_TEXT 4
|
||||
#endif
|
||||
#if !defined (N_DATA)
|
||||
#define N_DATA 6
|
||||
#endif
|
||||
#if !defined (N_BSS)
|
||||
#define N_BSS 8
|
||||
#endif
|
||||
#if !defined (N_FN)
|
||||
#define N_FN 15
|
||||
#endif
|
||||
|
||||
#if !defined (N_EXT)
|
||||
#define N_EXT 1
|
||||
#endif
|
||||
#if !defined (N_TYPE)
|
||||
#define N_TYPE 036
|
||||
#endif
|
||||
#if !defined (N_STAB)
|
||||
#define N_STAB 0340
|
||||
#endif
|
||||
|
||||
/* The following type indicates the definition of a symbol as being
|
||||
an indirect reference to another symbol. The other symbol
|
||||
appears as an undefined reference, immediately following this symbol.
|
||||
|
||||
Indirection is asymmetrical. The other symbol's value will be used
|
||||
to satisfy requests for the indirect symbol, but not vice versa.
|
||||
If the other symbol does not have a definition, libraries will
|
||||
be searched to find a definition. */
|
||||
#define N_INDR 0xa
|
||||
|
||||
/* The following symbols refer to set elements.
|
||||
All the N_SET[ATDB] symbols with the same name form one set.
|
||||
Space is allocated for the set in the text section, and each set
|
||||
element's value is stored into one word of the space.
|
||||
The first word of the space is the length of the set (number of elements).
|
||||
|
||||
The address of the set is made into an N_SETV symbol
|
||||
whose name is the same as the name of the set.
|
||||
This symbol acts like a N_DATA global symbol
|
||||
in that it can satisfy undefined external references. */
|
||||
|
||||
/* These appear as input to LD, in a .o file. */
|
||||
#define N_SETA 0x14 /* Absolute set element symbol */
|
||||
#define N_SETT 0x16 /* Text set element symbol */
|
||||
#define N_SETD 0x18 /* Data set element symbol */
|
||||
#define N_SETB 0x1A /* Bss set element symbol */
|
||||
|
||||
/* This is output from LD. */
|
||||
#define N_SETV 0x1C /* Pointer to set vector in data area. */
|
||||
|
||||
#if !defined (N_RELOCATION_INFO_DECLARED)
|
||||
/* This structure describes a single relocation to be performed.
|
||||
The text-relocation section of the file is a vector of these structures,
|
||||
all of which apply to the text section.
|
||||
Likewise, the data-relocation section applies to the data section. */
|
||||
|
||||
struct relocation_info
|
||||
{
|
||||
/* Address (within segment) to be relocated. */
|
||||
int r_address;
|
||||
/* The meaning of r_symbolnum depends on r_extern. */
|
||||
unsigned int r_symbolnum:24;
|
||||
/* Nonzero means value is a pc-relative offset
|
||||
and it should be relocated for changes in its own address
|
||||
as well as for changes in the symbol or section specified. */
|
||||
unsigned int r_pcrel:1;
|
||||
/* Length (as exponent of 2) of the field to be relocated.
|
||||
Thus, a value of 2 indicates 1<<2 bytes. */
|
||||
unsigned int r_length:2;
|
||||
/* 1 => relocate with value of symbol.
|
||||
r_symbolnum is the index of the symbol
|
||||
in file's the symbol table.
|
||||
0 => relocate with the address of a segment.
|
||||
r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS
|
||||
(the N_EXT bit may be set also, but signifies nothing). */
|
||||
unsigned int r_extern:1;
|
||||
/* Four bits that aren't used, but when writing an object file
|
||||
it is desirable to clear them. */
|
||||
#ifdef NS32K
|
||||
unsigned r_bsr:1;
|
||||
unsigned r_disp:1;
|
||||
unsigned r_pad:2;
|
||||
#else
|
||||
unsigned int r_pad:4;
|
||||
#endif
|
||||
};
|
||||
#endif /* no N_RELOCATION_INFO_DECLARED. */
|
||||
|
||||
|
||||
#endif /* __A_OUT_GNU_H__ */
|
||||
|
|
@ -1,815 +0,0 @@
|
|||
/*-
|
||||
* This code is derived from software copyrighted by the Free Software
|
||||
* Foundation.
|
||||
*
|
||||
* Modified 1991 by Donn Seeley at UUNET Technologies, Inc.
|
||||
*
|
||||
* from: @(#)i386-opcode.h 6.3 (Berkeley) 5/8/91
|
||||
* $Id: i386-opcode.h,v 1.4 1993/09/24 17:19:16 jtc Exp $
|
||||
*/
|
||||
|
||||
/* i386-opcode.h -- Intel 80386 opcode table
|
||||
Copyright (C) 1989, Free Software Foundation.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 1, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
template i386_optab[] = {
|
||||
|
||||
#define _ None
|
||||
/* move instructions */
|
||||
{ "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 },
|
||||
{ "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 },
|
||||
{ "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 },
|
||||
{ "mov", 2, 0xc6, _, W|Modrm, Imm, Reg|Mem, 0 },
|
||||
{ "mov", 2, 0x8c, _, D|Modrm, SReg3|SReg2, Reg16|Mem16, 0 },
|
||||
/* move to/from control debug registers */
|
||||
{ "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0},
|
||||
{ "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0},
|
||||
{ "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0},
|
||||
|
||||
/* move with sign extend */
|
||||
/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
|
||||
conflict with the "movs" string move instruction. Thus,
|
||||
{"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
|
||||
is not kosher; we must seperate the two instructions. */
|
||||
{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg32, 0},
|
||||
{"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16, 0},
|
||||
{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
|
||||
|
||||
/* move with zero extend */
|
||||
{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
|
||||
{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},
|
||||
|
||||
/* push instructions */
|
||||
{"push", 1, 0x50, _, ShortForm, WordReg,0,0 },
|
||||
{"push", 1, 0xff, 0x6, Modrm, WordReg|WordMem, 0, 0 },
|
||||
{"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0},
|
||||
{"push", 1, 0x68, _, NoModrm, Imm16|Imm32, 0, 0},
|
||||
{"push", 1, 0x06, _, Seg2ShortForm, SReg2,0,0 },
|
||||
{"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 },
|
||||
/* push all */
|
||||
{"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 },
|
||||
|
||||
/* pop instructions */
|
||||
{"pop", 1, 0x58, _, ShortForm, WordReg,0,0 },
|
||||
{"pop", 1, 0x8f, 0x0, Modrm, WordReg|WordMem, 0, 0 },
|
||||
#define POP_SEG_SHORT 0x7
|
||||
{"pop", 1, 0x07, _, Seg2ShortForm, SReg2,0,0 },
|
||||
{"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 },
|
||||
/* pop all */
|
||||
{"popa", 0, 0x61, _, NoModrm, 0, 0, 0 },
|
||||
|
||||
/* xchg exchange instructions
|
||||
xchg commutes: we allow both operand orders */
|
||||
{"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 },
|
||||
{"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 },
|
||||
{"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 },
|
||||
{"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 },
|
||||
|
||||
/* in/out from ports */
|
||||
{"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 },
|
||||
{"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 },
|
||||
{"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 },
|
||||
{"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 },
|
||||
|
||||
/* load effective address */
|
||||
{"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 },
|
||||
|
||||
/* load segment registers from memory */
|
||||
{"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0},
|
||||
{"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0},
|
||||
{"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0},
|
||||
{"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0},
|
||||
{"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0},
|
||||
|
||||
/* flags register instructions */
|
||||
{"clc", 0, 0xf8, _, NoModrm, 0, 0, 0},
|
||||
{"cld", 0, 0xfc, _, NoModrm, 0, 0, 0},
|
||||
{"cli", 0, 0xfa, _, NoModrm, 0, 0, 0},
|
||||
{"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0},
|
||||
{"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0},
|
||||
{"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0},
|
||||
{"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0},
|
||||
{"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0},
|
||||
{"popf", 0, 0x9d, _, NoModrm, 0, 0, 0},
|
||||
{"stc", 0, 0xf9, _, NoModrm, 0, 0, 0},
|
||||
{"std", 0, 0xfd, _, NoModrm, 0, 0, 0},
|
||||
{"sti", 0, 0xfb, _, NoModrm, 0, 0, 0},
|
||||
|
||||
{"add", 2, 0x0, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"add", 2, 0x83, 0, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"add", 2, 0x4, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0},
|
||||
{"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"sub", 2, 0x28, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"sub", 2, 0x83, 5, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"sub", 2, 0x2c, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"sub", 2, 0x80, 5, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0},
|
||||
{"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"sbb", 2, 0x18, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"sbb", 2, 0x83, 3, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"sbb", 2, 0x1c, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"sbb", 2, 0x80, 3, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"cmp", 2, 0x38, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"cmp", 2, 0x83, 7, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"cmp", 2, 0x3c, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"cmp", 2, 0x80, 7, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0},
|
||||
{"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0},
|
||||
{"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"and", 2, 0x20, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"and", 2, 0x83, 4, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"and", 2, 0x24, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"and", 2, 0x80, 4, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"or", 2, 0x08, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"or", 2, 0x83, 1, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"or", 2, 0x0c, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"or", 2, 0x80, 1, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"xor", 2, 0x30, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"xor", 2, 0x83, 6, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"xor", 2, 0x34, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"xor", 2, 0x80, 6, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"adc", 2, 0x10, _, DW|Modrm, Reg, Reg|Mem, 0},
|
||||
{"adc", 2, 0x83, 2, Modrm, Imm8S, WordReg|WordMem, 0},
|
||||
{"adc", 2, 0x14, _, W|NoModrm, Imm, Acc, 0},
|
||||
{"adc", 2, 0x80, 2, W|Modrm, Imm, Reg|Mem, 0},
|
||||
|
||||
{"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0},
|
||||
{"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"aaa", 0, 0x37, _, NoModrm, 0, 0, 0},
|
||||
{"aas", 0, 0x3f, _, NoModrm, 0, 0, 0},
|
||||
{"daa", 0, 0x27, _, NoModrm, 0, 0, 0},
|
||||
{"das", 0, 0x2f, _, NoModrm, 0, 0, 0},
|
||||
{"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0},
|
||||
{"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* conversion insns */
|
||||
/* conversion: intel naming */
|
||||
{"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0},
|
||||
{"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0},
|
||||
{"cwde", 0, 0x98, _, NoModrm, 0, 0, 0},
|
||||
{"cdq", 0, 0x99, _, NoModrm, 0, 0, 0},
|
||||
/* att naming */
|
||||
{"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0},
|
||||
{"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0},
|
||||
{"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0},
|
||||
{"cltd", 0, 0x99, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
|
||||
expanding 64-bit multiplies, and *cannot* be selected to accomplish
|
||||
'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
|
||||
These multiplies can only be selected with single opearnd forms. */
|
||||
{"mul", 1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0},
|
||||
{"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
|
||||
|
||||
|
||||
/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
|
||||
These instructions are exceptions: 'imul $2, %eax, %ecx' would put
|
||||
'%eax' in the reg field and '%ecx' in the regmem field if we did not
|
||||
switch them. */
|
||||
{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
|
||||
{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg},
|
||||
{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg},
|
||||
/*
|
||||
imul with 2 operands mimicks imul with 3 by puting register both
|
||||
in i.rm.reg & i.rm.regmem fields
|
||||
*/
|
||||
{"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0},
|
||||
{"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0},
|
||||
{"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0},
|
||||
{"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0},
|
||||
{"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0},
|
||||
{"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0},
|
||||
|
||||
{"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
|
||||
{"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem},
|
||||
{"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
|
||||
|
||||
{"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
{"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem},
|
||||
{"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem},
|
||||
|
||||
{"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0},
|
||||
{"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0},
|
||||
{"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0},
|
||||
{"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0},
|
||||
|
||||
/* control transfer instructions */
|
||||
#define CALL_PC_RELATIVE 0xe8
|
||||
{"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0},
|
||||
{"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0},
|
||||
#define CALL_FAR_IMMEDIATE 0x9a
|
||||
{"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Imm32, 0},
|
||||
{"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0},
|
||||
|
||||
#define JUMP_PC_RELATIVE 0xeb
|
||||
{"jmp", 1, 0xeb, _, Jump, Disp, 0, 0},
|
||||
{"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0},
|
||||
#define JUMP_FAR_IMMEDIATE 0xea
|
||||
{"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0},
|
||||
{"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0},
|
||||
|
||||
{"ret", 0, 0xc3, _, NoModrm, 0, 0, 0},
|
||||
{"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0},
|
||||
{"lret", 0, 0xcb, _, NoModrm, 0, 0, 0},
|
||||
{"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0},
|
||||
{"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0},
|
||||
{"leave", 0, 0xc9, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* conditional jumps */
|
||||
{"jo", 1, 0x70, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jno", 1, 0x71, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jb", 1, 0x72, _, Jump, Disp, 0, 0},
|
||||
{"jc", 1, 0x72, _, Jump, Disp, 0, 0},
|
||||
{"jnae", 1, 0x72, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jnb", 1, 0x73, _, Jump, Disp, 0, 0},
|
||||
{"jnc", 1, 0x73, _, Jump, Disp, 0, 0},
|
||||
{"jae", 1, 0x73, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"je", 1, 0x74, _, Jump, Disp, 0, 0},
|
||||
{"jz", 1, 0x74, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jne", 1, 0x75, _, Jump, Disp, 0, 0},
|
||||
{"jnz", 1, 0x75, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jbe", 1, 0x76, _, Jump, Disp, 0, 0},
|
||||
{"jna", 1, 0x76, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jnbe", 1, 0x77, _, Jump, Disp, 0, 0},
|
||||
{"ja", 1, 0x77, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"js", 1, 0x78, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jns", 1, 0x79, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jp", 1, 0x7a, _, Jump, Disp, 0, 0},
|
||||
{"jpe", 1, 0x7a, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jnp", 1, 0x7b, _, Jump, Disp, 0, 0},
|
||||
{"jpo", 1, 0x7b, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jl", 1, 0x7c, _, Jump, Disp, 0, 0},
|
||||
{"jnge", 1, 0x7c, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jnl", 1, 0x7d, _, Jump, Disp, 0, 0},
|
||||
{"jge", 1, 0x7d, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jle", 1, 0x7e, _, Jump, Disp, 0, 0},
|
||||
{"jng", 1, 0x7e, _, Jump, Disp, 0, 0},
|
||||
|
||||
{"jnle", 1, 0x7f, _, Jump, Disp, 0, 0},
|
||||
{"jg", 1, 0x7f, _, Jump, Disp, 0, 0},
|
||||
|
||||
/* these turn into pseudo operations when disp is larger than 8 bits */
|
||||
#define IS_JUMP_ON_CX_ZERO(o) \
|
||||
(o == 0x67e3)
|
||||
#define IS_JUMP_ON_ECX_ZERO(o) \
|
||||
(o == 0xe3)
|
||||
|
||||
{"jcxz", 1, 0x67e3, _, JumpByte, Disp, 0, 0},
|
||||
{"jecxz", 1, 0xe3, _, JumpByte, Disp, 0, 0},
|
||||
|
||||
#define IS_LOOP_ECX_TIMES(o) \
|
||||
(o == 0xe2 || o == 0xe1 || o == 0xe0)
|
||||
|
||||
{"loop", 1, 0xe2, _, JumpByte, Disp, 0, 0},
|
||||
|
||||
{"loopz", 1, 0xe1, _, JumpByte, Disp, 0, 0},
|
||||
{"loope", 1, 0xe1, _, JumpByte, Disp, 0, 0},
|
||||
|
||||
{"loopnz", 1, 0xe0, _, JumpByte, Disp, 0, 0},
|
||||
{"loopne", 1, 0xe0, _, JumpByte, Disp, 0, 0},
|
||||
|
||||
/* set byte on flag instructions */
|
||||
{"seto", 1, 0x0f90, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setno", 1, 0x0f91, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setb", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setnae", 1, 0x0f92, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setnb", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setae", 1, 0x0f93, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"sete", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setz", 1, 0x0f94, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setne", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setnz", 1, 0x0f95, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setbe", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setna", 1, 0x0f96, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setnbe", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"seta", 1, 0x0f97, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"sets", 1, 0x0f98, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setns", 1, 0x0f99, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setp", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setpe", 1, 0x0f9a, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setnp", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setpo", 1, 0x0f9b, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setl", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setnge", 1, 0x0f9c, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setnl", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setge", 1, 0x0f9d, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setle", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setng", 1, 0x0f9e, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
{"setnle", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
{"setg", 1, 0x0f9f, 0, Modrm, Reg8|Mem, 0, 0},
|
||||
|
||||
#define IS_STRING_INSTRUCTION(o) \
|
||||
((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
|
||||
(o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
|
||||
(o) == 0xd7)
|
||||
|
||||
/* string manipulation */
|
||||
{"cmps", 0, 0xa6, _, W|NoModrm, 0, 0, 0},
|
||||
{"ins", 0, 0x6c, _, W|NoModrm, 0, 0, 0},
|
||||
{"outs", 0, 0x6e, _, W|NoModrm, 0, 0, 0},
|
||||
{"lods", 0, 0xac, _, W|NoModrm, 0, 0, 0},
|
||||
{"movs", 0, 0xa4, _, W|NoModrm, 0, 0, 0},
|
||||
{"scas", 0, 0xae, _, W|NoModrm, 0, 0, 0},
|
||||
{"stos", 0, 0xaa, _, W|NoModrm, 0, 0, 0},
|
||||
{"xlat", 0, 0xd7, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* bit manipulation */
|
||||
{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
|
||||
{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, Reg|Mem, Reg, 0},
|
||||
{"bt", 2, 0x0fa3, _, Modrm, Reg, Reg|Mem, 0},
|
||||
{"bt", 2, 0x0fba, 4, Modrm, Imm8, Reg|Mem, 0},
|
||||
{"btc", 2, 0x0fbb, _, Modrm, Reg, Reg|Mem, 0},
|
||||
{"btc", 2, 0x0fba, 7, Modrm, Imm8, Reg|Mem, 0},
|
||||
{"btr", 2, 0x0fb3, _, Modrm, Reg, Reg|Mem, 0},
|
||||
{"btr", 2, 0x0fba, 6, Modrm, Imm8, Reg|Mem, 0},
|
||||
{"bts", 2, 0x0fab, _, Modrm, Reg, Reg|Mem, 0},
|
||||
{"bts", 2, 0x0fba, 5, Modrm, Imm8, Reg|Mem, 0},
|
||||
|
||||
/* interrupts & op. sys insns */
|
||||
/* See i386.c for conversion of 'int $3' into the special int 3 insn. */
|
||||
#define INT_OPCODE 0xcd
|
||||
#define INT3_OPCODE 0xcc
|
||||
{"int", 1, 0xcd, _, NoModrm, Imm8, 0, 0},
|
||||
{"int3", 0, 0xcc, _, NoModrm, 0, 0, 0},
|
||||
{"into", 0, 0xce, _, NoModrm, 0, 0, 0},
|
||||
{"iret", 0, 0xcf, _, NoModrm, 0, 0, 0},
|
||||
|
||||
{"boundl", 2, 0x62, _, Modrm, Reg32, Mem, 0},
|
||||
{"boundw", 2, 0x6662, _, Modrm, Reg16, Mem, 0},
|
||||
|
||||
{"hlt", 0, 0xf4, _, NoModrm, 0, 0, 0},
|
||||
{"wait", 0, 0x9b, _, NoModrm, 0, 0, 0},
|
||||
/* nop is actually 'xchgl %eax, %eax' */
|
||||
{"nop", 0, 0x90, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* protection control */
|
||||
{"arpl", 2, 0x63, _, Modrm, Reg16, Reg16|Mem, 0},
|
||||
{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
|
||||
{"lgdt", 1, 0x0f01, 2, Modrm, Mem, 0, 0},
|
||||
{"lidt", 1, 0x0f01, 3, Modrm, Mem, 0, 0},
|
||||
{"lldt", 1, 0x0f00, 2, Modrm, WordReg|Mem, 0, 0},
|
||||
{"lmsw", 1, 0x0f01, 6, Modrm, WordReg|Mem, 0, 0},
|
||||
{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
|
||||
{"ltr", 1, 0x0f00, 3, Modrm, WordReg|Mem, 0, 0},
|
||||
|
||||
{"sgdt", 1, 0x0f01, 0, Modrm, Mem, 0, 0},
|
||||
{"sidt", 1, 0x0f01, 1, Modrm, Mem, 0, 0},
|
||||
{"sldt", 1, 0x0f00, 0, Modrm, WordReg|Mem, 0, 0},
|
||||
{"smsw", 1, 0x0f01, 4, Modrm, WordReg|Mem, 0, 0},
|
||||
{"str", 1, 0x0f00, 1, Modrm, Reg16|Mem, 0, 0},
|
||||
|
||||
{"verr", 1, 0x0f00, 4, Modrm, WordReg|Mem, 0, 0},
|
||||
{"verw", 1, 0x0f00, 5, Modrm, WordReg|Mem, 0, 0},
|
||||
|
||||
/* floating point instructions */
|
||||
|
||||
/* load */
|
||||
{"fld", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"flds", 1, 0xd9, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem float */
|
||||
{"fildl", 1, 0xdb, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem word */
|
||||
{"fldl", 1, 0xdd, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem double */
|
||||
{"fldl", 1, 0xd9c0, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"filds", 1, 0xdf, 0, Modrm, Mem, 0, 0}, /* %st0 <-- mem dword */
|
||||
{"fildq", 1, 0xdf, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem qword */
|
||||
{"fldt", 1, 0xdb, 5, Modrm, Mem, 0, 0}, /* %st0 <-- mem efloat */
|
||||
{"fbld", 1, 0xdf, 4, Modrm, Mem, 0, 0}, /* %st0 <-- mem bcd */
|
||||
|
||||
/* store (no pop) */
|
||||
{"fst", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"fsts", 1, 0xd9, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
|
||||
{"fistl", 1, 0xdb, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
|
||||
{"fstl", 1, 0xdd, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
|
||||
{"fstl", 1, 0xddd0, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"fists", 1, 0xdf, 2, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
|
||||
|
||||
/* store (with pop) */
|
||||
{"fstp", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"fstps", 1, 0xd9, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem float */
|
||||
{"fistpl", 1, 0xdb, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem word */
|
||||
{"fstpl", 1, 0xdd, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem double */
|
||||
{"fstpl", 1, 0xddd8, _, ShortForm, FloatReg, 0, 0}, /* register */
|
||||
{"fistps", 1, 0xdf, 3, Modrm, Mem, 0, 0}, /* %st0 --> mem dword */
|
||||
{"fistpq", 1, 0xdf, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem qword */
|
||||
{"fstpt", 1, 0xdb, 7, Modrm, Mem, 0, 0}, /* %st0 --> mem efloat */
|
||||
{"fbstp", 1, 0xdf, 6, Modrm, Mem, 0, 0}, /* %st0 --> mem bcd */
|
||||
|
||||
/* exchange %st<n> with %st0 */
|
||||
{"fxch", 1, 0xd9c8, _, ShortForm, FloatReg, 0, 0},
|
||||
|
||||
/* comparison (without pop) */
|
||||
{"fcom", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fcoms", 1, 0xd8, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
|
||||
{"ficoml", 1, 0xda, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
|
||||
{"fcoml", 1, 0xdc, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
|
||||
{"fcoml", 1, 0xd8d0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"ficoms", 1, 0xde, 2, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
|
||||
|
||||
/* comparison (with pop) */
|
||||
{"fcomp", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fcomps", 1, 0xd8, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem float */
|
||||
{"ficompl", 1, 0xda, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem word */
|
||||
{"fcompl", 1, 0xdc, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem double */
|
||||
{"fcompl", 1, 0xd8d8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"ficomps", 1, 0xde, 3, Modrm, Mem, 0, 0}, /* compare %st0, mem dword */
|
||||
{"fcompp", 0, 0xded9, _, NoModrm, 0, 0, 0}, /* compare %st0, %st1 & pop twice */
|
||||
|
||||
/* unordered comparison (with pop) */
|
||||
{"fucom", 1, 0xdde0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fucomp", 1, 0xdde8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fucompp", 0, 0xdae9, _, NoModrm, 0, 0, 0}, /* ucompare %st0, %st1 & pop twice */
|
||||
|
||||
{"ftst", 0, 0xd9e4, _, NoModrm, 0, 0, 0}, /* test %st0 */
|
||||
{"fxam", 0, 0xd9e5, _, NoModrm, 0, 0, 0}, /* examine %st0 */
|
||||
|
||||
/* load constants into %st0 */
|
||||
{"fld1", 0, 0xd9e8, _, NoModrm, 0, 0, 0}, /* %st0 <-- 1.0 */
|
||||
{"fldl2t", 0, 0xd9e9, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(10) */
|
||||
{"fldl2e", 0, 0xd9ea, _, NoModrm, 0, 0, 0}, /* %st0 <-- log2(e) */
|
||||
{"fldpi", 0, 0xd9eb, _, NoModrm, 0, 0, 0}, /* %st0 <-- pi */
|
||||
{"fldlg2", 0, 0xd9ec, _, NoModrm, 0, 0, 0}, /* %st0 <-- log10(2) */
|
||||
{"fldln2", 0, 0xd9ed, _, NoModrm, 0, 0, 0}, /* %st0 <-- ln(2) */
|
||||
{"fldz", 0, 0xd9ee, _, NoModrm, 0, 0, 0}, /* %st0 <-- 0.0 */
|
||||
|
||||
/* arithmetic */
|
||||
|
||||
/* add */
|
||||
{"fadd", 1, 0xd8c0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
|
||||
{"fadd", 0, 0xdcc1, _, NoModrm, 0, 0, 0}, /* alias for fadd %st, %st(1) */
|
||||
{"faddp", 1, 0xdac0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"faddp", 2, 0xdac0, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
|
||||
{"faddp", 0, 0xdec1, _, NoModrm, 0, 0, 0}, /* alias for faddp %st, %st(1) */
|
||||
{"fadds", 1, 0xd8, 0, Modrm, Mem, 0, 0},
|
||||
{"fiaddl", 1, 0xda, 0, Modrm, Mem, 0, 0},
|
||||
{"faddl", 1, 0xdc, 0, Modrm, Mem, 0, 0},
|
||||
{"fiadds", 1, 0xde, 0, Modrm, Mem, 0, 0},
|
||||
|
||||
/* sub */
|
||||
/* Note: intel has decided that certain of these operations are reversed
|
||||
in assembler syntax. */
|
||||
{"fsub", 1, 0xd8e0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fsub", 2, 0xd8e0, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fsub", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fsub", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fsub", 0, 0xdce1, _, NoModrm, 0, 0, 0},
|
||||
{"fsubp", 1, 0xdae0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fsubp", 2, 0xdae0, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fsubp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fsubp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fsubp", 0, 0xdee1, _, NoModrm, 0, 0, 0},
|
||||
{"fsubs", 1, 0xd8, 4, Modrm, Mem, 0, 0},
|
||||
{"fisubl", 1, 0xda, 4, Modrm, Mem, 0, 0},
|
||||
{"fsubl", 1, 0xdc, 4, Modrm, Mem, 0, 0},
|
||||
{"fisubs", 1, 0xde, 4, Modrm, Mem, 0, 0},
|
||||
|
||||
/* sub reverse */
|
||||
{"fsubr", 1, 0xd8e8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fsubr", 2, 0xd8e8, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fsubr", 2, 0xdce0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fsubr", 2, 0xdce8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fsubr", 0, 0xdce9, _, NoModrm, 0, 0, 0},
|
||||
{"fsubrp", 1, 0xdae8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fsubrp", 2, 0xdae8, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fsubrp", 2, 0xdee0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fsubrp", 2, 0xdee8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fsubrp", 0, 0xdee9, _, NoModrm, 0, 0, 0},
|
||||
{"fsubrs", 1, 0xd8, 5, Modrm, Mem, 0, 0},
|
||||
{"fisubrl", 1, 0xda, 5, Modrm, Mem, 0, 0},
|
||||
{"fsubrl", 1, 0xdc, 5, Modrm, Mem, 0, 0},
|
||||
{"fisubrs", 1, 0xde, 5, Modrm, Mem, 0, 0},
|
||||
|
||||
/* mul */
|
||||
{"fmul", 1, 0xd8c8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
|
||||
{"fmul", 0, 0xdcc9, _, NoModrm, 0, 0, 0},
|
||||
{"fmulp", 1, 0xdac8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fmulp", 2, 0xdac8, _, ShortForm|FloatD, FloatReg, FloatAcc, 0},
|
||||
{"fmulp", 0, 0xdec9, _, NoModrm, 0, 0, 0},
|
||||
{"fmuls", 1, 0xd8, 1, Modrm, Mem, 0, 0},
|
||||
{"fimull", 1, 0xda, 1, Modrm, Mem, 0, 0},
|
||||
{"fmull", 1, 0xdc, 1, Modrm, Mem, 0, 0},
|
||||
{"fimuls", 1, 0xde, 1, Modrm, Mem, 0, 0},
|
||||
|
||||
/* div */
|
||||
/* Note: intel has decided that certain of these operations are reversed
|
||||
in assembler syntax. */
|
||||
{"fdiv", 1, 0xd8f0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0},
|
||||
{"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0},
|
||||
{"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0},
|
||||
{"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0},
|
||||
{"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0},
|
||||
{"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0},
|
||||
|
||||
/* div reverse */
|
||||
{"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0},
|
||||
{"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0},
|
||||
#ifdef NON_BROKEN_OPCODES
|
||||
{"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#else
|
||||
{"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
|
||||
#endif
|
||||
{"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0},
|
||||
{"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0},
|
||||
{"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0},
|
||||
{"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0},
|
||||
{"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0},
|
||||
|
||||
{"f2xm1", 0, 0xd9f0, _, NoModrm, 0, 0, 0},
|
||||
{"fyl2x", 0, 0xd9f1, _, NoModrm, 0, 0, 0},
|
||||
{"fptan", 0, 0xd9f2, _, NoModrm, 0, 0, 0},
|
||||
{"fpatan", 0, 0xd9f3, _, NoModrm, 0, 0, 0},
|
||||
{"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0},
|
||||
{"fprem1", 0, 0xd9f5, _, NoModrm, 0, 0, 0},
|
||||
{"fdecstp", 0, 0xd9f6, _, NoModrm, 0, 0, 0},
|
||||
{"fincstp", 0, 0xd9f7, _, NoModrm, 0, 0, 0},
|
||||
{"fprem", 0, 0xd9f8, _, NoModrm, 0, 0, 0},
|
||||
{"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0},
|
||||
{"fsqrt", 0, 0xd9fa, _, NoModrm, 0, 0, 0},
|
||||
{"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0},
|
||||
{"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0},
|
||||
{"fscale", 0, 0xd9fd, _, NoModrm, 0, 0, 0},
|
||||
{"fsin", 0, 0xd9fe, _, NoModrm, 0, 0, 0},
|
||||
{"fcos", 0, 0xd9ff, _, NoModrm, 0, 0, 0},
|
||||
|
||||
{"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0},
|
||||
{"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* processor control */
|
||||
{"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
|
||||
{"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
|
||||
{"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0},
|
||||
{"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
|
||||
{"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
|
||||
{"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
|
||||
{"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
|
||||
{"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
|
||||
{"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
|
||||
{"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
|
||||
{"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
|
||||
{"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
|
||||
{"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
|
||||
/*
|
||||
We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
|
||||
instructions; i'm not sure how to add them or how they are different.
|
||||
My 386/387 book offers no details about this.
|
||||
*/
|
||||
{"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
|
||||
{"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
|
||||
{"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0},
|
||||
{"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
|
||||
{"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
|
||||
{"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0},
|
||||
|
||||
{"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0},
|
||||
{"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0},
|
||||
{"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/*
|
||||
opcode prefixes; we allow them as seperate insns too
|
||||
(see prefix table below)
|
||||
*/
|
||||
{"aword", 0, 0x67, _, NoModrm, 0, 0, 0},
|
||||
{"word", 0, 0x66, _, NoModrm, 0, 0, 0},
|
||||
{"lock", 0, 0xf0, _, NoModrm, 0, 0, 0},
|
||||
{"cs", 0, 0x2e, _, NoModrm, 0, 0, 0},
|
||||
{"ds", 0, 0x3e, _, NoModrm, 0, 0, 0},
|
||||
{"es", 0, 0x26, _, NoModrm, 0, 0, 0},
|
||||
{"fs", 0, 0x64, _, NoModrm, 0, 0, 0},
|
||||
{"gs", 0, 0x65, _, NoModrm, 0, 0, 0},
|
||||
{"ss", 0, 0x36, _, NoModrm, 0, 0, 0},
|
||||
{"rep", 0, 0xf3, _, NoModrm, 0, 0, 0},
|
||||
{"repe", 0, 0xf3, _, NoModrm, 0, 0, 0},
|
||||
{ "repne", 0, 0xf2, _, NoModrm, 0, 0, 0},
|
||||
|
||||
/* 486 extensions */
|
||||
{"bswap", 1, 0x0fc8, _, ShortForm, Reg32,0,0 },
|
||||
{"xadd", 2, 0x0fc0, _, DW|Modrm, Reg, Reg|Mem, 0 },
|
||||
{"cmpxchg", 2, 0x0fb0, _, DW|Modrm, Reg, Reg|Mem, 0 },
|
||||
{"invd", 0, 0x0f08, _, NoModrm, 0, 0, 0},
|
||||
{"wbinvd", 0, 0x0f09, _, NoModrm, 0, 0, 0},
|
||||
{"invlpg", 1, 0x0f01, 7, Modrm, Mem, 0, 0},
|
||||
|
||||
{"", 0, 0, 0, 0, 0, 0, 0} /* sentinal */
|
||||
};
|
||||
#undef _
|
||||
|
||||
template *i386_optab_end
|
||||
= i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
|
||||
|
||||
/* 386 register table */
|
||||
|
||||
reg_entry i386_regtab[] = {
|
||||
/* 8 bit regs */
|
||||
{"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
|
||||
{"bl", Reg8, 3},
|
||||
{"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
|
||||
/* 16 bit regs */
|
||||
{"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
|
||||
{"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
|
||||
/* 32 bit regs */
|
||||
{"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
|
||||
{"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
|
||||
/* segment registers */
|
||||
{"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
|
||||
{"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
|
||||
/* control registers */
|
||||
{"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
|
||||
/* debug registers */
|
||||
{"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
|
||||
{"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
|
||||
/* test registers */
|
||||
{"tr6", Test, 6}, {"tr7", Test, 7},
|
||||
/* float registers */
|
||||
{"st(0)", FloatReg|FloatAcc, 0},
|
||||
{"st", FloatReg|FloatAcc, 0},
|
||||
{"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
|
||||
{"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
|
||||
{"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
|
||||
};
|
||||
|
||||
#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
|
||||
|
||||
reg_entry *i386_regtab_end
|
||||
= i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
|
||||
|
||||
/* segment stuff */
|
||||
seg_entry cs = { "cs", 0x2e };
|
||||
seg_entry ds = { "ds", 0x3e };
|
||||
seg_entry ss = { "ss", 0x36 };
|
||||
seg_entry es = { "es", 0x26 };
|
||||
seg_entry fs = { "fs", 0x64 };
|
||||
seg_entry gs = { "gs", 0x65 };
|
||||
seg_entry null = { "", 0x0 };
|
||||
|
||||
/*
|
||||
This table is used to store the default segment register implied by all
|
||||
possible memory addressing modes.
|
||||
It is indexed by the mode & modrm entries of the modrm byte as follows:
|
||||
index = (mode<<3) | modrm;
|
||||
*/
|
||||
seg_entry *one_byte_segment_defaults[] = {
|
||||
/* mode 0 */
|
||||
&ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
|
||||
/* mode 1 */
|
||||
&ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
|
||||
/* mode 2 */
|
||||
&ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
|
||||
/* mode 3 --- not a memory reference; never referenced */
|
||||
};
|
||||
|
||||
seg_entry *two_byte_segment_defaults[] = {
|
||||
/* mode 0 */
|
||||
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
|
||||
/* mode 1 */
|
||||
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
|
||||
/* mode 2 */
|
||||
&ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
|
||||
/* mode 3 --- not a memory reference; never referenced */
|
||||
};
|
||||
|
||||
prefix_entry i386_prefixtab[] = {
|
||||
{ "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
|
||||
* (How is this useful?) */
|
||||
#define WORD_PREFIX_OPCODE 0x66
|
||||
{ "data16", 0x66 }, /* operand size prefix */
|
||||
{ "lock", 0xf0 }, /* bus lock prefix */
|
||||
{ "wait", 0x9b }, /* wait for coprocessor */
|
||||
{ "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
|
||||
{ "es", 0x26 }, { "fs", 0x64 },
|
||||
{ "gs", 0x65 }, { "ss", 0x36 },
|
||||
/* REPE & REPNE used to detect rep/repne with a non-string instruction */
|
||||
#define REPNE 0xf2
|
||||
#define REPE 0xf3
|
||||
{ "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */
|
||||
{ "repne", 0xf2 }
|
||||
};
|
||||
|
||||
prefix_entry *i386_prefixtab_end
|
||||
= i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,299 +0,0 @@
|
|||
/* i386.h -- Header file for i386.c
|
||||
Copyright (C) 1989, Free Software Foundation.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 1, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
$Id: i386.h,v 1.2 1993/08/02 17:26:49 mycroft Exp $
|
||||
*/
|
||||
|
||||
#define MAX_OPERANDS 3 /* max operands per insn */
|
||||
#define MAX_PREFIXES 4 /* max prefixes per opcode */
|
||||
#define MAX_IMMEDIATE_OPERANDS 2 /* max immediates per insn */
|
||||
#define MAX_MEMORY_OPERANDS 2 /* max memory ref per insn
|
||||
* lcall uses 2
|
||||
*/
|
||||
/* we define the syntax here (modulo base,index,scale syntax) */
|
||||
#define REGISTER_PREFIX '%'
|
||||
#define IMMEDIATE_PREFIX '$'
|
||||
#define ABSOLUTE_PREFIX '*'
|
||||
#define PREFIX_SEPERATOR '/'
|
||||
|
||||
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
|
||||
|
||||
/* register numbers */
|
||||
#define EBP_REG_NUM 5
|
||||
#define ESP_REG_NUM 4
|
||||
|
||||
/* modrm_byte.regmem for twobyte escape */
|
||||
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
|
||||
/* index_base_byte.index for no index register addressing */
|
||||
#define NO_INDEX_REGISTER ESP_REG_NUM
|
||||
/* index_base_byte.base for no base register addressing */
|
||||
#define NO_BASE_REGISTER EBP_REG_NUM
|
||||
|
||||
/* these are the att as opcode suffixes, making movl --> mov, for example */
|
||||
#define DWORD_OPCODE_SUFFIX 'l'
|
||||
#define WORD_OPCODE_SUFFIX 'w'
|
||||
#define BYTE_OPCODE_SUFFIX 'b'
|
||||
|
||||
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
|
||||
#define REGMEM_FIELD_HAS_REG 0x3 /* always = 0x3 */
|
||||
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
|
||||
|
||||
#define END_OF_INSN '\0'
|
||||
|
||||
/*
|
||||
When an operand is read in it is classified by its type. This type includes
|
||||
all the possible ways an operand can be used. Thus, '%eax' is both 'register
|
||||
# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
|
||||
'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
|
||||
Operands are classified so that we can match given operand types with
|
||||
the opcode table in i386-opcode.h.
|
||||
*/
|
||||
#define Unknown 0x0
|
||||
/* register */
|
||||
#define Reg8 0x1 /* 8 bit reg */
|
||||
#define Reg16 0x2 /* 16 bit reg */
|
||||
#define Reg32 0x4 /* 32 bit reg */
|
||||
#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
|
||||
#define WordReg (Reg16|Reg32) /* for push/pop operands */
|
||||
/* immediate */
|
||||
#define Imm8 0x8 /* 8 bit immediate */
|
||||
#define Imm8S 0x10 /* 8 bit immediate sign extended */
|
||||
#define Imm16 0x20 /* 16 bit immediate */
|
||||
#define Imm32 0x40 /* 32 bit immediate */
|
||||
#define Imm1 0x80 /* 1 bit immediate */
|
||||
#define ImmUnknown Imm32 /* for unknown expressions */
|
||||
#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
|
||||
/* memory */
|
||||
#define Disp8 0x200 /* 8 bit displacement (for jumps) */
|
||||
#define Disp16 0x400 /* 16 bit displacement */
|
||||
#define Disp32 0x800 /* 32 bit displacement */
|
||||
#define Disp (Disp8|Disp16|Disp32) /* General displacement */
|
||||
#define DispUnknown Disp32 /* for unknown size displacements */
|
||||
#define Mem8 0x1000
|
||||
#define Mem16 0x2000
|
||||
#define Mem32 0x4000
|
||||
#define BaseIndex 0x8000
|
||||
#define Mem (Disp|Mem8|Mem16|Mem32|BaseIndex) /* General memory */
|
||||
#define WordMem (Mem16|Mem32|Disp|BaseIndex)
|
||||
#define ByteMem (Mem8|Disp|BaseIndex)
|
||||
/* specials */
|
||||
#define InOutPortReg 0x10000 /* register to hold in/out port addr = dx */
|
||||
#define ShiftCount 0x20000 /* register to hold shift cound = cl */
|
||||
#define Control 0x40000 /* Control register */
|
||||
#define Debug 0x80000 /* Debug register */
|
||||
#define Test 0x100000 /* Test register */
|
||||
#define FloatReg 0x200000 /* Float register */
|
||||
#define FloatAcc 0x400000 /* Float stack top %st(0) */
|
||||
#define SReg2 0x800000 /* 2 bit segment register */
|
||||
#define SReg3 0x1000000 /* 3 bit segment register */
|
||||
#define Acc 0x2000000 /* Accumulator %al or %ax or %eax */
|
||||
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
|
||||
#define JumpAbsolute 0x4000000
|
||||
#define Abs8 0x08000000
|
||||
#define Abs16 0x10000000
|
||||
#define Abs32 0x20000000
|
||||
#define Abs (Abs8|Abs16|Abs32)
|
||||
|
||||
#define MODE_FROM_DISP_SIZE(t) \
|
||||
((t&(Disp8)) ? 1 : \
|
||||
((t&(Disp32)) ? 2 : 0))
|
||||
|
||||
#define Byte (Reg8|Imm8|Imm8S)
|
||||
#define Word (Reg16|Imm16)
|
||||
#define DWord (Reg32|Imm32)
|
||||
|
||||
/* convert opcode suffix ('b' 'w' 'l' typically) into type specifyer */
|
||||
#define OPCODE_SUFFIX_TO_TYPE(s) \
|
||||
(s == BYTE_OPCODE_SUFFIX ? Byte : \
|
||||
(s == WORD_OPCODE_SUFFIX ? Word : DWord))
|
||||
|
||||
#define FITS_IN_SIGNED_BYTE(num) ((num) >= -128 && (num) <= 127)
|
||||
#define FITS_IN_UNSIGNED_BYTE(num) ((num) >= 0 && (num) <= 255)
|
||||
#define FITS_IN_UNSIGNED_WORD(num) ((num) >= 0 && (num) <= 65535)
|
||||
#define FITS_IN_SIGNED_WORD(num) ((num) >= -32768 && (num) <= 32767)
|
||||
|
||||
#define SMALLEST_DISP_TYPE(num) \
|
||||
FITS_IN_SIGNED_BYTE(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32)
|
||||
|
||||
#define SMALLEST_IMM_TYPE(num) \
|
||||
(num == 1) ? (Imm1|Imm8|Imm8S|Imm16|Imm32): \
|
||||
FITS_IN_SIGNED_BYTE(num) ? (Imm8S|Imm8|Imm16|Imm32) : \
|
||||
FITS_IN_UNSIGNED_BYTE(num) ? (Imm8|Imm16|Imm32): \
|
||||
(FITS_IN_SIGNED_WORD(num)||FITS_IN_UNSIGNED_WORD(num)) ? (Imm16|Imm32) : \
|
||||
(Imm32)
|
||||
|
||||
typedef unsigned char uchar;
|
||||
typedef unsigned int uint;
|
||||
|
||||
typedef struct {
|
||||
/* instruction name sans width suffix ("mov" for movl insns) */
|
||||
char *name;
|
||||
|
||||
/* how many operands */
|
||||
uint operands;
|
||||
|
||||
/* base_opcode is the fundamental opcode byte with a optional prefix(es). */
|
||||
uint base_opcode;
|
||||
|
||||
/* extension_opcode is the 3 bit extension for group <n> insns.
|
||||
If this template has no extension opcode (the usual case) use None */
|
||||
uchar extension_opcode;
|
||||
#define None 0xff /* If no extension_opcode is possible. */
|
||||
|
||||
/* the bits in opcode_modifier are used to generate the final opcode from
|
||||
the base_opcode. These bits also are used to detect alternate forms of
|
||||
the same instruction */
|
||||
uint opcode_modifier;
|
||||
|
||||
/* opcode_modifier bits: */
|
||||
#define W 0x1 /* set if operands are words or dwords */
|
||||
#define D 0x2 /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
|
||||
/* direction flag for floating insns: MUST BE 0x400 */
|
||||
#define FloatD 0x400
|
||||
/* shorthand */
|
||||
#define DW (D|W)
|
||||
#define ShortForm 0x10 /* register is in low 3 bits of opcode */
|
||||
#define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */
|
||||
#define Seg2ShortForm 0x40 /* encoding of load segment reg insns */
|
||||
#define Seg3ShortForm 0x80 /* fs/gs segment register insns. */
|
||||
#define Jump 0x100 /* special case for jump insns. */
|
||||
#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
|
||||
/* 0x400 CANNOT BE USED since it's already used by FloatD above */
|
||||
#define DONT_USE 0x400
|
||||
#define NoModrm 0x800
|
||||
#define Modrm 0x1000
|
||||
#define imulKludge 0x2000
|
||||
#define JumpByte 0x4000
|
||||
#define JumpDword 0x8000
|
||||
#define ReverseRegRegmem 0x10000
|
||||
|
||||
/* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
|
||||
instuction comes in byte, word, and dword sizes and is encoded into
|
||||
machine code in the canonical way. */
|
||||
#define COMES_IN_ALL_SIZES (W)
|
||||
|
||||
/* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
|
||||
source and destination operands can be reversed by setting either
|
||||
the D (for integer insns) or the FloatD (for floating insns) bit
|
||||
in base_opcode. */
|
||||
#define COMES_IN_BOTH_DIRECTIONS (D|FloatD)
|
||||
|
||||
/* operand_types[i] describes the type of operand i. This is made
|
||||
by OR'ing together all of the possible type masks. (e.g.
|
||||
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
||||
either a register or an immediate operand */
|
||||
uint operand_types[3];
|
||||
} template;
|
||||
|
||||
/*
|
||||
'templates' is for grouping together 'template' structures for opcodes
|
||||
of the same name. This is only used for storing the insns in the grand
|
||||
ole hash table of insns.
|
||||
The templates themselves start at START and range up to (but not including)
|
||||
END.
|
||||
*/
|
||||
typedef struct {
|
||||
template *start;
|
||||
template *end;
|
||||
} templates;
|
||||
|
||||
/* these are for register name --> number & type hash lookup */
|
||||
typedef struct {
|
||||
char * reg_name;
|
||||
uint reg_type;
|
||||
uint reg_num;
|
||||
} reg_entry;
|
||||
|
||||
typedef struct {
|
||||
char * seg_name;
|
||||
uint seg_prefix;
|
||||
} seg_entry;
|
||||
|
||||
/* these are for prefix name --> prefix code hash lookup */
|
||||
typedef struct {
|
||||
char * prefix_name;
|
||||
uchar prefix_code;
|
||||
} prefix_entry;
|
||||
|
||||
/* 386 operand encoding bytes: see 386 book for details of this. */
|
||||
typedef struct {
|
||||
unsigned regmem:3; /* codes register or memory operand */
|
||||
unsigned reg:3; /* codes register operand (or extended opcode) */
|
||||
unsigned mode:2; /* how to interpret regmem & reg */
|
||||
} modrm_byte;
|
||||
|
||||
/* 386 opcode byte to code indirect addressing. */
|
||||
typedef struct {
|
||||
unsigned base:3;
|
||||
unsigned index:3;
|
||||
unsigned scale:2;
|
||||
} base_index_byte;
|
||||
|
||||
/* 'md_assemble ()' gathers together information and puts it into a
|
||||
i386_insn. */
|
||||
|
||||
typedef struct {
|
||||
/* TM holds the template for the insn were currently assembling. */
|
||||
template tm;
|
||||
/* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */
|
||||
char suffix;
|
||||
/* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
|
||||
|
||||
/* OPERANDS gives the number of given operands. */
|
||||
uint operands;
|
||||
|
||||
/* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number of
|
||||
given register, displacement, memory operands and immediate operands. */
|
||||
uint reg_operands, disp_operands, mem_operands, imm_operands;
|
||||
|
||||
/* TYPES [i] is the type (see above #defines) which tells us how to
|
||||
search through DISPS [i] & IMMS [i] & REGS [i] for the required
|
||||
operand. */
|
||||
uint types [MAX_OPERANDS];
|
||||
|
||||
/* Displacements (if given) for each operand. */
|
||||
expressionS * disps [MAX_OPERANDS];
|
||||
|
||||
/* Immediate operands (if given) for each operand. */
|
||||
expressionS * imms [MAX_OPERANDS];
|
||||
|
||||
/* Register operands (if given) for each operand. */
|
||||
reg_entry * regs [MAX_OPERANDS];
|
||||
|
||||
/* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
|
||||
the base index byte below. */
|
||||
reg_entry * base_reg;
|
||||
reg_entry * index_reg;
|
||||
uint log2_scale_factor;
|
||||
|
||||
/* SEG gives the seg_entry of this insn. It is equal to zero unless
|
||||
an explicit segment override is given. */
|
||||
seg_entry * seg; /* segment for memory operands (if given) */
|
||||
|
||||
/* PREFIX holds all the given prefix opcodes (usually null).
|
||||
PREFIXES is the size of PREFIX. */
|
||||
char prefix [MAX_PREFIXES];
|
||||
uint prefixes;
|
||||
|
||||
/* RM and IB are the modrm byte and the base index byte where the addressing
|
||||
modes of this insn are encoded. */
|
||||
|
||||
modrm_byte rm;
|
||||
base_index_byte bi;
|
||||
} i386_insn;
|
||||
|
|
@ -1,494 +0,0 @@
|
|||
/* Table of opcodes for the i860.
|
||||
Copyright (C) 1989 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
|
||||
|
||||
GAS/GDB is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 1, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS/GDB is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS or GDB; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
$Id: i860-opcode.h,v 1.2 1993/08/02 17:26:52 mycroft Exp $
|
||||
*/
|
||||
|
||||
#if !defined(__STDC__) && !defined(const)
|
||||
#define const
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Structure of an opcode table entry.
|
||||
*/
|
||||
struct i860_opcode
|
||||
{
|
||||
const char *name;
|
||||
unsigned long int match; /* Bits that must be set. */
|
||||
unsigned long int lose; /* Bits that must not be set. */
|
||||
const char *args;
|
||||
/* Nonzero if this is a possible expand-instruction. */
|
||||
char expand;
|
||||
};
|
||||
|
||||
enum expand_type
|
||||
{
|
||||
E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
|
||||
};
|
||||
|
||||
/*
|
||||
All i860 opcodes are 32 bits, except for the pseudoinstructions
|
||||
and the operations utilizing a 32-bit address expression, an
|
||||
unsigned 32-bit constant, or a signed 32-bit constant.
|
||||
These opcodes are expanded into a two-instruction sequence for
|
||||
any situation where the immediate operand does not fit in 32 bits.
|
||||
In the case of the add and subtract operations the expansion is
|
||||
to a three-instruction sequence (ex: orh, or, adds). In cases
|
||||
where the address is to be relocated, the instruction is
|
||||
expanded to handle the worse case, this could be optimized at
|
||||
the final link if the actual address were known.
|
||||
|
||||
The pseudoinstructions are: mov, fmov, pmov, nop, and fnop.
|
||||
These instructions are implemented as a one or two instruction
|
||||
sequence of other operations.
|
||||
|
||||
The match component is a mask saying which bits must match a
|
||||
particular opcode in order for an instruction to be an instance
|
||||
of that opcode.
|
||||
|
||||
The args component is a string containing one character
|
||||
for each operand of the instruction.
|
||||
|
||||
Kinds of operands:
|
||||
# Number used by optimizer. It is ignored.
|
||||
1 src1 integer register.
|
||||
2 src2 integer register.
|
||||
d dest register.
|
||||
c ctrlreg control register.
|
||||
i 16 bit immediate.
|
||||
I 16 bit immediate, aligned.
|
||||
5 5 bit immediate.
|
||||
l lbroff 26 bit PC relative immediate.
|
||||
r sbroff 16 bit PC relative immediate.
|
||||
s split 16 bit immediate.
|
||||
S split 16 bit immediate, aligned.
|
||||
e src1 floating point register.
|
||||
f src2 floating point register.
|
||||
g dest floating point register.
|
||||
|
||||
*/
|
||||
|
||||
/* The order of the opcodes in this table is significant:
|
||||
|
||||
* The assembler requires that all instances of the same mnemonic must be
|
||||
consecutive. If they aren't, the assembler will bomb at runtime.
|
||||
|
||||
* The disassembler should not care about the order of the opcodes. */
|
||||
|
||||
static struct i860_opcode i860_opcodes[] =
|
||||
{
|
||||
|
||||
/* REG-Format Instructions */
|
||||
{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */
|
||||
{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
|
||||
{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
|
||||
{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */
|
||||
{ "ld.s", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */
|
||||
{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */
|
||||
{ "ld.l", 0x14000001, 0xe8000000, "I(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */
|
||||
|
||||
{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */
|
||||
{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */
|
||||
{ "st.s", 0x1c000000, 0xe0000000, "1,S(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */
|
||||
{ "st.l", 0x1c000001, 0xe0000000, "1,S(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */
|
||||
|
||||
{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */
|
||||
|
||||
{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */
|
||||
{ "fld.l", 0x24000002, 0xd8000001, "i(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
|
||||
{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */
|
||||
{ "fld.l", 0x24000003, 0xd8000000, "i(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
|
||||
{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */
|
||||
{ "fld.d", 0x24000000, 0xd8000007, "i(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
|
||||
{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */
|
||||
{ "fld.d", 0x24000001, 0xd8000006, "i(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
|
||||
{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */
|
||||
{ "fld.q", 0x24000004, 0xd8000003, "i(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
|
||||
{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */
|
||||
{ "fld.q", 0x24000005, 0xd8000002, "i(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
|
||||
|
||||
{ "pfld.l", 0x60000000, 0x9c000003, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */
|
||||
{ "pfld.l", 0x64000000, 0x98000003, "i(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */
|
||||
{ "pfld.l", 0x60000001, 0x9c000002, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */
|
||||
{ "pfld.l", 0x64000001, 0x98000002, "i(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */
|
||||
{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */
|
||||
{ "pfld.d", 0x64000000, 0x98000007, "i(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */
|
||||
{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */
|
||||
{ "pfld.d", 0x64000001, 0x98000006, "i(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */
|
||||
|
||||
{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */
|
||||
{ "fst.l", 0x2c000002, 0xd0000001, "g,i(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */
|
||||
{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */
|
||||
{ "fst.l", 0x2c000003, 0xd0000000, "g,i(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */
|
||||
{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
|
||||
{ "fst.d", 0x2c000000, 0xd0000007, "g,i(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
|
||||
{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
|
||||
{ "fst.d", 0x2c000001, 0xd0000006, "g,i(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
|
||||
|
||||
{ "pst.d", 0x3c000000, 0xc0000007, "g,i(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */
|
||||
{ "pst.d", 0x3c000001, 0xc0000006, "g,i(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */
|
||||
|
||||
{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */
|
||||
{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */
|
||||
{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */
|
||||
{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */
|
||||
{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */
|
||||
{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */
|
||||
{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */
|
||||
{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */
|
||||
|
||||
{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */
|
||||
{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */
|
||||
{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */
|
||||
{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */
|
||||
{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */
|
||||
{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */
|
||||
{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */
|
||||
|
||||
{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */
|
||||
{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */
|
||||
{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */
|
||||
{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */
|
||||
|
||||
{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */
|
||||
|
||||
{ "flush", 0x34000000, 0xc81f0001, "i(2)", E_ADDR }, /* flush #const(isrc2) */
|
||||
{ "flush", 0x34000001, 0xc81f0000, "i(2)++", E_ADDR }, /* flush #const(isrc2)++ */
|
||||
|
||||
{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */
|
||||
{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */
|
||||
{ "andh", 0xc8000000, 0x34000000, "1,2,d", 0 }, /* andh isrc1,isrc2,idest */
|
||||
{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */
|
||||
{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */
|
||||
{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */
|
||||
{ "andnoth", 0xd8000000, 0x24000000, "1,2,d", 0 }, /* andnoth isrc1,isrc2,idest */
|
||||
{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */
|
||||
{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */
|
||||
{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */
|
||||
{ "orh", 0xe8000000, 0x14000000, "1,2,d", 0 }, /* orh isrc1,isrc2,idest */
|
||||
{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */
|
||||
{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */
|
||||
{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */
|
||||
{ "xorh", 0xf8000000, 0x04000000, "1,2,d", 0 }, /* xorh isrc1,isrc2,idest */
|
||||
{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */
|
||||
|
||||
{ "bte", 0x58000000, 0xa4000000, "1,2,s", 0 }, /* bte isrc1s,isrc2,sbroff */
|
||||
{ "bte", 0x5c000000, 0xa0000000, "5,2,s", 0 }, /* bte #const5,isrc2,sbroff */
|
||||
{ "btne", 0x50000000, 0xac000000, "1,2,s", 0 }, /* btne isrc1s,isrc2,sbroff */
|
||||
{ "btne", 0x54000000, 0xa8000000, "5,2,s", 0 }, /* btne #const5,isrc2,sbroff */
|
||||
{ "bla", 0xb4000000, 0x48000000, "1,2,s", E_DELAY }, /* bla isrc1s,isrc2,sbroff */
|
||||
{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */
|
||||
|
||||
/* Core Escape Instruction Format */
|
||||
{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */
|
||||
{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */
|
||||
{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */
|
||||
{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */
|
||||
|
||||
/* CTRL-Format Instructions */
|
||||
{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */
|
||||
{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */
|
||||
{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */
|
||||
{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */
|
||||
{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */
|
||||
{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
|
||||
|
||||
/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */
|
||||
{ "r2p1.ss", 0x48000400, 0xb40003ff, "e,f,g", 0 },
|
||||
{ "r2p1.sd", 0x48000480, 0xb400037f, "e,f,g", 0 },
|
||||
{ "r2p1.dd", 0x48000580, 0xb400027f, "e,f,g", 0 },
|
||||
{ "r2pt.ss", 0x48000401, 0xb40003fe, "e,f,g", 0 },
|
||||
{ "r2pt.sd", 0x48000481, 0xb400037e, "e,f,g", 0 },
|
||||
{ "r2pt.dd", 0x48000581, 0xb400027e, "e,f,g", 0 },
|
||||
{ "r2ap1.ss", 0x48000402, 0xb40003fd, "e,f,g", 0 },
|
||||
{ "r2ap1.sd", 0x48000482, 0xb400037d, "e,f,g", 0 },
|
||||
{ "r2ap1.dd", 0x48000582, 0xb400027d, "e,f,g", 0 },
|
||||
{ "r2apt.ss", 0x48000403, 0xb40003fc, "e,f,g", 0 },
|
||||
{ "r2apt.sd", 0x48000483, 0xb400037c, "e,f,g", 0 },
|
||||
{ "r2apt.dd", 0x48000583, 0xb400027c, "e,f,g", 0 },
|
||||
{ "i2p1.ss", 0x48000404, 0xb40003fb, "e,f,g", 0 },
|
||||
{ "i2p1.sd", 0x48000484, 0xb400037b, "e,f,g", 0 },
|
||||
{ "i2p1.dd", 0x48000584, 0xb400027b, "e,f,g", 0 },
|
||||
{ "i2pt.ss", 0x48000405, 0xb40003fa, "e,f,g", 0 },
|
||||
{ "i2pt.sd", 0x48000485, 0xb400037a, "e,f,g", 0 },
|
||||
{ "i2pt.dd", 0x48000585, 0xb400027a, "e,f,g", 0 },
|
||||
{ "i2ap1.ss", 0x48000406, 0xb40003f9, "e,f,g", 0 },
|
||||
{ "i2ap1.sd", 0x48000486, 0xb4000379, "e,f,g", 0 },
|
||||
{ "i2ap1.dd", 0x48000586, 0xb4000279, "e,f,g", 0 },
|
||||
{ "i2apt.ss", 0x48000407, 0xb40003f8, "e,f,g", 0 },
|
||||
{ "i2apt.sd", 0x48000487, 0xb4000378, "e,f,g", 0 },
|
||||
{ "i2apt.dd", 0x48000587, 0xb4000278, "e,f,g", 0 },
|
||||
{ "rat1p2.ss", 0x48000408, 0xb40003f7, "e,f,g", 0 },
|
||||
{ "rat1p2.sd", 0x48000488, 0xb4000377, "e,f,g", 0 },
|
||||
{ "rat1p2.dd", 0x48000588, 0xb4000277, "e,f,g", 0 },
|
||||
{ "m12apm.ss", 0x48000409, 0xb40003f6, "e,f,g", 0 },
|
||||
{ "m12apm.sd", 0x48000489, 0xb4000376, "e,f,g", 0 },
|
||||
{ "m12apm.dd", 0x48000589, 0xb4000276, "e,f,g", 0 },
|
||||
{ "ra1p2.ss", 0x4800040a, 0xb40003f5, "e,f,g", 0 },
|
||||
{ "ra1p2.sd", 0x4800048a, 0xb4000375, "e,f,g", 0 },
|
||||
{ "ra1p2.dd", 0x4800058a, 0xb4000275, "e,f,g", 0 },
|
||||
{ "m12ttpa.ss", 0x4800040b, 0xb40003f4, "e,f,g", 0 },
|
||||
{ "m12ttpa.sd", 0x4800048b, 0xb4000374, "e,f,g", 0 },
|
||||
{ "m12ttpa.dd", 0x4800058b, 0xb4000274, "e,f,g", 0 },
|
||||
{ "iat1p2.ss", 0x4800040c, 0xb40003f3, "e,f,g", 0 },
|
||||
{ "iat1p2.sd", 0x4800048c, 0xb4000373, "e,f,g", 0 },
|
||||
{ "iat1p2.dd", 0x4800058c, 0xb4000273, "e,f,g", 0 },
|
||||
{ "m12tpm.ss", 0x4800040d, 0xb40003f2, "e,f,g", 0 },
|
||||
{ "m12tpm.sd", 0x4800048d, 0xb4000372, "e,f,g", 0 },
|
||||
{ "m12tpm.dd", 0x4800058d, 0xb4000272, "e,f,g", 0 },
|
||||
{ "ia1p2.ss", 0x4800040e, 0xb40003f1, "e,f,g", 0 },
|
||||
{ "ia1p2.sd", 0x4800048e, 0xb4000371, "e,f,g", 0 },
|
||||
{ "ia1p2.dd", 0x4800058e, 0xb4000271, "e,f,g", 0 },
|
||||
{ "m12tpa.ss", 0x4800040f, 0xb40003f0, "e,f,g", 0 },
|
||||
{ "m12tpa.sd", 0x4800048f, 0xb4000370, "e,f,g", 0 },
|
||||
{ "m12tpa.dd", 0x4800058f, 0xb4000270, "e,f,g", 0 },
|
||||
|
||||
/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */
|
||||
{ "r2s1.ss", 0x48000410, 0xb40003ef, "e,f,g", 0 },
|
||||
{ "r2s1.sd", 0x48000490, 0xb400036f, "e,f,g", 0 },
|
||||
{ "r2s1.dd", 0x48000590, 0xb400026f, "e,f,g", 0 },
|
||||
{ "r2st.ss", 0x48000411, 0xb40003ee, "e,f,g", 0 },
|
||||
{ "r2st.sd", 0x48000491, 0xb400036e, "e,f,g", 0 },
|
||||
{ "r2st.dd", 0x48000591, 0xb400026e, "e,f,g", 0 },
|
||||
{ "r2as1.ss", 0x48000412, 0xb40003ed, "e,f,g", 0 },
|
||||
{ "r2as1.sd", 0x48000492, 0xb400036d, "e,f,g", 0 },
|
||||
{ "r2as1.dd", 0x48000592, 0xb400026d, "e,f,g", 0 },
|
||||
{ "r2ast.ss", 0x48000413, 0xb40003ec, "e,f,g", 0 },
|
||||
{ "r2ast.sd", 0x48000493, 0xb400036c, "e,f,g", 0 },
|
||||
{ "r2ast.dd", 0x48000593, 0xb400026c, "e,f,g", 0 },
|
||||
{ "i2s1.ss", 0x48000414, 0xb40003eb, "e,f,g", 0 },
|
||||
{ "i2s1.sd", 0x48000494, 0xb400036b, "e,f,g", 0 },
|
||||
{ "i2s1.dd", 0x48000594, 0xb400026b, "e,f,g", 0 },
|
||||
{ "i2st.ss", 0x48000415, 0xb40003ea, "e,f,g", 0 },
|
||||
{ "i2st.sd", 0x48000495, 0xb400036a, "e,f,g", 0 },
|
||||
{ "i2st.dd", 0x48000595, 0xb400026a, "e,f,g", 0 },
|
||||
{ "i2as1.ss", 0x48000416, 0xb40003e9, "e,f,g", 0 },
|
||||
{ "i2as1.sd", 0x48000496, 0xb4000369, "e,f,g", 0 },
|
||||
{ "i2as1.dd", 0x48000596, 0xb4000269, "e,f,g", 0 },
|
||||
{ "i2ast.ss", 0x48000417, 0xb40003e8, "e,f,g", 0 },
|
||||
{ "i2ast.sd", 0x48000497, 0xb4000368, "e,f,g", 0 },
|
||||
{ "i2ast.dd", 0x48000597, 0xb4000268, "e,f,g", 0 },
|
||||
{ "rat1s2.ss", 0x48000418, 0xb40003e7, "e,f,g", 0 },
|
||||
{ "rat1s2.sd", 0x48000498, 0xb4000367, "e,f,g", 0 },
|
||||
{ "rat1s2.dd", 0x48000598, 0xb4000267, "e,f,g", 0 },
|
||||
{ "m12asm.ss", 0x48000419, 0xb40003e6, "e,f,g", 0 },
|
||||
{ "m12asm.sd", 0x48000499, 0xb4000366, "e,f,g", 0 },
|
||||
{ "m12asm.dd", 0x48000599, 0xb4000266, "e,f,g", 0 },
|
||||
{ "ra1s2.ss", 0x4800041a, 0xb40003e5, "e,f,g", 0 },
|
||||
{ "ra1s2.sd", 0x4800049a, 0xb4000365, "e,f,g", 0 },
|
||||
{ "ra1s2.dd", 0x4800059a, 0xb4000265, "e,f,g", 0 },
|
||||
{ "m12ttsa.ss", 0x4800041b, 0xb40003e4, "e,f,g", 0 },
|
||||
{ "m12ttsa.sd", 0x4800049b, 0xb4000364, "e,f,g", 0 },
|
||||
{ "m12ttsa.dd", 0x4800059b, 0xb4000264, "e,f,g", 0 },
|
||||
{ "iat1s2.ss", 0x4800041c, 0xb40003e3, "e,f,g", 0 },
|
||||
{ "iat1s2.sd", 0x4800049c, 0xb4000363, "e,f,g", 0 },
|
||||
{ "iat1s2.dd", 0x4800059c, 0xb4000263, "e,f,g", 0 },
|
||||
{ "m12tsm.ss", 0x4800041d, 0xb40003e2, "e,f,g", 0 },
|
||||
{ "m12tsm.sd", 0x4800049d, 0xb4000362, "e,f,g", 0 },
|
||||
{ "m12tsm.dd", 0x4800059d, 0xb4000262, "e,f,g", 0 },
|
||||
{ "ia1s2.ss", 0x4800041e, 0xb40003e1, "e,f,g", 0 },
|
||||
{ "ia1s2.sd", 0x4800049e, 0xb4000361, "e,f,g", 0 },
|
||||
{ "ia1s2.dd", 0x4800059e, 0xb4000261, "e,f,g", 0 },
|
||||
{ "m12tsa.ss", 0x4800041f, 0xb40003e0, "e,f,g", 0 },
|
||||
{ "m12tsa.sd", 0x4800049f, 0xb4000360, "e,f,g", 0 },
|
||||
{ "m12tsa.dd", 0x4800059f, 0xb4000260, "e,f,g", 0 },
|
||||
|
||||
/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */
|
||||
{ "mr2p1.ss", 0x48000000, 0xb40007ff, "e,f,g", 0 },
|
||||
{ "mr2p1.sd", 0x48000080, 0xb400077f, "e,f,g", 0 },
|
||||
{ "mr2p1.dd", 0x48000180, 0xb400067f, "e,f,g", 0 },
|
||||
{ "mr2pt.ss", 0x48000001, 0xb40007fe, "e,f,g", 0 },
|
||||
{ "mr2pt.sd", 0x48000081, 0xb400077e, "e,f,g", 0 },
|
||||
{ "mr2pt.dd", 0x48000181, 0xb400067e, "e,f,g", 0 },
|
||||
{ "mr2mp1.ss", 0x48000002, 0xb40007fd, "e,f,g", 0 },
|
||||
{ "mr2mp1.sd", 0x48000082, 0xb400077d, "e,f,g", 0 },
|
||||
{ "mr2mp1.dd", 0x48000182, 0xb400067d, "e,f,g", 0 },
|
||||
{ "mr2mpt.ss", 0x48000003, 0xb40007fc, "e,f,g", 0 },
|
||||
{ "mr2mpt.sd", 0x48000083, 0xb400077c, "e,f,g", 0 },
|
||||
{ "mr2mpt.dd", 0x48000183, 0xb400067c, "e,f,g", 0 },
|
||||
{ "mi2p1.ss", 0x48000004, 0xb40007fb, "e,f,g", 0 },
|
||||
{ "mi2p1.sd", 0x48000084, 0xb400077b, "e,f,g", 0 },
|
||||
{ "mi2p1.dd", 0x48000184, 0xb400067b, "e,f,g", 0 },
|
||||
{ "mi2pt.ss", 0x48000005, 0xb40007fa, "e,f,g", 0 },
|
||||
{ "mi2pt.sd", 0x48000085, 0xb400077a, "e,f,g", 0 },
|
||||
{ "mi2pt.dd", 0x48000185, 0xb400067a, "e,f,g", 0 },
|
||||
{ "mi2mp1.ss", 0x48000006, 0xb40007f9, "e,f,g", 0 },
|
||||
{ "mi2mp1.sd", 0x48000086, 0xb4000779, "e,f,g", 0 },
|
||||
{ "mi2mp1.dd", 0x48000186, 0xb4000679, "e,f,g", 0 },
|
||||
{ "mi2mpt.ss", 0x48000007, 0xb40007f8, "e,f,g", 0 },
|
||||
{ "mi2mpt.sd", 0x48000087, 0xb4000778, "e,f,g", 0 },
|
||||
{ "mi2mpt.dd", 0x48000187, 0xb4000678, "e,f,g", 0 },
|
||||
{ "mrmt1p2.ss", 0x48000008, 0xb40007f7, "e,f,g", 0 },
|
||||
{ "mrmt1p2.sd", 0x48000088, 0xb4000777, "e,f,g", 0 },
|
||||
{ "mrmt1p2.dd", 0x48000188, 0xb4000677, "e,f,g", 0 },
|
||||
{ "mm12mpm.ss", 0x48000009, 0xb40007f6, "e,f,g", 0 },
|
||||
{ "mm12mpm.sd", 0x48000089, 0xb4000776, "e,f,g", 0 },
|
||||
{ "mm12mpm.dd", 0x48000189, 0xb4000676, "e,f,g", 0 },
|
||||
{ "mrm1p2.ss", 0x4800000a, 0xb40007f5, "e,f,g", 0 },
|
||||
{ "mrm1p2.sd", 0x4800008a, 0xb4000775, "e,f,g", 0 },
|
||||
{ "mrm1p2.dd", 0x4800018a, 0xb4000675, "e,f,g", 0 },
|
||||
{ "mm12ttpm.ss",0x4800000b, 0xb40007f4, "e,f,g", 0 },
|
||||
{ "mm12ttpm.sd",0x4800008b, 0xb4000774, "e,f,g", 0 },
|
||||
{ "mm12ttpm.dd",0x4800018b, 0xb4000674, "e,f,g", 0 },
|
||||
{ "mimt1p2.ss", 0x4800000c, 0xb40007f3, "e,f,g", 0 },
|
||||
{ "mimt1p2.sd", 0x4800008c, 0xb4000773, "e,f,g", 0 },
|
||||
{ "mimt1p2.dd", 0x4800018c, 0xb4000673, "e,f,g", 0 },
|
||||
{ "mm12tpm.ss", 0x4800000d, 0xb40007f2, "e,f,g", 0 },
|
||||
{ "mm12tpm.sd", 0x4800008d, 0xb4000772, "e,f,g", 0 },
|
||||
{ "mm12tpm.dd", 0x4800018d, 0xb4000672, "e,f,g", 0 },
|
||||
{ "mim1p2.ss", 0x4800000e, 0xb40007f1, "e,f,g", 0 },
|
||||
{ "mim1p2.sd", 0x4800008e, 0xb4000771, "e,f,g", 0 },
|
||||
{ "mim1p2.dd", 0x4800018e, 0xb4000671, "e,f,g", 0 },
|
||||
|
||||
/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */
|
||||
{ "mr2s1.ss", 0x48000010, 0xb40007ef, "e,f,g", 0 },
|
||||
{ "mr2s1.sd", 0x48000090, 0xb400076f, "e,f,g", 0 },
|
||||
{ "mr2s1.dd", 0x48000190, 0xb400066f, "e,f,g", 0 },
|
||||
{ "mr2st.ss", 0x48000011, 0xb40007ee, "e,f,g", 0 },
|
||||
{ "mr2st.sd", 0x48000091, 0xb400076e, "e,f,g", 0 },
|
||||
{ "mr2st.dd", 0x48000191, 0xb400066e, "e,f,g", 0 },
|
||||
{ "mr2ms1.ss", 0x48000012, 0xb40007ed, "e,f,g", 0 },
|
||||
{ "mr2ms1.sd", 0x48000092, 0xb400076d, "e,f,g", 0 },
|
||||
{ "mr2ms1.dd", 0x48000192, 0xb400066d, "e,f,g", 0 },
|
||||
{ "mr2mst.ss", 0x48000013, 0xb40007ec, "e,f,g", 0 },
|
||||
{ "mr2mst.sd", 0x48000093, 0xb400076c, "e,f,g", 0 },
|
||||
{ "mr2mst.dd", 0x48000193, 0xb400066c, "e,f,g", 0 },
|
||||
{ "mi2s1.ss", 0x48000014, 0xb40007eb, "e,f,g", 0 },
|
||||
{ "mi2s1.sd", 0x48000094, 0xb400076b, "e,f,g", 0 },
|
||||
{ "mi2s1.dd", 0x48000194, 0xb400066b, "e,f,g", 0 },
|
||||
{ "mi2st.ss", 0x48000015, 0xb40007ea, "e,f,g", 0 },
|
||||
{ "mi2st.sd", 0x48000095, 0xb400076a, "e,f,g", 0 },
|
||||
{ "mi2st.dd", 0x48000195, 0xb400066a, "e,f,g", 0 },
|
||||
{ "mi2ms1.ss", 0x48000016, 0xb40007e9, "e,f,g", 0 },
|
||||
{ "mi2ms1.sd", 0x48000096, 0xb4000769, "e,f,g", 0 },
|
||||
{ "mi2ms1.dd", 0x48000196, 0xb4000669, "e,f,g", 0 },
|
||||
{ "mi2mst.ss", 0x48000017, 0xb40007e8, "e,f,g", 0 },
|
||||
{ "mi2mst.sd", 0x48000097, 0xb4000768, "e,f,g", 0 },
|
||||
{ "mi2mst.dd", 0x48000197, 0xb4000668, "e,f,g", 0 },
|
||||
{ "mrmt1s2.ss", 0x48000018, 0xb40007e7, "e,f,g", 0 },
|
||||
{ "mrmt1s2.sd", 0x48000098, 0xb4000767, "e,f,g", 0 },
|
||||
{ "mrmt1s2.dd", 0x48000198, 0xb4000667, "e,f,g", 0 },
|
||||
{ "mm12msm.ss", 0x48000019, 0xb40007e6, "e,f,g", 0 },
|
||||
{ "mm12msm.sd", 0x48000099, 0xb4000766, "e,f,g", 0 },
|
||||
{ "mm12msm.dd", 0x48000199, 0xb4000666, "e,f,g", 0 },
|
||||
{ "mrm1s2.ss", 0x4800001a, 0xb40007e5, "e,f,g", 0 },
|
||||
{ "mrm1s2.sd", 0x4800009a, 0xb4000765, "e,f,g", 0 },
|
||||
{ "mrm1s2.dd", 0x4800019a, 0xb4000665, "e,f,g", 0 },
|
||||
{ "mm12ttsm.ss",0x4800001b, 0xb40007e4, "e,f,g", 0 },
|
||||
{ "mm12ttsm.sd",0x4800009b, 0xb4000764, "e,f,g", 0 },
|
||||
{ "mm12ttsm.dd",0x4800019b, 0xb4000664, "e,f,g", 0 },
|
||||
{ "mimt1s2.ss", 0x4800001c, 0xb40007e3, "e,f,g", 0 },
|
||||
{ "mimt1s2.sd", 0x4800009c, 0xb4000763, "e,f,g", 0 },
|
||||
{ "mimt1s2.dd", 0x4800019c, 0xb4000663, "e,f,g", 0 },
|
||||
{ "mm12tsm.ss", 0x4800001d, 0xb40007e2, "e,f,g", 0 },
|
||||
{ "mm12tsm.sd", 0x4800009d, 0xb4000762, "e,f,g", 0 },
|
||||
{ "mm12tsm.dd", 0x4800019d, 0xb4000662, "e,f,g", 0 },
|
||||
{ "mim1s2.ss", 0x4800001e, 0xb40007e1, "e,f,g", 0 },
|
||||
{ "mim1s2.sd", 0x4800009e, 0xb4000761, "e,f,g", 0 },
|
||||
{ "mim1s2.dd", 0x4800019e, 0xb4000661, "e,f,g", 0 },
|
||||
|
||||
|
||||
{ "fmul.ss", 0x48000020, 0xb40007df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
|
||||
{ "fmul.sd", 0x480000a0, 0xb400075f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
|
||||
{ "fmul.dd", 0x480001a0, 0xb400065f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
|
||||
{ "pfmul.ss", 0x48000420, 0xb40003df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
|
||||
{ "pfmul.sd", 0x480004a0, 0xb400035f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
|
||||
{ "pfmul.dd", 0x480005a0, 0xb400025f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
|
||||
{ "pfmul3.dd", 0x480005a4, 0xb400025b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */
|
||||
{ "fmlow.dd", 0x480001a1, 0xb400065e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */
|
||||
{ "frcp.ss", 0x48000022, 0xb40007dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */
|
||||
{ "frcp.sd", 0x480000a2, 0xb400075d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
|
||||
{ "frcp.dd", 0x480001a2, 0xb400065d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
|
||||
{ "frsqr.ss", 0x48000023, 0xb40007dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
|
||||
{ "frsqr.sd", 0x480000a3, 0xb400075c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
|
||||
{ "frsqr.dd", 0x480001a3, 0xb400065c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
|
||||
{ "fadd.ss", 0x48000030, 0xb40007cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
|
||||
{ "fadd.sd", 0x480000b0, 0xb400074f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
|
||||
{ "fadd.dd", 0x480001b0, 0xb400064f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
|
||||
{ "pfadd.ss", 0x48000430, 0xb40003cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
|
||||
{ "pfadd.sd", 0x480004b0, 0xb400034f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
|
||||
{ "pfadd.dd", 0x480005b0, 0xb400024f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
|
||||
{ "fsub.ss", 0x48000031, 0xb40007ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
|
||||
{ "fsub.sd", 0x480000b1, 0xb400074e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
|
||||
{ "fsub.dd", 0x480001b1, 0xb400064e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
|
||||
{ "pfsub.ss", 0x48000431, 0xb40003ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
|
||||
{ "pfsub.sd", 0x480004b1, 0xb400034e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
|
||||
{ "pfsub.dd", 0x480005b1, 0xb400024e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
|
||||
{ "fix.ss", 0x48000032, 0xb40007cd, "e,g", 0 }, /* fix.p fsrc1,fdest */
|
||||
{ "fix.sd", 0x480000b2, 0xb400074d, "e,g", 0 }, /* fix.p fsrc1,fdest */
|
||||
{ "fix.dd", 0x480001b2, 0xb400064d, "e,g", 0 }, /* fix.p fsrc1,fdest */
|
||||
{ "pfix.ss", 0x48000432, 0xb40003cd, "e,g", 0 }, /* pfix.p fsrc1,fdest */
|
||||
{ "pfix.sd", 0x480004b2, 0xb400034d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
|
||||
{ "pfix.dd", 0x480005b2, 0xb400024d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
|
||||
{ "famov.ss", 0x48000033, 0xb40007cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
|
||||
{ "famov.ds", 0x48000133, 0xb40006cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
|
||||
{ "famov.sd", 0x480000b3, 0xb400074c, "e,g", 0 }, /* famov.p fsrc1,fdest */
|
||||
{ "famov.dd", 0x480001b3, 0xb400064c, "e,g", 0 }, /* famov.p fsrc1,fdest */
|
||||
{ "pfamov.ss", 0x48000433, 0xb40003cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
|
||||
{ "pfamov.ds", 0x48000533, 0xb40002cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
|
||||
{ "pfamov.sd", 0x480004b3, 0xb400034c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
|
||||
{ "pfamov.dd", 0x480005b3, 0xb400024c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
|
||||
/* pfgt has R bit cleared; pfle has R bit set */
|
||||
{ "pfgt.ss", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
|
||||
{ "pfgt.sd", 0x48000434, 0xb40003cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
|
||||
{ "pfgt.dd", 0x48000534, 0xb40002cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
|
||||
/* pfgt has R bit cleared; pfle has R bit set */
|
||||
{ "pfle.ss", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
|
||||
{ "pfle.sd", 0x480004b4, 0xb400034b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
|
||||
{ "pfle.dd", 0x480005b4, 0xb400024b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
|
||||
{ "ftrunc.ss", 0x4800003a, 0xb40007c5, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
|
||||
{ "ftrunc.sd", 0x480000ba, 0xb4000745, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
|
||||
{ "ftrunc.dd", 0x480001ba, 0xb4000645, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
|
||||
{ "pftrunc.ss", 0x4800043a, 0xb40003c5, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
|
||||
{ "pftrunc.sd", 0x480004ba, 0xb4000345, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
|
||||
{ "pftrunc.dd", 0x480005ba, 0xb4000245, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
|
||||
{ "fxfr", 0x48000040, 0xb40007bf, "e,d", 0 }, /* fxfr fsrc1,idest */
|
||||
{ "fiadd.ss", 0x48000049, 0xb40007b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
|
||||
{ "fiadd.dd", 0x480001c9, 0xb4000636, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
|
||||
{ "pfiadd.ss", 0x48000449, 0xb40003b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
|
||||
{ "pfiadd.dd", 0x480005c9, 0xb4000236, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
|
||||
{ "fisub.ss", 0x4800004d, 0xb40007b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
|
||||
{ "fisub.dd", 0x480001cd, 0xb4000632, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
|
||||
{ "pfisub.ss", 0x4800044d, 0xb40003b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
|
||||
{ "pfisub.dd", 0x480005cd, 0xb4000232, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
|
||||
{ "fzchkl", 0x48000057, 0xb40007a8, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */
|
||||
{ "pfzchkl", 0x48000457, 0xb40003a8, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */
|
||||
{ "fzchks", 0x4800005f, 0xb40007a0, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */
|
||||
{ "pfzchks", 0x4800045f, 0xb40003a0, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */
|
||||
{ "faddp", 0x48000050, 0xb40007af, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */
|
||||
{ "pfaddp", 0x48000450, 0xb40003af, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */
|
||||
{ "faddz", 0x48000051, 0xb40007ae, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */
|
||||
{ "pfaddz", 0x48000451, 0xb40003ae, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */
|
||||
{ "form", 0x4800005a, 0xb40007a5, "e,g", 0 }, /* form fsrc1,fdest */
|
||||
{ "pform", 0x4800045a, 0xb40003a5, "e,g", 0 }, /* pform fsrc1,fdest */
|
||||
|
||||
/* Floating point pseudo-instructions */
|
||||
{ "fmov.ss", 0x48000049, 0xb7e007b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
|
||||
{ "fmov.dd", 0x480001c9, 0xb7e00636, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
|
||||
{ "fmov.sd", 0x480000b0, 0xb7e0074f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
|
||||
{ "fmov.ds", 0x48000130, 0xb7e006cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */
|
||||
{ "pfmov.ds", 0x48000530, 0xb73002cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */
|
||||
{ "pfmov.dd", 0x480005c9, 0xb7e00236, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
|
||||
|
||||
|
||||
};
|
||||
|
||||
#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue