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Change mips3_clockintr() to take (struct clockframe *) rather than 

pc and status since it calls hardclock(9) anyway.
OK'ed by gdamore on port-mips.
This commit is contained in:
tsutsui 2006-09-10 14:27:38 +00:00
parent 843ed515f0
commit e5dc12ca9c
5 changed files with 26 additions and 21 deletions
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10
sys/arch/algor/algor/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.9 2006/09/05 01:33:24 gdamore Exp $ */
/* $NetBSD: interrupt.c,v 1.10 2006/09/10 14:27:38 tsutsui Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.9 2006/09/05 01:33:24 gdamore Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.10 2006/09/10 14:27:38 tsutsui Exp $");
#include "opt_algor_p4032.h"
#include "opt_algor_p5064.h"
@ -145,11 +145,15 @@ intr_init(void)
void
cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{
struct clockframe cf;
uvmexp.intrs++;
if (ipending & MIPS_INT_MASK_5) {
mips3_clockintr(status, pc);
cf.pc = pc;
cf.sr = status;
mips3_clockintr(&cf);
/* Re-enable clock interrupts. */
cause &= ~MIPS_INT_MASK_5;

10
sys/arch/cobalt/cobalt/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.73 2006/09/10 06:41:09 tsutsui Exp $ */
/* $NetBSD: machdep.c,v 1.74 2006/09/10 14:27:38 tsutsui Exp $ */
/*
* Copyright (c) 2006 Izumi Tsutsui.
@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.73 2006/09/10 06:41:09 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.74 2006/09/10 14:27:38 tsutsui Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -663,9 +663,7 @@ cpu_intr_disestablish(void *cookie)
void
cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
{
#if 0
struct clockframe cf;
#endif
struct cobalt_intrhand *ih;
uvmexp.intrs++;
@ -673,7 +671,9 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
if (ipending & MIPS_INT_MASK_5) {
/* call the common MIPS3 clock interrupt handler */
mips3_clockintr(status, pc);
cf.pc = pc;
cf.sr = status;
mips3_clockintr(&cf);
cause &= ~MIPS_INT_MASK_5;
}

10
sys/arch/evbmips/evbmips/interrupt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $ */
/* $NetBSD: interrupt.c,v 1.9 2006/09/10 14:27:38 tsutsui Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.8 2006/09/02 22:54:47 gdamore Exp $");
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.9 2006/09/10 14:27:38 tsutsui Exp $");
#include <sys/param.h>
#include <sys/device.h>
@ -60,11 +60,15 @@ intr_init(void)
void
cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{
struct clockframe cf;
uvmexp.intrs++;
if (ipending & MIPS_INT_MASK_5) {
/* call the common MIPS3 clock interrupt handler */
mips3_clockintr(status, pc);
cf.pc = pc;
cf.sr = status;
mips3_clockintr(&cf);
/* Re-enable clock interrupts. */
cause &= ~MIPS_INT_MASK_5;

4
sys/arch/mips/include/mips3_clock.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips3_clock.h,v 1.3 2006/09/08 23:39:27 gdamore Exp $ */
/* $NetBSD: mips3_clock.h,v 1.4 2006/09/10 14:27:38 tsutsui Exp $ */
/*
* Copyright (c) 2006 Garrett D'Amore.
@ -34,7 +34,7 @@
#ifndef _MIPS3_CLOCK_H
#define _MIPS3_CLOCK_H
void mips3_clockintr(uint32_t, uint32_t);
void mips3_clockintr(struct clockframe *);
void mips3_initclocks(void);
void mips3_delay(int);
void mips3_setstatclockrate(int);

13
sys/arch/mips/mips/mips3_clockintr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips3_clockintr.c,v 1.1 2006/09/08 23:39:28 gdamore Exp $ */
/* $NetBSD: mips3_clockintr.c,v 1.2 2006/09/10 14:27:38 tsutsui Exp $ */
/*
* Copyright (c) 1992, 1993
@ -78,7 +78,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips3_clockintr.c,v 1.1 2006/09/08 23:39:28 gdamore Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips3_clockintr.c,v 1.2 2006/09/10 14:27:38 tsutsui Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -101,10 +101,9 @@ uint32_t next_cp0_clk_intr; /* used to schedule hard clock interrupts */
* cpu_intr() routine.
*/
void
mips3_clockintr(uint32_t status, uint32_t pc)
mips3_clockintr(struct clockframe *cfp)
{
uint32_t new_cnt;
struct clockframe cf;
uint32_t new_cnt;
next_cp0_clk_intr += curcpu()->ci_cycles_per_hz;
mips3_cp0_compare_write(next_cp0_clk_intr);
@ -123,9 +122,7 @@ mips3_clockintr(uint32_t status, uint32_t pc)
mips_int5_missed_evcnt.ev_count++;
}
cf.pc = pc;
cf.sr = status;
hardclock(&cf);
hardclock(cfp);
mips_int5_evcnt.ev_count++;