Cleanup (add some checks, remove dead code).
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@ -1,4 +1,4 @@
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/* $NetBSD: clock.c,v 1.22 1994/12/30 17:17:55 gwr Exp $ */
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/* $NetBSD: clock.c,v 1.23 1995/01/18 17:13:57 gwr Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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@ -74,29 +74,27 @@ volatile char *clock_va;
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(run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \
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INTERSIL_CMD_NORMAL_MODE)
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#define intersil_disable() \
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intersil_clock->clk_cmd_reg = \
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE)
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#define intersil_enable() \
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intersil_clock->clk_cmd_reg = \
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE)
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#define intersil_clear() intersil_clock->clk_intr_reg
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#define intersil_clear() (void)intersil_clock->clk_intr_reg
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int clockmatch __P((struct device *, void *vcf, void *args));
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void clockattach __P((struct device *, struct device *, void *));
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struct cfdriver clockcd =
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{ NULL, "clock", clockmatch, clockattach, DV_DULL,
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sizeof(struct device), 0};
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struct cfdriver clockcd = {
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NULL, "clock", clockmatch, clockattach,
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DV_DULL, sizeof(struct device), 0 };
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/* Called very earyl by internal_configure. */
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/* Called very early by internal_configure. */
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void clock_init()
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{
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clock_va = obio_find_mapping(OBIO_CLOCK, OBIO_CLOCK_SIZE);
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if (!clock_va)
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mon_panic("clock VA not found\n");
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mon_panic("clock_init: clock_va\n");
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if (!interrupt_reg)
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mon_panic("clock_init: interrupt_reg\n");
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/* Turn off clock interrupts until cpu_initclocks() */
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intersil_clock->clk_cmd_reg =
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
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intersil_clear();
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}
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int clockmatch(parent, vcf, args)
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@ -109,8 +107,6 @@ int clockmatch(parent, vcf, args)
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/* This driver only supports one unit. */
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if (cf->cf_unit != 0)
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return (0);
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if (clock_va == NULL)
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return (0);
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if (ca->ca_paddr == -1)
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ca->ca_paddr = OBIO_CLOCK;
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if (ca->ca_intpri == -1)
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@ -130,10 +126,7 @@ void clockattach(parent, self, args)
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if (ca->ca_intpri != 5)
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panic("clock: level != 5");
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/* Initialize, connect ISR. */
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intersil_disable();
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set_clk_mode(0, IREG_CLOCK_ENAB_7, 0);
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isr_add_custom(ca->ca_intpri, level5intr_clock); /* XXX */
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isr_add_custom(5, level5intr_clock);
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set_clk_mode(IREG_CLOCK_ENAB_5, 0, 0);
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}
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@ -146,7 +139,11 @@ set_clk_mode(on, off, enable)
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u_char on, off;
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int enable;
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{
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register u_char interreg, dummy;
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register u_char interreg;
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if (!intersil_clock)
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panic("set_clk_mode");
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/*
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* make sure that we are only playing w/
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* clock interrupt register bits
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@ -170,7 +167,7 @@ set_clk_mode(on, off, enable)
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*interrupt_reg &= ~(IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5);
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intersil_clock->clk_cmd_reg =
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
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dummy = intersil_clock->clk_intr_reg; /* clear clock */
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intersil_clear();
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/*
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* Now we set all the desired bits
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@ -195,16 +192,11 @@ void
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cpu_initclocks(void)
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{
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struct timer_softc *clock;
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unsigned char dummy;
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if (clockcd.cd_ndevs < 1 ||
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!(clock = clockcd.cd_devs[0]))
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panic("cpu_initclocks: no timer");
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/* make sure irq5/7 stuff is resolved :) */
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dummy = intersil_clear();
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if (!intersil_clock)
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panic("cpu_initclocks");
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intersil_clear();
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intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
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intersil_clock->clk_cmd_reg =
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
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@ -222,35 +214,10 @@ setstatclockrate(newhz)
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}
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/*
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* Startrtclock restarts the real-time clock, which provides
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* hardclock interrupts to kern_clock.c.
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* This is is called by the "custom" interrupt handler
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* after it has reset the pending bit in the clock.
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*/
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void startrtclock()
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{
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char dummy;
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if (!intersil_clock)
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panic("clock: not initialized");
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intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
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intersil_clock->clk_cmd_reg =
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
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dummy = intersil_clear();
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}
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void enablertclock()
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{
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unsigned char dummy;
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/* make sure irq5/7 stuff is resolved :) */
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dummy = intersil_clear();
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intersil_clock->clk_intr_reg = INTERSIL_INTER_CSECONDS;
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intersil_clock->clk_cmd_reg =
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intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
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}
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int clock_count = 0;
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void clock_intr(frame)
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struct clockframe *frame;
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{
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