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Start replacing the x86 PTE bits.

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This commit is contained in:
maxv 2019-03-09 08:42:25 +00:00
parent 26a59cedc6
commit e4552b509f
31 changed files with 321 additions and 332 deletions
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6
sys/arch/amd64/amd64/db_disasm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_disasm.c,v 1.26 2019/02/03 03:19:26 mrg Exp $ */
/* $NetBSD: db_disasm.c,v 1.27 2019/03/09 08:42:25 maxv Exp $ */
/*
* Mach Operating System
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.26 2019/02/03 03:19:26 mrg Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.27 2019/03/09 08:42:25 maxv Exp $");
#ifndef _KERNEL
#include <sys/types.h>
@ -1212,7 +1212,7 @@ db_disasm(db_addr_t loc, bool altfmt)
else
pde = vtopte((vaddr_t)pte);
if ((*pde & PG_V) == 0 || (*pte & PG_V) == 0) {
if ((*pde & PTE_P) == 0 || (*pte & PTE_P) == 0) {
db_printf("invalid address\n");
return (loc);
}

6
sys/arch/amd64/amd64/gdt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gdt.c,v 1.46 2019/02/11 14:59:32 cherry Exp $ */
/* $NetBSD: gdt.c,v 1.47 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 1996, 1997, 2009 The NetBSD Foundation, Inc.
@ -37,7 +37,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gdt.c,v 1.46 2019/02/11 14:59:32 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: gdt.c,v 1.47 2019/03/09 08:42:25 maxv Exp $");
#include "opt_multiprocessor.h"
#include "opt_xen.h"
@ -330,7 +330,7 @@ lgdt(struct region_descriptor *desc)
va = desc->rd_base + (i << PAGE_SHIFT);
frames[i] = ((paddr_t)xpmap_ptetomach((pt_entry_t *)va)) >>
PAGE_SHIFT;
pmap_pte_clearbits(kvtopte(va), PG_RW);
pmap_pte_clearbits(kvtopte(va), PTE_W);
}
if (HYPERVISOR_set_gdt(frames, (desc->rd_limit + 1) >> 3))

36
sys/arch/amd64/amd64/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.179 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: locore.S,v 1.180 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright-o-rama!
@ -187,8 +187,8 @@
#define _RELOC(x) ((x) - KERNBASE)
#define RELOC(x) _RELOC(_C_LABEL(x))
/* 32bit version of PG_NX */
#define PG_NX32 0x80000000
/* 32bit version of PTE_NX */
#define PTE_NX32 0x80000000
#if L2_SLOT_KERNBASE > 0
#define TABLE_L2_ENTRIES (2 * (NKL2_KIMG_ENTRIES + 1))
@ -307,7 +307,7 @@
ELFNOTE(Xen, XEN_ELFNOTE_HV_START_LOW, .quad, HYPERVISOR_VIRT_START)
ELFNOTE(Xen, XEN_ELFNOTE_FEATURES, .asciz, "")
ELFNOTE(Xen, XEN_ELFNOTE_PAE_MODE, .asciz, "yes")
ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID, .long, PG_V, PG_V)\
ELFNOTE(Xen, XEN_ELFNOTE_L1_MFN_VALID, .long, PTE_P, PTE_P)\
ELFNOTE(Xen, XEN_ELFNOTE_LOADER, .asciz, "generic")
ELFNOTE(Xen, XEN_ELFNOTE_SUSPEND_CANCEL, .long, 0)
#if NKSYMS > 0 || defined(DDB) || defined(MODULAR)
@ -586,13 +586,13 @@ ENTRY(start)
movl $RELOC(tmpstk),%esp
/*
* Retrieve the NX/XD flag. We use the 32bit version of PG_NX.
* Retrieve the NX/XD flag. We use the 32bit version of PTE_NX.
*/
movl $0x80000001,%eax
cpuid
andl $CPUID_NOX,%edx
jz .Lno_NOX
movl $PG_NX32,RELOC(nox_flag)
movl $PTE_NX32,RELOC(nox_flag)
.Lno_NOX:
/*
@ -680,7 +680,7 @@ ENTRY(start)
movl $RELOC(__rodata_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt
/* Map the kernel rodata R. */
@ -688,7 +688,7 @@ ENTRY(start)
movl $RELOC(__data_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt_nox
/* Map the kernel data+bss RW. */
@ -696,7 +696,7 @@ ENTRY(start)
movl $RELOC(__kernel_end),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map [SYMS]+[PRELOADED MODULES] RW. */
@ -704,21 +704,21 @@ ENTRY(start)
movl %esi,%ecx /* start of BOOTSTRAP TABLES */
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map the BOOTSTRAP TABLES RW. */
movl %esi,%eax /* start of BOOTSTRAP TABLES */
movl $TABLESIZE,%ecx /* length of BOOTSTRAP TABLES */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* We are on (4). Map ISA I/O MEM RW. */
movl $IOM_BEGIN,%eax
movl $IOM_SIZE,%ecx /* size of ISA I/O MEM */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW/*|PG_N*/),%eax
orl $(PTE_P|PTE_W/*|PTE_PCD*/),%eax
fillkpt_nox
/*
@ -726,7 +726,7 @@ ENTRY(start)
*/
leal (PROC0_PTP2_OFF)(%esi),%ebx
leal (PROC0_PTP1_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $(NKL2_KIMG_ENTRIES+1),%ecx
fillkpt
@ -734,7 +734,7 @@ ENTRY(start)
/* If needed, set up level 2 entries for actual kernel mapping */
leal (PROC0_PTP2_OFF + L2_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PTP1_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $(NKL2_KIMG_ENTRIES+1),%ecx
fillkpt
#endif
@ -744,7 +744,7 @@ ENTRY(start)
*/
leal (PROC0_PTP3_OFF)(%esi),%ebx
leal (PROC0_PTP2_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL3_KIMG_ENTRIES,%ecx
fillkpt
@ -752,7 +752,7 @@ ENTRY(start)
/* If needed, set up level 3 entries for actual kernel mapping */
leal (PROC0_PTP3_OFF + L3_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PTP2_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL3_KIMG_ENTRIES,%ecx
fillkpt
#endif
@ -762,14 +762,14 @@ ENTRY(start)
*/
leal (PROC0_PML4_OFF)(%esi),%ebx
leal (PROC0_PTP3_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL4_KIMG_ENTRIES,%ecx
fillkpt
/* Set up L4 entries for actual kernel mapping */
leal (PROC0_PML4_OFF + L4_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PTP3_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL4_KIMG_ENTRIES,%ecx
fillkpt

8
sys/arch/amd64/amd64/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.326 2019/02/14 08:18:25 cherry Exp $ */
/* $NetBSD: machdep.c,v 1.327 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
@ -110,7 +110,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.326 2019/02/14 08:18:25 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.327 2019/03/09 08:42:25 maxv Exp $");
#include "opt_modular.h"
#include "opt_user_ldt.h"
@ -1589,8 +1589,8 @@ init_pte(void)
#ifndef XENPV
extern uint32_t nox_flag;
pd_entry_t *pdir = (pd_entry_t *)bootspace.pdir;
pdir[L4_SLOT_PTE] = PDPpaddr | PG_KW | ((uint64_t)nox_flag << 32) |
PG_V;
pdir[L4_SLOT_PTE] = PDPpaddr | PTE_W | ((uint64_t)nox_flag << 32) |
PTE_P;
#endif
extern pd_entry_t *normal_pdes[3];

10
sys/arch/amd64/include/asan.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: asan.h,v 1.2 2019/02/04 15:07:34 maxv Exp $ */
/* $NetBSD: asan.h,v 1.3 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@ -102,19 +102,19 @@ kasan_md_shadow_map_page(vaddr_t va)
if (!pmap_valid_entry(L4_BASE[pl4_i(va)])) {
pa = __md_palloc();
L4_BASE[pl4_i(va)] = pa | PG_KW | pmap_pg_nx | PG_V;
L4_BASE[pl4_i(va)] = pa | PTE_W | pmap_pg_nx | PTE_P;
}
if (!pmap_valid_entry(L3_BASE[pl3_i(va)])) {
pa = __md_palloc();
L3_BASE[pl3_i(va)] = pa | PG_KW | pmap_pg_nx | PG_V;
L3_BASE[pl3_i(va)] = pa | PTE_W | pmap_pg_nx | PTE_P;
}
if (!pmap_valid_entry(L2_BASE[pl2_i(va)])) {
pa = __md_palloc();
L2_BASE[pl2_i(va)] = pa | PG_KW | pmap_pg_nx | PG_V;
L2_BASE[pl2_i(va)] = pa | PTE_W | pmap_pg_nx | PTE_P;
}
if (!pmap_valid_entry(L1_BASE[pl1_i(va)])) {
pa = __md_palloc();
L1_BASE[pl1_i(va)] = pa | PG_KW | pmap_pg_g | pmap_pg_nx | PG_V;
L1_BASE[pl1_i(va)] = pa | PTE_W | pmap_pg_g | pmap_pg_nx | PTE_P;
}
}

47
sys/arch/amd64/include/pte.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pte.h,v 1.11 2019/03/07 14:40:35 maxv Exp $ */
/* $NetBSD: pte.h,v 1.12 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -120,30 +120,27 @@ typedef uint64_t pt_entry_t; /* PTE */
#define PTE_FRAME PTE_4KFRAME
#define PTE_LGFRAME PTE_2MFRAME
/*
* PDE/PTE bits. These are no different from their i386 counterparts.
* XXX To be deleted.
*/
#define PG_V 0x0000000000000001 /* valid */
#define PG_RW 0x0000000000000002 /* read-write */
#define PG_u 0x0000000000000004 /* user accessible */
#define PG_WT 0x0000000000000008 /* write-through */
#define PG_N 0x0000000000000010 /* non-cacheable */
#define PG_U 0x0000000000000020 /* used */
#define PG_M 0x0000000000000040 /* modified */
#define PG_PAT 0x0000000000000080 /* PAT (on pte) */
#define PG_PS 0x0000000000000080 /* 2MB page size (on pde) */
#define PG_G 0x0000000000000100 /* not flushed */
#define PG_AVAIL1 0x0000000000000200
#define PG_AVAIL2 0x0000000000000400
#define PG_AVAIL3 0x0000000000000800
#define PG_LGPAT 0x0000000000001000 /* PAT on large pages */
#define PG_FRAME 0x000ffffffffff000
#define PG_NX 0x8000000000000000
#define PG_2MFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
#define PG_1GFRAME 0x000fffffc0000000 /* large (1G) page frame mask */
#define PG_LGFRAME PG_2MFRAME
#define PG_KW 0x0000000000000002 /* kernel read-write */
/* XXX To be deleted. */
#define PG_V PTE_P
#define PG_RW PTE_W
#define PG_u PTE_U
#define PG_WT PTE_PWT
#define PG_N PTE_PCD
#define PG_U PTE_A
#define PG_M PTE_D
#define PG_PAT PTE_PAT
#define PG_PS PTE_PS
#define PG_G PTE_G
#define PG_AVAIL1 PTE_AVL1
#define PG_AVAIL2 PTE_AVL2
#define PG_AVAIL3 PTE_AVL3
#define PG_LGPAT PTE_LGPAT
#define PG_FRAME PTE_FRAME
#define PG_NX PTE_NX
#define PG_2MFRAME PTE_2MFRAME
#define PG_1GFRAME PTE_1GFRAME
#define PG_LGFRAME PTE_LGFRAME
#define PG_KW PTE_W
#include <x86/pte.h>

30
sys/arch/amd64/stand/prekern/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.9 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: locore.S,v 1.10 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 1998, 2000, 2007, 2008, 2016, 2017 The NetBSD Foundation, Inc.
@ -51,8 +51,8 @@
#include "pdir.h"
#include "redef.h"
/* 32bit version of PG_NX */
#define PG_NX32 0x80000000
/* 32bit version of PTE_NX */
#define PTE_NX32 0x80000000
#define TABLE_L2_ENTRIES (NKL2_KIMG_ENTRIES + 1)
#define TABLE_L3_ENTRIES NKL3_KIMG_ENTRIES
@ -326,13 +326,13 @@ ENTRY(start)
movl %eax,_C_LABEL(cpuid_level)
/*
* Retrieve the NX/XD flag. We use the 32bit version of PG_NX.
* Retrieve the NX/XD flag. We use the 32bit version of PTE_NX.
*/
movl $0x80000001,%eax
cpuid
andl $CPUID_NOX,%edx
jz .Lno_NOX
movl $PG_NX32,_C_LABEL(nox_flag)
movl $PTE_NX32,_C_LABEL(nox_flag)
.Lno_NOX:
/*
@ -424,7 +424,7 @@ ENTRY(start)
movl $_C_LABEL(__rodata_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt
/* Map the prekern rodata R. */
@ -432,7 +432,7 @@ ENTRY(start)
movl $_C_LABEL(__data_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt_nox
/* Map the prekern data+bss RW. */
@ -440,7 +440,7 @@ ENTRY(start)
movl $_C_LABEL(__prekern_end),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map a RO view of the kernel. */
@ -448,21 +448,21 @@ ENTRY(start)
movl %esi,%ecx /* start of BOOTSTRAP TABLES */
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt_nox
/* Map the BOOTSTRAP TABLES RW. */
movl %esi,%eax /* start of BOOTSTRAP TABLES */
movl $TABLESIZE,%ecx /* length of BOOTSTRAP TABLES */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map the ISA I/O MEM RW. */
movl $IOM_BEGIN,%eax
movl $IOM_SIZE,%ecx /* size of ISA I/O MEM */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW/*|PG_N*/),%eax
orl $(PTE_P|PTE_W/*|PTE_PCD*/),%eax
fillkpt_nox
/*
@ -470,7 +470,7 @@ ENTRY(start)
*/
leal (PROC0_PTP2_OFF)(%esi),%ebx
leal (PROC0_PTP1_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $(NKL2_KIMG_ENTRIES+1),%ecx
fillkpt
@ -479,7 +479,7 @@ ENTRY(start)
*/
leal (PROC0_PTP3_OFF)(%esi),%ebx
leal (PROC0_PTP2_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL3_KIMG_ENTRIES,%ecx
fillkpt
@ -488,14 +488,14 @@ ENTRY(start)
*/
leal (PROC0_PML4_OFF)(%esi),%ebx
leal (PROC0_PTP3_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $NKL4_KIMG_ENTRIES,%ecx
fillkpt
/* Install recursive top level PDE (one entry) */
leal (PROC0_PML4_OFF + PDIR_SLOT_PTE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PML4_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $1,%ecx
fillkpt_nox

22
sys/arch/amd64/stand/prekern/mm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mm.c,v 1.23 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: mm.c,v 1.24 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc. All rights reserved.
@ -44,8 +44,8 @@ static const uint8_t pads[4] = {
#define MM_PROT_EXECUTE 0x02
static const pt_entry_t protection_codes[3] = {
[MM_PROT_READ] = PG_NX,
[MM_PROT_WRITE] = PG_RW | PG_NX,
[MM_PROT_READ] = PTE_NX,
[MM_PROT_WRITE] = PTE_W | PTE_NX,
[MM_PROT_EXECUTE] = 0,
/* RWX does not exist */
};
@ -67,16 +67,16 @@ mm_init(paddr_t first_pa)
static void
mm_enter_pa(paddr_t pa, vaddr_t va, pte_prot_t prot)
{
if (PTE_BASE[pl1_i(va)] & PG_V) {
if (PTE_BASE[pl1_i(va)] & PTE_P) {
fatal("mm_enter_pa: mapping already present");
}
PTE_BASE[pl1_i(va)] = pa | PG_V | protection_codes[prot];
PTE_BASE[pl1_i(va)] = pa | PTE_P | protection_codes[prot];
}
static void
mm_reenter_pa(paddr_t pa, vaddr_t va, pte_prot_t prot)
{
PTE_BASE[pl1_i(va)] = pa | PG_V | protection_codes[prot];
PTE_BASE[pl1_i(va)] = pa | PTE_P | protection_codes[prot];
}
static void
@ -109,7 +109,7 @@ mm_palloc(size_t npages)
static bool
mm_pte_is_valid(pt_entry_t pte)
{
return ((pte & PG_V) != 0);
return ((pte & PTE_P) != 0);
}
static void
@ -124,7 +124,7 @@ mm_mprotect(vaddr_t startva, size_t size, pte_prot_t prot)
for (i = 0; i < npages; i++) {
va = startva + i * PAGE_SIZE;
pa = (PTE_BASE[pl1_i(va)] & PG_FRAME);
pa = (PTE_BASE[pl1_i(va)] & PTE_FRAME);
mm_reenter_pa(pa, va, prot);
mm_flush_va(va);
}
@ -175,7 +175,7 @@ mm_map_tree(vaddr_t startva, vaddr_t endva)
ASSERT(nL4e == 1);
if (!mm_pte_is_valid(L4_BASE[L4e_idx])) {
pa = mm_palloc(1);
L4_BASE[L4e_idx] = pa | PG_V | PG_RW;
L4_BASE[L4e_idx] = pa | PTE_P | PTE_W;
}
/* Build L3. */
@ -186,7 +186,7 @@ mm_map_tree(vaddr_t startva, vaddr_t endva)
continue;
}
pa = mm_palloc(1);
L3_BASE[L3e_idx+i] = pa | PG_V | PG_RW;
L3_BASE[L3e_idx+i] = pa | PTE_P | PTE_W;
}
/* Build L2. */
@ -197,7 +197,7 @@ mm_map_tree(vaddr_t startva, vaddr_t endva)
continue;
}
pa = mm_palloc(1);
L2_BASE[L2e_idx+i] = pa | PG_V | PG_RW;
L2_BASE[L2e_idx+i] = pa | PTE_P | PTE_W;
}
}

6
sys/arch/i386/i386/db_disasm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_disasm.c,v 1.47 2015/05/13 02:37:41 msaitoh Exp $ */
/* $NetBSD: db_disasm.c,v 1.48 2019/03/09 08:42:25 maxv Exp $ */
/*
* Mach Operating System
@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.47 2015/05/13 02:37:41 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.48 2019/03/09 08:42:25 maxv Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@ -1146,7 +1146,7 @@ db_disasm(db_addr_t loc, bool altfmt)
else
pte = vtopte((vaddr_t)loc);
pde = vtopte((vaddr_t)pte);
if ((*pde & PG_V) == 0 || (*pte & PG_V) == 0) {
if ((*pde & PTE_P) == 0 || (*pte & PTE_P) == 0) {
db_printf("invalid address\n");
return (loc);
}

8
sys/arch/i386/i386/gdt.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: gdt.c,v 1.69 2019/02/11 14:59:32 cherry Exp $ */
/* $NetBSD: gdt.c,v 1.70 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 1996, 1997, 2009 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gdt.c,v 1.69 2019/02/11 14:59:32 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: gdt.c,v 1.70 2019/03/09 08:42:25 maxv Exp $");
#include "opt_multiprocessor.h"
#include "opt_xen.h"
@ -211,12 +211,12 @@ gdt_init_cpu(struct cpu_info *ci)
/*
* Our own
* pmap_pte_clearbits(ptp, PG_RW)
* pmap_pte_clearbits(ptp, PTE_W)
* but without spl(), since %fs is not set up properly yet; ie
* curcpu() won't work at this point and spl() will break.
*/
if (HYPERVISOR_update_va_mapping((vaddr_t)va,
*ptp & ~PG_RW, UVMF_INVLPG) < 0) {
*ptp & ~PTE_W, UVMF_INVLPG) < 0) {
panic("%s page RO update failed.\n", __func__);
}
}

4
sys/arch/i386/i386/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.112 2019/03/07 13:26:24 maxv Exp $
# $NetBSD: genassym.cf,v 1.113 2019/03/09 08:42:25 maxv Exp $
#
# Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@ -144,6 +144,8 @@ define KERNTEXTOFF KERNTEXTOFF
define PG_RW PG_RW
define PG_V PG_V
define PG_KW PG_KW
define PTE_P PTE_P
define PTE_W PTE_W
define PGEX_U PGEX_U
define L2_SLOT_KERNBASE pl2_pi(KERNBASE)

32
sys/arch/i386/i386/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.165 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: locore.S,v 1.166 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright-o-rama!
@ -128,7 +128,7 @@
*/
#include <machine/asm.h>
__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.165 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.166 2019/03/09 08:42:25 maxv Exp $");
#include "opt_copy_symtab.h"
#include "opt_ddb.h"
@ -167,8 +167,8 @@ __KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.165 2019/03/07 13:26:24 maxv Exp $");
#endif /* XENPV */
#define RELOC(x) _RELOC(_C_LABEL(x))
/* 32bit version of PG_NX */
#define PG_NX32 0x80000000
/* 32bit version of PTE_NX */
#define PTE_NX32 0x80000000
#ifndef PAE
#define PROC0_PDIR_OFF 0
@ -551,13 +551,13 @@ try586: /* Use the `cpuid' instruction. */
movl %eax,RELOC(cpuid_level)
/*
* Retrieve the NX/XD flag. We use the 32bit version of PG_NX.
* Retrieve the NX/XD flag. We use the 32bit version of PTE_NX.
*/
movl $0x80000001,%eax
cpuid
andl $CPUID_NOX,%edx
jz no_NOX
movl $PG_NX32,RELOC(nox_flag)
movl $PTE_NX32,RELOC(nox_flag)
no_NOX:
2:
@ -693,7 +693,7 @@ no_NOX:
movl $RELOC(__rodata_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt
/* Map the kernel rodata R. */
@ -701,7 +701,7 @@ no_NOX:
movl $RELOC(__data_start),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V),%eax
orl $(PTE_P),%eax
fillkpt_nox
/* Map the kernel data+bss RW. */
@ -709,7 +709,7 @@ no_NOX:
movl $RELOC(__kernel_end),%ecx
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map [SYMS]+[PRELOADED MODULES] RW. */
@ -717,21 +717,21 @@ no_NOX:
movl %esi,%ecx /* start of BOOTSTRAP TABLES */
subl %eax,%ecx
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* Map the BOOTSTRAP TABLES RW. */
movl %esi,%eax /* start of BOOTSTRAP TABLES */
movl RELOC(tablesize),%ecx /* length of BOOTSTRAP TABLES */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
fillkpt_nox
/* We are on (4). Map ISA I/O MEM RW. */
movl $IOM_BEGIN,%eax
movl $IOM_SIZE,%ecx /* size of ISA I/O MEM */
shrl $PGSHIFT,%ecx
orl $(PG_V|PG_KW/*|PG_N*/),%eax
orl $(PTE_P|PTE_W/*|PTE_PCD*/),%eax
fillkpt_nox
/*
@ -739,21 +739,21 @@ no_NOX:
*/
leal (PROC0_PDIR_OFF)(%esi),%ebx
leal (PROC0_PTP1_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl RELOC(nkptp)+1*4,%ecx
fillkpt
/* Set up L2 entries for actual kernel mapping */
leal (PROC0_PDIR_OFF + L2_SLOT_KERNBASE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PTP1_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl RELOC(nkptp)+1*4,%ecx
fillkpt
/* Install recursive top level PDE */
leal (PROC0_PDIR_OFF + PDIR_SLOT_PTE * PDE_SIZE)(%esi),%ebx
leal (PROC0_PDIR_OFF)(%esi),%eax
orl $(PG_V|PG_KW),%eax
orl $(PTE_P|PTE_W),%eax
movl $PDP_SIZE,%ecx
fillkpt_nox
@ -763,7 +763,7 @@ no_NOX:
*/
leal (PROC0_L3_OFF)(%esi),%ebx
leal (PROC0_PDIR_OFF)(%esi),%eax
orl $(PG_V),%eax
orl $(PTE_P),%eax
movl $PDP_SIZE,%ecx
fillkpt

8
sys/arch/i386/i386/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.817 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: machdep.c,v 1.818 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006, 2008, 2009, 2017
@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.817 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.818 2019/03/09 08:42:25 maxv Exp $");
#include "opt_beep.h"
#include "opt_compat_freebsd.h"
@ -1029,7 +1029,7 @@ initgdt(union descriptor *tgdt)
pt_entry_t pte;
pte = pmap_pa2pte((vaddr_t)gdtstore - KERNBASE);
pte |= xpmap_pg_nx | PG_V;
pte |= xpmap_pg_nx | PTE_P;
if (HYPERVISOR_update_va_mapping((vaddr_t)gdtstore, pte,
UVMF_INVLPG) < 0) {
@ -1262,7 +1262,7 @@ init386(paddr_t first_avail)
pt_entry_t pte;
pte = pmap_pa2pte((vaddr_t)tmpgdt - KERNBASE);
pte |= PG_RW | xpmap_pg_nx | PG_V;
pte |= PTE_W | xpmap_pg_nx | PTE_P;
if (HYPERVISOR_update_va_mapping((vaddr_t)tmpgdt, pte, UVMF_INVLPG) < 0) {
panic("tmpgdt page relaim RW update failed.\n");

44
sys/arch/i386/include/pte.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pte.h,v 1.30 2019/03/07 14:40:35 maxv Exp $ */
/* $NetBSD: pte.h,v 1.31 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@ -175,31 +175,23 @@ typedef uint32_t pt_entry_t; /* PTE */
#define PTE_NX 0 /* Dummy */
#endif
/*
* here we define the bits of the PDE/PTE, as described above:
* XXXCDC: need to rename these (PG_u == ugly).
* XXX To be deleted.
*/
#define PG_V 0x00000001 /* valid entry */
#define PG_RW 0x00000002 /* read-write page */
#define PG_u 0x00000004 /* user accessible page */
#define PG_WT 0x00000008 /* write through */
#define PG_N 0x00000010 /* non-cacheable */
#define PG_U 0x00000020 /* has been used */
#define PG_M 0x00000040 /* has been modified */
#define PG_PAT 0x00000080 /* PAT (on pte) */
#define PG_PS 0x00000080 /* 4MB page size (2MB for PAE) */
#define PG_G 0x00000100 /* global, don't TLB flush */
#define PG_AVAIL1 0x00000200 /* ignored by hardware */
#define PG_AVAIL2 0x00000400 /* ignored by hardware */
#define PG_AVAIL3 0x00000800 /* ignored by hardware */
#define PG_LGPAT 0x00001000 /* PAT on large pages */
#define PG_KW 0x00000002 /* kernel read-write */
#ifdef PAE
#define PG_NX 0x8000000000000000ULL /* No-execute */
#else
#define PG_NX 0 /* dummy */
#endif
/* XXX To be deleted. */
#define PG_V PTE_P
#define PG_RW PTE_W
#define PG_u PTE_U
#define PG_WT PTE_PWT
#define PG_N PTE_PCD
#define PG_U PTE_A
#define PG_M PTE_D
#define PG_PAT PTE_PAT
#define PG_PS PTE_PS
#define PG_G PTE_G
#define PG_AVAIL1 PTE_AVL1
#define PG_AVAIL2 PTE_AVL2
#define PG_AVAIL3 PTE_AVL3
#define PG_LGPAT PTE_LGPAT
#define PG_KW PTE_W
#define PG_NX PTE_NX
#include <x86/pte.h>

12
sys/arch/usermode/usermode/db_memrw.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_memrw.c,v 1.4 2018/08/05 18:57:49 reinoud Exp $ */
/* $NetBSD: db_memrw.c,v 1.5 2019/03/09 08:42:26 maxv Exp $ */
/*-
* Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_memrw.c,v 1.4 2018/08/05 18:57:49 reinoud Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_memrw.c,v 1.5 2019/03/09 08:42:26 maxv Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@ -152,7 +152,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
ppte = kvtopte(addr);
pte = *ppte;
if ((pte & PG_V) == 0) {
if ((pte & PTE_P) == 0) {
printf(" address %p not a valid page\n", dst);
return;
}
@ -173,8 +173,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
/*
* Make the kernel text page writable.
*/
pmap_pte_clearbits(ppte, PG_KR);
pmap_pte_setbits(ppte, PG_KW);
pmap_pte_setbits(ppte, PTE_W);
pmap_update_pg(addr);
/*
@ -192,8 +191,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
/*
* Turn the page back to read-only.
*/
pmap_pte_clearbits(ppte, PG_KW);
pmap_pte_setbits(ppte, PG_KR);
pmap_pte_clearbits(ppte, PTE_W);
pmap_update_pg(addr);
/*

8
sys/arch/x86/acpi/acpi_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: acpi_machdep.c,v 1.23 2019/03/03 17:33:33 maxv Exp $ */
/* $NetBSD: acpi_machdep.c,v 1.24 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: acpi_machdep.c,v 1.23 2019/03/03 17:33:33 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: acpi_machdep.c,v 1.24 2019/03/09 08:42:25 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -326,7 +326,7 @@ acpi_md_OsReadable(void *Pointer, uint32_t Length)
for (; sva < eva; sva += PAGE_SIZE) {
pte = kvtopte(sva);
if ((*pte & PG_V) == 0) {
if ((*pte & PTE_P) == 0) {
rv = FALSE;
break;
}
@ -350,7 +350,7 @@ acpi_md_OsWritable(void *Pointer, uint32_t Length)
for (; sva < eva; sva += PAGE_SIZE) {
pte = kvtopte(sva);
if ((*pte & (PG_V|PG_RW)) != (PG_V|PG_RW)) {
if ((*pte & (PTE_P|PTE_W)) != (PTE_P|PTE_W)) {
rv = FALSE;
break;
}

4
sys/arch/x86/include/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.98 2019/02/23 10:59:12 maxv Exp $ */
/* $NetBSD: pmap.h,v 1.99 2019/03/09 08:42:26 maxv Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@ -331,7 +331,7 @@ extern long nkptp[PTP_LEVELS];
#define pmap_move(DP,SP,D,L,S)
#define pmap_phys_address(ppn) (x86_ptob(ppn) & ~X86_MMAP_FLAG_MASK)
#define pmap_mmap_flags(ppn) x86_mmap_flags(ppn)
#define pmap_valid_entry(E) ((E) & PG_V) /* is PDE or PTE valid? */
#define pmap_valid_entry(E) ((E) & PTE_P) /* is PDE or PTE valid? */
#if defined(__x86_64__) || defined(PAE)
#define X86_MMAP_FLAG_SHIFT (64 - PGSHIFT)

8
sys/arch/x86/include/pmap_pv.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap_pv.h,v 1.4 2019/02/01 05:44:29 maxv Exp $ */
/* $NetBSD: pmap_pv.h,v 1.5 2019/03/09 08:42:26 maxv Exp $ */
/*-
* Copyright (c)2008 YAMAMOTO Takashi,
@ -82,9 +82,9 @@ struct pmap_page {
#define pp_link pp_u.u_link
uint8_t pp_flags;
uint8_t pp_attrs;
#define PP_ATTRS_M 0x01 /* saved PG_M */
#define PP_ATTRS_U 0x02 /* saved PG_U */
#define PP_ATTRS_W 0x04 /* saved PG_RW */
#define PP_ATTRS_M 0x01 /* Dirty */
#define PP_ATTRS_U 0x02 /* Accessed */
#define PP_ATTRS_W 0x04 /* Writable */
};
/* pp_flags */

4
sys/arch/x86/include/specialreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: specialreg.h,v 1.141 2019/02/16 12:05:30 maxv Exp $ */
/* $NetBSD: specialreg.h,v 1.142 2019/03/09 08:42:26 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@ -45,7 +45,7 @@
* Bits in 486 special registers:
*/
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
#define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
#define CR0_NW 0x20000000 /* Not Write-through */
#define CR0_CD 0x40000000 /* Cache Disable */

8
sys/arch/x86/x86/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.167 2019/02/15 08:54:01 nonaka Exp $ */
/* $NetBSD: cpu.c,v 1.168 2019/03/09 08:42:26 maxv Exp $ */
/*
* Copyright (c) 2000-2012 NetBSD Foundation, Inc.
@ -62,7 +62,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.167 2019/02/15 08:54:01 nonaka Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.168 2019/03/09 08:42:26 maxv Exp $");
#include "opt_ddb.h"
#include "opt_mpbios.h" /* for MPDEBUG */
@ -919,7 +919,7 @@ cpu_hatch(void *v)
#ifdef PAE
pd_entry_t * l3_pd = ci->ci_pae_l3_pdir;
for (i = 0 ; i < PDP_SIZE; i++) {
l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PG_V;
l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PTE_P;
}
lcr3(ci->ci_pae_l3_pdirpa);
#else
@ -1321,7 +1321,7 @@ cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap)
x86_disable_intr();
for (i = 0 ; i < PDP_SIZE; i++) {
l3_pd[i] = pmap->pm_pdirpa[i] | PG_V;
l3_pd[i] = pmap->pm_pdirpa[i] | PTE_P;
}
if (interrupts_enabled)

10
sys/arch/x86/x86/db_memrw.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: db_memrw.c,v 1.9 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: db_memrw.c,v 1.10 2019/03/09 08:42:26 maxv Exp $ */
/*-
* Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: db_memrw.c,v 1.9 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: db_memrw.c,v 1.10 2019/03/09 08:42:26 maxv Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@ -147,7 +147,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
ppte = kvtopte(addr);
pte = *ppte;
if ((pte & PG_V) == 0) {
if ((pte & PTE_P) == 0) {
#ifdef DDB
db_printf(" address %p not a valid page\n", dst);
#endif
@ -170,7 +170,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
/*
* Make the kernel text page writable.
*/
pmap_pte_setbits(ppte, PG_KW);
pmap_pte_setbits(ppte, PTE_W);
pmap_update_pg(addr);
/*
@ -188,7 +188,7 @@ db_write_text(vaddr_t addr, size_t size, const char *data)
/*
* Turn the page back to read-only.
*/
pmap_pte_clearbits(ppte, PG_KW);
pmap_pte_clearbits(ppte, PTE_W);
pmap_update_pg(addr);
/*

6
sys/arch/x86/x86/kgdb_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: kgdb_machdep.c,v 1.3 2017/09/17 09:41:35 maxv Exp $ */
/* $NetBSD: kgdb_machdep.c,v 1.4 2019/03/09 08:42:26 maxv Exp $ */
/*
* Copyright (c) 1997, 2017 The NetBSD Foundation, Inc.
@ -56,7 +56,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: kgdb_machdep.c,v 1.3 2017/09/17 09:41:35 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: kgdb_machdep.c,v 1.4 2019/03/09 08:42:26 maxv Exp $");
#include "opt_ddb.h"
@ -91,7 +91,7 @@ kgdb_acc(vaddr_t va, size_t len)
pte = vtopte(va);
else
pte = kvtopte(va);
if ((*pte & PG_V) == 0)
if ((*pte & PTE_P) == 0)
return 0;
if (*pte & PG_PS)
va = (va & PG_LGFRAME) + NBPD_L2;

6
sys/arch/x86/x86/lapic.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: lapic.c,v 1.70 2019/02/17 05:06:16 nonaka Exp $ */
/* $NetBSD: lapic.c,v 1.71 2019/03/09 08:42:26 maxv Exp $ */
/*-
* Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.70 2019/02/17 05:06:16 nonaka Exp $");
__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.71 2019/03/09 08:42:26 maxv Exp $");
#include "acpica.h"
#include "ioapic.h"
@ -387,7 +387,7 @@ lapic_map(paddr_t lapic_base)
*/
pte = kvtopte(va);
*pte = lapic_base | PG_RW | PG_V | PG_N | pmap_pg_g | pmap_pg_nx;
*pte = lapic_base | PTE_W | PTE_P | PTE_PCD | pmap_pg_g | pmap_pg_nx;
invlpg(va);
#ifdef MULTIPROCESSOR

226
sys/arch/x86/x86/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.328 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: pmap.c,v 1.329 2019/03/09 08:42:26 maxv Exp $ */
/*
* Copyright (c) 2008, 2010, 2016, 2017 The NetBSD Foundation, Inc.
@ -130,7 +130,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.328 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.329 2019/03/09 08:42:26 maxv Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@ -511,11 +511,11 @@ pmap_stats_update(struct pmap *pmap, int resid_diff, int wired_diff)
static inline void
pmap_stats_update_bypte(struct pmap *pmap, pt_entry_t npte, pt_entry_t opte)
{
int resid_diff = ((npte & PG_V) ? 1 : 0) - ((opte & PG_V) ? 1 : 0);
int resid_diff = ((npte & PTE_P) ? 1 : 0) - ((opte & PTE_P) ? 1 : 0);
int wired_diff = ((npte & PG_W) ? 1 : 0) - ((opte & PG_W) ? 1 : 0);
KASSERT((npte & (PG_V | PG_W)) != PG_W);
KASSERT((opte & (PG_V | PG_W)) != PG_W);
KASSERT((npte & (PTE_P | PG_W)) != PG_W);
KASSERT((opte & (PTE_P | PG_W)) != PG_W);
pmap_stats_update(pmap, resid_diff, wired_diff);
}
@ -833,7 +833,7 @@ pmap_pat_flags(u_int flags)
/* results in PGC_UCMINUS on cpus which have
* the cpuid PAT but PAT "disabled"
*/
return PG_N;
return PTE_PCD;
default:
return 0;
}
@ -888,7 +888,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
} else
#endif /* DOM0OPS */
npte = pmap_pa2pte(pa);
npte |= protection_codes[prot] | PG_V | pmap_pg_g;
npte |= protection_codes[prot] | PTE_P | pmap_pg_g;
npte |= pmap_pat_flags(flags);
opte = pmap_pte_testset(pte, npte); /* zap! */
@ -897,9 +897,9 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
* large pages created are for the kernel image, and they should never
* be kentered.
*/
KASSERTMSG(!(opte & PG_PS), "PG_PS va=%#"PRIxVADDR, va);
KASSERTMSG(!(opte & PTE_PS), "PTE_PS va=%#"PRIxVADDR, va);
if ((opte & (PG_V | PG_U)) == (PG_V | PG_U)) {
if ((opte & (PTE_P | PTE_A)) == (PTE_P | PTE_A)) {
/* This should not happen. */
printf_nolog("%s: mapping already present\n", __func__);
kpreempt_disable();
@ -932,9 +932,9 @@ pmap_changeprot_local(vaddr_t va, vm_prot_t prot)
npte = opte = *pte;
if ((prot & VM_PROT_WRITE) != 0)
npte |= PG_RW;
npte |= PTE_W;
else
npte &= ~PG_RW;
npte &= ~PTE_W;
if (opte != npte) {
pmap_pte_set(pte, npte);
@ -967,11 +967,11 @@ pmap_kremove1(vaddr_t sva, vsize_t len, bool localonly)
for (va = sva; va < eva; va += PAGE_SIZE) {
pte = kvtopte(va);
opte = pmap_pte_testset(pte, 0); /* zap! */
if ((opte & (PG_V | PG_U)) == (PG_V | PG_U) && !localonly) {
if ((opte & (PTE_P | PTE_A)) == (PTE_P | PTE_A) && !localonly) {
pmap_tlb_shootdown(pmap_kernel(), va, opte,
TLBSHOOT_KREMOVE);
}
KASSERTMSG((opte & PG_PS) == 0,
KASSERTMSG((opte & PTE_PS) == 0,
"va %#" PRIxVADDR " is a large page", va);
KASSERTMSG((opte & PG_PVLIST) == 0,
"va %#" PRIxVADDR " is a pv tracked page", va);
@ -1053,7 +1053,7 @@ pmap_bootstrap(vaddr_t kva_start)
int i;
vaddr_t kva;
pmap_pg_nx = (cpu_feature[2] & CPUID_NOX ? PG_NX : 0);
pmap_pg_nx = (cpu_feature[2] & CPUID_NOX ? PTE_NX : 0);
/*
* Set up our local static global vars that keep track of the usage of
@ -1071,10 +1071,10 @@ pmap_bootstrap(vaddr_t kva_start)
protection_codes[VM_PROT_EXECUTE] = PG_X;
protection_codes[VM_PROT_READ] = pmap_pg_nx;
protection_codes[VM_PROT_READ|VM_PROT_EXECUTE] = PG_X;
protection_codes[VM_PROT_WRITE] = PG_RW | pmap_pg_nx;
protection_codes[VM_PROT_WRITE|VM_PROT_EXECUTE] = PG_RW | PG_X;
protection_codes[VM_PROT_WRITE|VM_PROT_READ] = PG_RW | pmap_pg_nx;
protection_codes[VM_PROT_ALL] = PG_RW | PG_X;
protection_codes[VM_PROT_WRITE] = PTE_W | pmap_pg_nx;
protection_codes[VM_PROT_WRITE|VM_PROT_EXECUTE] = PTE_W | PG_X;
protection_codes[VM_PROT_WRITE|VM_PROT_READ] = PTE_W | pmap_pg_nx;
protection_codes[VM_PROT_ALL] = PTE_W | PG_X;
/*
* Now we init the kernel's pmap.
@ -1122,9 +1122,9 @@ pmap_bootstrap(vaddr_t kva_start)
* (and happens later)
*/
if (cpu_feature[0] & CPUID_PGE) {
pmap_pg_g = PG_G; /* enable software */
pmap_pg_g = PTE_G; /* enable software */
/* add PG_G attribute to already mapped kernel pages */
/* add PTE_G attribute to already mapped kernel pages */
pmap_remap_global();
}
#endif
@ -1194,7 +1194,7 @@ pmap_bootstrap(vaddr_t kva_start)
memset((void *)(xen_dummy_user_pgd + KERNBASE), 0, PAGE_SIZE);
/* Mark read-only */
HYPERVISOR_update_va_mapping(xen_dummy_user_pgd + KERNBASE,
pmap_pa2pte(xen_dummy_user_pgd) | PG_V | pmap_pg_nx,
pmap_pa2pte(xen_dummy_user_pgd) | PTE_P | pmap_pg_nx,
UVMF_INVLPG);
/* Pin as L4 */
xpq_queue_pin_l4_table(xpmap_ptom_masked(xen_dummy_user_pgd));
@ -1406,7 +1406,7 @@ pmap_init_pcpu(void)
size_t size;
int i;
const pd_entry_t pteflags = PG_V | PG_KW | pmap_pg_nx;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
size = sizeof(struct pcpu_area);
@ -1424,11 +1424,11 @@ pmap_init_pcpu(void)
KASSERT(L4_BASE[L4e_idx+i] == 0);
pa = pmap_bootstrap_palloc(1);
*pte = (pa & PG_FRAME) | pteflags;
*pte = (pa & PTE_FRAME) | pteflags;
pmap_update_pg(tmpva);
memset((void *)tmpva, 0, PAGE_SIZE);
L4_BASE[L4e_idx+i] = pa | pteflags | PG_U;
L4_BASE[L4e_idx+i] = pa | pteflags | PTE_A;
}
/* Build L3 */
@ -1438,11 +1438,11 @@ pmap_init_pcpu(void)
KASSERT(L3_BASE[L3e_idx+i] == 0);
pa = pmap_bootstrap_palloc(1);
*pte = (pa & PG_FRAME) | pteflags;
*pte = (pa & PTE_FRAME) | pteflags;
pmap_update_pg(tmpva);
memset((void *)tmpva, 0, PAGE_SIZE);
L3_BASE[L3e_idx+i] = pa | pteflags | PG_U;
L3_BASE[L3e_idx+i] = pa | pteflags | PTE_A;
}
/* Build L2 */
@ -1453,11 +1453,11 @@ pmap_init_pcpu(void)
KASSERT(L2_BASE[L2e_idx+i] == 0);
pa = pmap_bootstrap_palloc(1);
*pte = (pa & PG_FRAME) | pteflags;
*pte = (pa & PTE_FRAME) | pteflags;
pmap_update_pg(tmpva);
memset((void *)tmpva, 0, PAGE_SIZE);
L2_BASE[L2e_idx+i] = pa | pteflags | PG_U;
L2_BASE[L2e_idx+i] = pa | pteflags | PTE_A;
}
/* Build L1 */
@ -1503,8 +1503,8 @@ pmap_init_directmap(struct pmap *kpm)
phys_ram_seg_t *mc;
int i;
const pd_entry_t pteflags = PG_V | PG_KW | pmap_pg_nx;
const pd_entry_t holepteflags = PG_V | pmap_pg_nx;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
const pd_entry_t holepteflags = PTE_P | pmap_pg_nx;
CTASSERT(NL4_SLOT_DIRECT * NBPD_L4 == MAXPHYSMEM);
@ -1540,11 +1540,11 @@ pmap_init_directmap(struct pmap *kpm)
KASSERT(L4_BASE[L4e_idx+i] == 0);
pa = pmap_bootstrap_palloc(1);
*pte = (pa & PG_FRAME) | pteflags;
*pte = (pa & PTE_FRAME) | pteflags;
pmap_update_pg(tmpva);
memset((void *)tmpva, 0, PAGE_SIZE);
L4_BASE[L4e_idx+i] = pa | pteflags | PG_U;
L4_BASE[L4e_idx+i] = pa | pteflags | PTE_A;
}
/* Build L3 */
@ -1554,11 +1554,11 @@ pmap_init_directmap(struct pmap *kpm)
KASSERT(L3_BASE[L3e_idx+i] == 0);
pa = pmap_bootstrap_palloc(1);
*pte = (pa & PG_FRAME) | pteflags;
*pte = (pa & PTE_FRAME) | pteflags;
pmap_update_pg(tmpva);
memset((void *)tmpva, 0, PAGE_SIZE);
L3_BASE[L3e_idx+i] = pa | pteflags | PG_U;
L3_BASE[L3e_idx+i] = pa | pteflags | PTE_A;
}
/* Build L2 */
@ -1570,11 +1570,11 @@ pmap_init_directmap(struct pmap *kpm)
pa = (paddr_t)(i * NBPD_L2);
if (spahole <= pa && pa < epahole) {
L2_BASE[L2e_idx+i] = pa | holepteflags | PG_U |
PG_PS | pmap_pg_g;
L2_BASE[L2e_idx+i] = pa | holepteflags | PTE_A |
PTE_PS | pmap_pg_g;
} else {
L2_BASE[L2e_idx+i] = pa | pteflags | PG_U |
PG_PS | pmap_pg_g;
L2_BASE[L2e_idx+i] = pa | pteflags | PTE_A |
PTE_PS | pmap_pg_g;
}
}
@ -1590,7 +1590,7 @@ pmap_init_directmap(struct pmap *kpm)
#if !defined(XENPV)
/*
* Remap all of the virtual pages created so far with the PG_G bit.
* Remap all of the virtual pages created so far with the PTE_G bit.
*/
static void
pmap_remap_global(void)
@ -1660,7 +1660,7 @@ pmap_remap_largepages(void)
pa = roundup(bootspace.segs[i].pa, NBPD_L2);
for (/* */; kva < kva_end; kva += NBPD_L2, pa += NBPD_L2) {
pde = &L2_BASE[pl2_i(kva)];
*pde = pa | pmap_pg_g | PG_PS | PG_V;
*pde = pa | pmap_pg_g | PTE_PS | PTE_P;
tlbflushg();
}
}
@ -1679,7 +1679,7 @@ pmap_remap_largepages(void)
pa = roundup(bootspace.segs[i].pa, NBPD_L2);
for (/* */; kva < kva_end; kva += NBPD_L2, pa += NBPD_L2) {
pde = &L2_BASE[pl2_i(kva)];
*pde = pa | pmap_pg_g | PG_PS | pmap_pg_nx | PG_V;
*pde = pa | pmap_pg_g | PTE_PS | pmap_pg_nx | PTE_P;
tlbflushg();
}
}
@ -1698,7 +1698,7 @@ pmap_remap_largepages(void)
pa = roundup(bootspace.segs[i].pa, NBPD_L2);
for (/* */; kva < kva_end; kva += NBPD_L2, pa += NBPD_L2) {
pde = &L2_BASE[pl2_i(kva)];
*pde = pa | pmap_pg_g | PG_PS | pmap_pg_nx | PG_KW | PG_V;
*pde = pa | pmap_pg_g | PTE_PS | pmap_pg_nx | PTE_W | PTE_P;
tlbflushg();
}
}
@ -2147,7 +2147,7 @@ pmap_get_ptp(struct pmap *pmap, vaddr_t va, pd_entry_t * const *pdes, int flags)
pmap->pm_ptphint[i - 2] = ptp;
pa = VM_PAGE_TO_PHYS(ptp);
pmap_pte_set(&pva[index], (pd_entry_t)
(pmap_pa2pte(pa) | PG_u | PG_RW | PG_V));
(pmap_pa2pte(pa) | PTE_U | PTE_W | PTE_P));
/*
* On Xen-amd64 or SVS, we need to sync the top level page
@ -2241,10 +2241,10 @@ pmap_pdp_ctor(void *arg, void *v, int flags)
* don't put kernel mappings on Xen.
*
* But we need to make pmap_create() happy, so put a dummy
* (without PG_V) value at the right place.
* (without PTE_P) value at the right place.
*/
pdir[PDIR_SLOT_KERN + nkptp[PTP_LEVELS - 1] - 1] =
(pd_entry_t)-1 & PG_FRAME;
(pd_entry_t)-1 & PTE_FRAME;
#else /* XENPV && __x86_64__*/
object = (vaddr_t)v;
for (i = 0; i < PDP_SIZE; i++, object += PAGE_SIZE) {
@ -2252,10 +2252,10 @@ pmap_pdp_ctor(void *arg, void *v, int flags)
(void)pmap_extract(pmap_kernel(), object, &pdirpa);
/* Put in recursive PDE to map the PTEs */
pdir[PDIR_SLOT_PTE + i] = pmap_pa2pte(pdirpa) | PG_V |
pdir[PDIR_SLOT_PTE + i] = pmap_pa2pte(pdirpa) | PTE_P |
pmap_pg_nx;
#ifndef XENPV
pdir[PDIR_SLOT_PTE + i] |= PG_KW;
pdir[PDIR_SLOT_PTE + i] |= PTE_W;
#endif
}
@ -2338,7 +2338,7 @@ pmap_pdp_dtor(void *arg, void *v)
for (i = 0; i < PDP_SIZE; i++, object += PAGE_SIZE) {
/* Set page RW again */
pte = kvtopte(object);
pmap_pte_set(pte, *pte | PG_RW);
pmap_pte_set(pte, *pte | PTE_W);
xen_bcast_invlpg((vaddr_t)object);
}
splx(s);
@ -3041,7 +3041,7 @@ pmap_pdes_invalid(vaddr_t va, pd_entry_t * const *pdes, pd_entry_t *lastpde)
for (i = PTP_LEVELS; i > 1; i--) {
index = pl_i(va, i);
pde = pdes[i - 2][index];
if ((pde & PG_V) == 0)
if ((pde & PTE_P) == 0)
return i;
}
if (lastpde != NULL)
@ -3103,10 +3103,10 @@ pmap_extract(struct pmap *pmap, vaddr_t va, paddr_t *pap)
}
if (pmap_pdes_valid(va, pdes, &pde)) {
pte = ptes[pl1_i(va)];
if (pde & PG_PS) {
pa = (pde & PG_LGFRAME) | (va & (NBPD_L2 - 1));
if (pde & PTE_PS) {
pa = (pde & PTE_LGFRAME) | (va & (NBPD_L2 - 1));
rv = true;
} else if (__predict_true((pte & PG_V) != 0)) {
} else if (__predict_true((pte & PTE_P) != 0)) {
pa = pmap_pte2pa(pte) | (va & (NBPD_L1 - 1));
rv = true;
}
@ -3178,7 +3178,7 @@ pmap_zero_page(paddr_t pa)
pt_entry_t *zpte;
vaddr_t zerova;
const pd_entry_t pteflags = PG_V | PG_RW | pmap_pg_nx | PG_M | PG_U;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_D | PTE_A;
kpreempt_disable();
@ -3220,7 +3220,7 @@ pmap_pageidlezero(paddr_t pa)
vaddr_t zerova;
bool rv;
const pd_entry_t pteflags = PG_V | PG_RW | pmap_pg_nx | PG_M | PG_U;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_D | PTE_A;
ci = curcpu();
zerova = ci->vpage[VPAGE_ZER];
@ -3263,7 +3263,7 @@ pmap_copy_page(paddr_t srcpa, paddr_t dstpa)
pt_entry_t *srcpte, *dstpte;
vaddr_t srcva, dstva;
const pd_entry_t pteflags = PG_V | PG_RW | pmap_pg_nx | PG_U;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A;
kpreempt_disable();
@ -3276,7 +3276,7 @@ pmap_copy_page(paddr_t srcpa, paddr_t dstpa)
KASSERT(*srcpte == 0 && *dstpte == 0);
pmap_pte_set(srcpte, pmap_pa2pte(srcpa) | pteflags);
pmap_pte_set(dstpte, pmap_pa2pte(dstpa) | pteflags | PG_M);
pmap_pte_set(dstpte, pmap_pa2pte(dstpa) | pteflags | PTE_D);
pmap_pte_flush();
pmap_update_pg(srcva);
pmap_update_pg(dstva);
@ -3306,9 +3306,9 @@ pmap_map_ptp(struct vm_page *ptp)
KASSERT(kpreempt_disabled());
#ifndef XENPV
const pd_entry_t pteflags = PG_V | PG_RW | pmap_pg_nx | PG_U | PG_M;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A | PTE_D;
#else
const pd_entry_t pteflags = PG_V | pmap_pg_nx | PG_U | PG_M;
const pd_entry_t pteflags = PTE_P | pmap_pg_nx | PTE_A | PTE_D;
#endif
ci = curcpu();
@ -3409,11 +3409,11 @@ static inline uint8_t
pmap_pte_to_pp_attrs(pt_entry_t pte)
{
uint8_t ret = 0;
if (pte & PG_M)
if (pte & PTE_D)
ret |= PP_ATTRS_M;
if (pte & PG_U)
if (pte & PTE_A)
ret |= PP_ATTRS_U;
if (pte & PG_RW)
if (pte & PTE_W)
ret |= PP_ATTRS_W;
return ret;
}
@ -3423,11 +3423,11 @@ pmap_pp_attrs_to_pte(uint8_t attrs)
{
pt_entry_t pte = 0;
if (attrs & PP_ATTRS_M)
pte |= PG_M;
pte |= PTE_D;
if (attrs & PP_ATTRS_U)
pte |= PG_U;
pte |= PTE_A;
if (attrs & PP_ATTRS_W)
pte |= PG_RW;
pte |= PTE_W;
return pte;
}
@ -3472,11 +3472,11 @@ pmap_remove_pte(struct pmap *pmap, struct vm_page *ptp, pt_entry_t *pte,
*/
ptp->wire_count--;
if (ptp->wire_count <= 1) {
opte |= PG_U;
opte |= PTE_A;
}
}
if ((opte & PG_U) != 0) {
if ((opte & PTE_A) != 0) {
pmap_tlb_shootdown(pmap, va, opte, TLBSHOOT_REMOVE_PTE);
}
@ -3647,7 +3647,7 @@ pmap_sync_pv(struct pv_pte *pvpte, paddr_t pa, int clearbits, uint8_t *oattrs,
optep);
}
expect = pmap_pa2pte(pa) | PG_V;
expect = pmap_pa2pte(pa) | PTE_P;
if (clearbits != ~0) {
KASSERT((clearbits & ~(PP_ATTRS_M|PP_ATTRS_U|PP_ATTRS_W)) == 0);
@ -3657,10 +3657,10 @@ pmap_sync_pv(struct pv_pte *pvpte, paddr_t pa, int clearbits, uint8_t *oattrs,
ptep = pmap_map_pte(pmap, ptp, va);
do {
opte = *ptep;
KASSERT((opte & (PG_M | PG_U)) != PG_M);
KASSERT((opte & (PG_U | PG_V)) != PG_U);
KASSERT(opte == 0 || (opte & PG_V) != 0);
if ((opte & (PG_FRAME | PG_V)) != expect) {
KASSERT((opte & (PTE_D | PTE_A)) != PTE_D);
KASSERT((opte & (PTE_A | PTE_P)) != PTE_A);
KASSERT(opte == 0 || (opte & PTE_P) != 0);
if ((opte & (PTE_FRAME | PTE_P)) != expect) {
/*
* We lost a race with a V->P operation like
* pmap_remove(). Wait for the competitor
@ -3672,7 +3672,7 @@ pmap_sync_pv(struct pv_pte *pvpte, paddr_t pa, int clearbits, uint8_t *oattrs,
pmap_unmap_pte();
if (clearbits != 0) {
pmap_tlb_shootdown(pmap, va,
(pmap == pmap_kernel() ? PG_G : 0),
(pmap == pmap_kernel() ? PTE_G : 0),
TLBSHOOT_SYNC_PV1);
}
return EAGAIN;
@ -3687,24 +3687,24 @@ pmap_sync_pv(struct pv_pte *pvpte, paddr_t pa, int clearbits, uint8_t *oattrs,
}
/*
* We need a shootdown if the PTE is cached (PG_U) ...
* ... Unless we are clearing only the PG_RW bit and
* it isn't cached as RW (PG_M).
* We need a shootdown if the PTE is cached (PTE_A) ...
* ... Unless we are clearing only the PTE_W bit and
* it isn't cached as RW (PTE_D).
*/
need_shootdown = (opte & PG_U) != 0 &&
!(clearbits == PG_RW && (opte & PG_M) == 0);
need_shootdown = (opte & PTE_A) != 0 &&
!(clearbits == PTE_W && (opte & PTE_D) == 0);
npte = opte & ~clearbits;
/*
* If we need a shootdown anyway, clear PG_U and PG_M.
* If we need a shootdown anyway, clear PTE_A and PTE_D.
*/
if (need_shootdown) {
npte &= ~(PG_U | PG_M);
npte &= ~(PTE_A | PTE_D);
}
KASSERT((npte & (PG_M | PG_U)) != PG_M);
KASSERT((npte & (PG_U | PG_V)) != PG_U);
KASSERT(npte == 0 || (opte & PG_V) != 0);
KASSERT((npte & (PTE_D | PTE_A)) != PTE_D);
KASSERT((npte & (PTE_A | PTE_P)) != PTE_A);
KASSERT(npte == 0 || (opte & PTE_P) != 0);
} while (pmap_pte_cas(ptep, opte, npte) != opte);
if (need_shootdown) {
@ -3989,9 +3989,9 @@ pmap_pv_clear_attrs(paddr_t pa, unsigned clearbits)
/*
* pmap_write_protect: write-protect pages in a pmap.
*
* Note for Xen-amd64. Xen automatically adds PG_u to the kernel pages, but we
* Note for Xen-amd64. Xen automatically adds PTE_U to the kernel pages, but we
* don't need to remove this bit when re-entering the PTEs here: Xen tracks the
* kernel pages with a reserved bit (_PAGE_GUEST_KERNEL), so even if PG_u is
* kernel pages with a reserved bit (_PAGE_GUEST_KERNEL), so even if PTE_U is
* present the page will still be considered as a kernel page, and the privilege
* separation will be enforced correctly.
*/
@ -4013,14 +4013,14 @@ pmap_write_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
bit_rem = 0;
if (!(prot & VM_PROT_WRITE))
bit_rem = PG_RW;
bit_rem = PTE_W;
bit_put = 0;
if (!(prot & VM_PROT_EXECUTE))
bit_put = pmap_pg_nx;
sva &= PG_FRAME;
eva &= PG_FRAME;
sva &= PTE_FRAME;
eva &= PTE_FRAME;
/* Acquire pmap. */
kpreempt_disable();
@ -4053,7 +4053,7 @@ pmap_write_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
npte = (opte & ~bit_rem) | bit_put;
} while (pmap_pte_cas(spte, opte, npte) != opte);
if ((opte & PG_M) != 0) {
if ((opte & PTE_D) != 0) {
vaddr_t tva = x86_ptob(spte - ptes);
pmap_tlb_shootdown(pmap, tva, opte,
TLBSHOOT_WRITE_PROTECT);
@ -4171,20 +4171,20 @@ pmap_enter_ma(struct pmap *pmap, vaddr_t va, paddr_t ma, paddr_t pa,
KASSERT(domid == DOMID_SELF || pa == 0);
#endif
npte = ma | protection_codes[prot] | PG_V;
npte = ma | protection_codes[prot] | PTE_P;
npte |= pmap_pat_flags(flags);
if (wired)
npte |= PG_W;
if (va < VM_MAXUSER_ADDRESS)
npte |= PG_u;
npte |= PTE_U;
if (pmap == pmap_kernel())
npte |= pmap_pg_g;
if (flags & VM_PROT_ALL) {
npte |= PG_U;
npte |= PTE_A;
if (flags & VM_PROT_WRITE) {
KASSERT((npte & PG_RW) != 0);
npte |= PG_M;
KASSERT((npte & PTE_W) != 0);
npte |= PTE_D;
}
}
@ -4265,10 +4265,10 @@ pmap_enter_ma(struct pmap *pmap, vaddr_t va, paddr_t ma, paddr_t pa,
opte = *ptep;
/*
* if the same page, inherit PG_U and PG_M.
* if the same page, inherit PTE_A and PTE_D.
*/
if (((opte ^ npte) & (PG_FRAME | PG_V)) == 0) {
npte |= opte & (PG_U | PG_M);
if (((opte ^ npte) & (PTE_FRAME | PTE_P)) == 0) {
npte |= opte & (PTE_A | PTE_D);
}
#if defined(XENPV)
if (domid != DOMID_SELF) {
@ -4305,7 +4305,7 @@ pmap_enter_ma(struct pmap *pmap, vaddr_t va, paddr_t ma, paddr_t pa,
/*
* If the same page, we can skip pv_entry handling.
*/
if (((opte ^ npte) & (PG_FRAME | PG_V)) == 0) {
if (((opte ^ npte) & (PTE_FRAME | PTE_P)) == 0) {
KASSERT(((opte ^ npte) & PG_PVLIST) == 0);
goto same_pa;
}
@ -4313,7 +4313,7 @@ pmap_enter_ma(struct pmap *pmap, vaddr_t va, paddr_t ma, paddr_t pa,
/*
* If old page is pv-tracked, remove pv_entry from its list.
*/
if ((~opte & (PG_V | PG_PVLIST)) == 0) {
if ((~opte & (PTE_P | PG_PVLIST)) == 0) {
if ((old_pg = PHYS_TO_VM_PAGE(oldpa)) != NULL) {
KASSERT(uvm_page_locked_p(old_pg));
old_pp = VM_PAGE_TO_PP(old_pg);
@ -4342,8 +4342,8 @@ same_pa:
* shootdown tlb if necessary.
*/
if ((~opte & (PG_V | PG_U)) == 0 &&
((opte ^ npte) & (PG_FRAME | PG_RW)) != 0) {
if ((~opte & (PTE_P | PTE_A)) == 0 &&
((opte ^ npte) & (PTE_FRAME | PTE_W)) != 0) {
pmap_tlb_shootdown(pmap, va, opte, TLBSHOOT_ENTER);
}
@ -4389,8 +4389,8 @@ pmap_get_physpage(void)
}
#endif
kpreempt_disable();
pmap_pte_set(early_zero_pte, pmap_pa2pte(pa) | PG_V |
PG_RW | pmap_pg_nx);
pmap_pte_set(early_zero_pte, pmap_pa2pte(pa) | PTE_P |
PTE_W | pmap_pg_nx);
pmap_pte_flush();
pmap_update_pg((vaddr_t)early_zerop);
memset(early_zerop, 0, PAGE_SIZE);
@ -4448,7 +4448,7 @@ pmap_alloc_level(struct pmap *cpm, vaddr_t kva, long *needed_ptps)
KASSERT(!pmap_valid_entry(pdep[i]));
pa = pmap_get_physpage();
pte = pmap_pa2pte(pa) | PG_V | PG_RW;
pte = pmap_pa2pte(pa) | PTE_P | PTE_W;
pmap_pte_set(&pdep[i], pte);
#ifdef XENPV
@ -4765,21 +4765,21 @@ pmap_init_tmp_pgtbl(paddr_t pg)
* 510: unused
* 511: maps 3->4GB (kernel)
*/
tmp_pml[508] = x86_tmp_pml_paddr[PTP_LEVELS - 1] | PG_V;
tmp_pml[508] = x86_tmp_pml_paddr[PTP_LEVELS - 1] | PTE_P;
tmp_pml[509] = 0;
tmp_pml[510] = 0;
tmp_pml[511] = pmap_pdirpa(pmap_kernel(), PDIR_SLOT_KERN) | PG_V;
tmp_pml[511] = pmap_pdirpa(pmap_kernel(), PDIR_SLOT_KERN) | PTE_P;
#endif
for (level = PTP_LEVELS - 1; level > 0; --level) {
tmp_pml = (void *)x86_tmp_pml_vaddr[level];
tmp_pml[pl_i(pg, level + 1)] =
(x86_tmp_pml_paddr[level - 1] & PG_FRAME) | PG_RW | PG_V;
(x86_tmp_pml_paddr[level - 1] & PTE_FRAME) | PTE_W | PTE_P;
}
tmp_pml = (void *)x86_tmp_pml_vaddr[0];
tmp_pml[pl_i(pg, 1)] = (pg & PG_FRAME) | PG_RW | PG_V;
tmp_pml[pl_i(pg, 1)] = (pg & PTE_FRAME) | PTE_W | PTE_P;
#ifdef PAE
/* Return the PA of the L3 page (entry 508 of the L2 page) */
@ -5185,9 +5185,9 @@ pmap_ept_enter(struct pmap *pmap, vaddr_t va, paddr_t pa, vm_prot_t prot,
opte = *ptep;
/*
* if the same page, inherit PG_U and PG_M.
* if the same page, inherit PTE_A and PTE_D.
*/
if (((opte ^ npte) & (PG_FRAME | PG_V)) == 0) {
if (((opte ^ npte) & (PG_FRAME | EPT_R)) == 0) {
npte |= opte & (EPT_A | EPT_D);
}
} while (pmap_pte_cas(ptep, opte, npte) != opte);
@ -5537,9 +5537,9 @@ pmap_ept_sync_pv(struct vm_page *ptp, vaddr_t va, paddr_t pa, int clearbits,
}
/*
* We need a shootdown if the PTE is cached (PG_U) ...
* ... Unless we are clearing only the PG_RW bit and
* it isn't cached as RW (PG_M).
* We need a shootdown if the PTE is cached (EPT_A) ...
* ... Unless we are clearing only the EPT_W bit and
* it isn't cached as RW (EPT_D).
*/
if (pmap_ept_has_ad) {
need_shootdown = (opte & EPT_A) != 0 &&
@ -5551,7 +5551,7 @@ pmap_ept_sync_pv(struct vm_page *ptp, vaddr_t va, paddr_t pa, int clearbits,
npte = opte & ~clearbits;
/*
* If we need a shootdown anyway, clear PG_U and PG_M.
* If we need a shootdown anyway, clear EPT_A and EPT_D.
*/
if (need_shootdown) {
npte &= ~(EPT_A | EPT_D);

8
sys/arch/x86/x86/svs.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: svs.c,v 1.22 2018/12/06 17:44:28 maxv Exp $ */
/* $NetBSD: svs.c,v 1.23 2019/03/09 08:42:26 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: svs.c,v 1.22 2018/12/06 17:44:28 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: svs.c,v 1.23 2019/03/09 08:42:26 maxv Exp $");
#include "opt_svs.h"
@ -256,7 +256,7 @@ svs_tree_add(struct cpu_info *ci, vaddr_t va)
__func__, cpu_index(ci));
pa = VM_PAGE_TO_PHYS(pg);
dstpde[pidx] = PG_V | PG_RW | pa;
dstpde[pidx] = PTE_P | PTE_W | pa;
}
pa = (paddr_t)(dstpde[pidx] & PG_FRAME);
@ -370,7 +370,7 @@ svs_utls_init(struct cpu_info *ci)
if (pmap_valid_entry(pd[pidx])) {
panic("%s: L1 page already mapped", __func__);
}
pd[pidx] = PG_V | PG_RW | pmap_pg_nx | pa;
pd[pidx] = PTE_P | PTE_W | pmap_pg_nx | pa;
/*
* Now, allocate a VA in the kernel map, that points to the UTLS

14
sys/arch/xen/x86/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.128 2019/02/02 12:32:55 cherry Exp $ */
/* $NetBSD: cpu.c,v 1.129 2019/03/09 08:42:25 maxv Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.128 2019/02/02 12:32:55 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.129 2019/03/09 08:42:25 maxv Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@ -797,7 +797,7 @@ gdt_prepframes(paddr_t *frames, vaddr_t base, uint32_t entries)
/* Mark Read-only */
pmap_pte_clearbits(kvtopte(base + (i << PAGE_SHIFT)),
PG_RW);
PTE_W);
}
}
@ -1151,7 +1151,7 @@ cpu_load_pmap(struct pmap *pmap, struct pmap *oldpmap)
/* don't update the kernel L3 slot */
for (i = 0; i < PDP_SIZE - 1; i++) {
xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t),
xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V);
xpmap_ptom(pmap->pm_pdirpa[i]) | PTE_P);
}
#endif
@ -1213,7 +1213,7 @@ pmap_cpu_init_late(struct cpu_info *ci)
/* Initialise L2 entries 0 - 2: Point them to pmap_kernel() */
for (i = 0; i < PDP_SIZE - 1; i++) {
ci->ci_pae_l3_pdir[i] =
xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PG_V;
xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PTE_P;
}
#endif
@ -1235,7 +1235,7 @@ pmap_cpu_init_late(struct cpu_info *ci)
/* Recursive kernel mapping */
ci->ci_kpm_pdir[PDIR_SLOT_PTE] = xpmap_ptom_masked(ci->ci_kpm_pdirpa)
| PG_V | xpmap_pg_nx;
| PTE_P | xpmap_pg_nx;
#else
/* Copy over the pmap_kernel() shadow L2 entries */
memcpy(ci->ci_kpm_pdir, pmap_kernel()->pm_pdir + PDIR_SLOT_KERN,
@ -1254,7 +1254,7 @@ pmap_cpu_init_late(struct cpu_info *ci)
* Initialize L3 entry 3. This mapping is shared across all pmaps and is
* static, ie: loading a new pmap will not update this entry.
*/
ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PG_V;
ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PTE_P;
/* Xen wants a RO L3. */
pmap_protect(pmap_kernel(), (vaddr_t)ci->ci_pae_l3_pdir,

36
sys/arch/xen/x86/x86_xpmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: x86_xpmap.c,v 1.83 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: x86_xpmap.c,v 1.84 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2017 The NetBSD Foundation, Inc.
@ -95,7 +95,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.83 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.84 2019/03/09 08:42:25 maxv Exp $");
#include "opt_xen.h"
#include "opt_ddb.h"
@ -180,7 +180,7 @@ xen_set_ldt(vaddr_t base, uint32_t entries)
for (va = base; va < end; va += PAGE_SIZE) {
KASSERT(va >= VM_MIN_KERNEL_ADDRESS);
ptp = kvtopte(va);
pmap_pte_clearbits(ptp, PG_RW);
pmap_pte_clearbits(ptp, PTE_W);
}
s = splvm(); /* XXXSMP */
xpq_queue_set_ldt(base, entries);
@ -681,8 +681,8 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
/* link L4->L3 */
addr = ((u_long)L3) - KERNBASE;
L4cpu[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PG_V | PG_RW;
L4[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PG_V | PG_RW;
L4cpu[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L4[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
/* L2 */
L2 = (pd_entry_t *)avail;
@ -691,7 +691,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
/* link L3->L2 */
addr = ((u_long)L2) - KERNBASE;
L3[pl3_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PG_V | PG_RW;
L3[pl3_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
#else
/* no L4 on i386PAE */
__USE(L4cpu);
@ -720,10 +720,10 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
*/
addr = ((u_long)L2) - KERNBASE;
for (i = 0; i < 3; i++, addr += PAGE_SIZE) {
L3[i] = xpmap_ptom_masked(addr) | PG_V;
L3[i] = xpmap_ptom_masked(addr) | PTE_P;
}
addr += PAGE_SIZE;
L3[3] = xpmap_ptom_masked(addr) | PG_V;
L3[3] = xpmap_ptom_masked(addr) | PTE_P;
#endif
/* Level 1 */
@ -767,7 +767,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
}
#endif
pte[pl1_pi(page)] |= PG_V;
pte[pl1_pi(page)] |= PTE_P;
if (page < (vaddr_t)&__rodata_start) {
/* Map the kernel text RX. Nothing to do. */
} else if (page >= (vaddr_t)&__rodata_start &&
@ -795,17 +795,17 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
} else if (page >= (vaddr_t)&__data_start &&
page < (vaddr_t)&__kernel_end) {
/* Map the kernel data+bss RW. */
pte[pl1_pi(page)] |= PG_RW | xpmap_pg_nx;
pte[pl1_pi(page)] |= PTE_W | xpmap_pg_nx;
} else {
/* Map the page RW. */
pte[pl1_pi(page)] |= PG_RW | xpmap_pg_nx;
pte[pl1_pi(page)] |= PTE_W | xpmap_pg_nx;
}
page += PAGE_SIZE;
}
addr = ((u_long)pte) - KERNBASE;
L2[pl2_pi(cur_page)] = xpmap_ptom_masked(addr) | PG_RW | PG_V;
L2[pl2_pi(cur_page)] = xpmap_ptom_masked(addr) | PTE_W | PTE_P;
/* Mark readonly */
xen_bt_set_readonly((vaddr_t)pte);
@ -815,10 +815,10 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
#ifdef __x86_64__
/* Recursive entry in pmap_kernel(). */
L4[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)L4 - KERNBASE)
| PG_V | xpmap_pg_nx;
| PTE_P | xpmap_pg_nx;
/* Recursive entry in higher-level per-cpu PD. */
L4cpu[PDIR_SLOT_PTE] = xpmap_ptom_masked((paddr_t)L4cpu - KERNBASE)
| PG_V | xpmap_pg_nx;
| PTE_P | xpmap_pg_nx;
/* Mark tables RO */
xen_bt_set_readonly((vaddr_t)L2);
@ -837,7 +837,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
*/
addr = (u_long)L2 - KERNBASE;
for (i = 0; i < 3; i++, addr += PAGE_SIZE) {
L2[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PG_V |
L2[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PTE_P |
xpmap_pg_nx;
}
@ -888,7 +888,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
addr = (u_long)L2 - KERNBASE + PAGE_SIZE * 3;
xpq_queue_pte_update(
xpmap_ptom(((vaddr_t)&L2[PDIR_SLOT_PTE + 3]) - KERNBASE),
xpmap_ptom_masked(addr) | PG_V);
xpmap_ptom_masked(addr) | PTE_P);
xpq_flush_queue();
#endif
}
@ -907,7 +907,7 @@ xen_bootstrap_tables(vaddr_t old_pgd, vaddr_t new_pgd, size_t old_count,
pte += pl1_pi(page);
while (page < old_pgd + (old_count * PAGE_SIZE) && page < map_end) {
addr = xpmap_ptom(((u_long)pte) - KERNBASE);
xpq_queue_pte_update(addr, *pte | PG_RW);
xpq_queue_pte_update(addr, *pte | PTE_W);
page += PAGE_SIZE;
/*
* Our PTEs are contiguous so it's safe to just "++" here.
@ -926,7 +926,7 @@ xen_bt_set_readonly(vaddr_t page)
pt_entry_t entry;
entry = xpmap_ptom_masked(page - KERNBASE);
entry |= PG_V | xpmap_pg_nx;
entry |= PTE_P | xpmap_pg_nx;
HYPERVISOR_update_va_mapping(page, entry, UVMF_INVLPG);
}

12
sys/arch/xen/x86/xen_pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xen_pmap.c,v 1.29 2019/03/07 13:26:24 maxv Exp $ */
/* $NetBSD: xen_pmap.c,v 1.30 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2007 Manuel Bouyer.
@ -101,7 +101,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: xen_pmap.c,v 1.29 2019/03/07 13:26:24 maxv Exp $");
__KERNEL_RCSID(0, "$NetBSD: xen_pmap.c,v 1.30 2019/03/09 08:42:25 maxv Exp $");
#include "opt_user_ldt.h"
#include "opt_lockdebug.h"
@ -175,7 +175,7 @@ pmap_kenter_ma(vaddr_t va, paddr_t ma, vm_prot_t prot, u_int flags)
else
pte = kvtopte(va);
npte = ma | ((prot & VM_PROT_WRITE) ? PG_RW : 0) | PG_V;
npte = ma | ((prot & VM_PROT_WRITE) ? PTE_W : 0) | PTE_P;
if (flags & PMAP_NOCACHE)
npte |= PG_N;
@ -225,7 +225,7 @@ pmap_extract_ma(struct pmap *pmap, vaddr_t va, paddr_t *pap)
pmap_unmap_ptes(pmap, pmap2);
kpreempt_enable();
if (__predict_true((pte & PG_V) != 0)) {
if (__predict_true((pte & PTE_P) != 0)) {
if (pap != NULL)
*pap = (pte & PG_FRAME) | (va & (NBPD_L1 - 1));
return true;
@ -274,7 +274,7 @@ pmap_map_recursive_entries(void)
for (i = 0; i < PDP_SIZE; i++) {
xpq_queue_pte_update(
xpmap_ptom(pmap_pdirpa(pm, PDIR_SLOT_PTE + i)),
xpmap_ptom((pm)->pm_pdirpa[i]) | PG_V);
xpmap_ptom((pm)->pm_pdirpa[i]) | PTE_P);
}
}
mutex_exit(&pmaps_lock);
@ -282,7 +282,7 @@ pmap_map_recursive_entries(void)
for (i = 0; i < PDP_SIZE; i++) {
xpq_queue_pte_update(
xpmap_ptom(pmap_pdirpa(pmap_kernel(), PDIR_SLOT_PTE + i)),
xpmap_ptom(pmap_kernel()->pm_pdirpa[i]) | PG_V);
xpmap_ptom(pmap_kernel()->pm_pdirpa[i]) | PTE_P);
}
}

8
sys/arch/xen/xen/if_xennet_xenbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_xennet_xenbus.c,v 1.85 2019/02/14 08:18:26 cherry Exp $ */
/* $NetBSD: if_xennet_xenbus.c,v 1.86 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -84,7 +84,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_xennet_xenbus.c,v 1.85 2019/02/14 08:18:26 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_xennet_xenbus.c,v 1.86 2019/03/09 08:42:25 maxv Exp $");
#include "opt_xen.h"
#include "opt_nfs_boot.h"
@ -860,7 +860,7 @@ xennet_free_rx_buffer(struct xennet_xenbus_softc *sc)
mmu[0].ptr = (ma << PAGE_SHIFT) | MMU_MACHPHYS_UPDATE;
mmu[0].val = pa >> PAGE_SHIFT;
MULTI_update_va_mapping(&mcl[0], va,
(ma << PAGE_SHIFT) | PG_V | PG_KW | xpmap_pg_nx,
(ma << PAGE_SHIFT) | PTE_P | PTE_W | xpmap_pg_nx,
UVMF_TLB_FLUSH|UVMF_ALL);
xpmap_ptom_map(pa, ptoa(ma));
mcl[1].op = __HYPERVISOR_mmu_update;
@ -1057,7 +1057,7 @@ again:
mmu[0].ptr = (ma << PAGE_SHIFT) | MMU_MACHPHYS_UPDATE;
mmu[0].val = pa >> PAGE_SHIFT;
MULTI_update_va_mapping(&mcl[0], va,
(ma << PAGE_SHIFT) | PG_V | PG_KW | xpmap_pg_nx,
(ma << PAGE_SHIFT) | PTE_P | PTE_W | xpmap_pg_nx,
UVMF_TLB_FLUSH|UVMF_ALL);
xpmap_ptom_map(pa, ptoa(ma));
mcl[1].op = __HYPERVISOR_mmu_update;

6
sys/arch/xen/xen/xen_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xen_machdep.c,v 1.21 2019/02/13 06:52:43 cherry Exp $ */
/* $NetBSD: xen_machdep.c,v 1.22 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -53,7 +53,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: xen_machdep.c,v 1.21 2019/02/13 06:52:43 cherry Exp $");
__KERNEL_RCSID(0, "$NetBSD: xen_machdep.c,v 1.22 2019/03/09 08:42:25 maxv Exp $");
#include "opt_xen.h"
@ -334,7 +334,7 @@ xen_prepare_resume(void)
{
/* map the new shared_info page */
if (HYPERVISOR_update_va_mapping((vaddr_t)HYPERVISOR_shared_info,
xen_start_info.shared_info | PG_RW | PG_V,
xen_start_info.shared_info | PTE_W | PTE_P,
UVMF_INVLPG)) {
DPRINTK(("could not map new shared info page"));
HYPERVISOR_crash();

10
sys/arch/xen/xen/xennetback_xenbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: xennetback_xenbus.c,v 1.74 2019/02/05 06:17:02 msaitoh Exp $ */
/* $NetBSD: xennetback_xenbus.c,v 1.75 2019/03/09 08:42:25 maxv Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: xennetback_xenbus.c,v 1.74 2019/02/05 06:17:02 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: xennetback_xenbus.c,v 1.75 2019/03/09 08:42:25 maxv Exp $");
#include "opt_xen.h"
@ -1077,7 +1077,7 @@ xennetback_ifsoftstart_transfer(void *arg)
*/
xpmap_ptom_map(xmit_pa, newp_ma);
MULTI_update_va_mapping(mclp, xmit_va,
newp_ma | PG_V | PG_RW | PG_U | PG_M | xpmap_pg_nx, 0);
newp_ma | PTE_P | PTE_W | PTE_A | PTE_D | xpmap_pg_nx, 0);
mclp++;
gop->mfn = xmit_ma >> PAGE_SHIFT;
gop->domid = xneti->xni_domid;
@ -1268,8 +1268,8 @@ xennetback_mbuf_addr(struct mbuf *m, paddr_t *xmit_pa, int *offset)
*offset = 0;
break;
}
*offset += (*xmit_pa & ~PG_FRAME);
*xmit_pa = (*xmit_pa & PG_FRAME);
*offset += (*xmit_pa & ~PTE_FRAME);
*xmit_pa = (*xmit_pa & PTE_FRAME);
}
static void