Track the SSIR per-cpu, rather than globally.
This commit is contained in:
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eced30c1f4
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@ -1,4 +1,4 @@
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# $NetBSD: genassym.cf,v 1.24 2020/09/05 16:29:07 thorpej Exp $
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# $NetBSD: genassym.cf,v 1.25 2020/09/05 18:01:42 thorpej Exp $
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#
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#
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# Copyright (c) 1982, 1990, 1993
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# Copyright (c) 1982, 1990, 1993
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@ -188,4 +188,5 @@ define SYS_exit SYS_exit
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# CPU info
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# CPU info
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define CPU_INFO_CURLWP offsetof(struct cpu_info, ci_curlwp)
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define CPU_INFO_CURLWP offsetof(struct cpu_info, ci_curlwp)
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define CPU_INFO_IDLE_LWP offsetof(struct cpu_info, ci_data.cpu_idlelwp)
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define CPU_INFO_IDLE_LWP offsetof(struct cpu_info, ci_data.cpu_idlelwp)
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define CPU_INFO_SSIR offsetof(struct cpu_info, ci_ssir)
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define CPU_INFO_SIZEOF sizeof(struct cpu_info)
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define CPU_INFO_SIZEOF sizeof(struct cpu_info)
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@ -1,4 +1,4 @@
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/* $NetBSD: interrupt.c,v 1.83 2020/09/05 16:29:07 thorpej Exp $ */
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/* $NetBSD: interrupt.c,v 1.84 2020/09/05 18:01:42 thorpej Exp $ */
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/*-
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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@ -65,7 +65,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.83 2020/09/05 16:29:07 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.84 2020/09/05 18:01:42 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/systm.h>
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@ -450,24 +450,21 @@ badaddr_read(void *addr, size_t size, void *rptr)
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return (rv);
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return (rv);
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}
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}
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volatile unsigned long ssir;
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/*
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/*
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* spl0:
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* spllower:
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*
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*
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* Lower interrupt priority to IPL 0 -- must check for
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* Lower interrupt priority. May need to check for software
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* software interrupts.
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* interrupts.
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*/
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*/
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void
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void
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spl0(void)
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spllower(int ipl)
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{
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{
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if (ssir) {
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if (ipl == ALPHA_PSL_IPL_0 && curcpu()->ci_ssir) {
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(void) alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT_LO);
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(void) alpha_pal_swpipl(ALPHA_PSL_IPL_SOFT_LO);
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softintr_dispatch();
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softintr_dispatch();
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}
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}
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(void) alpha_pal_swpipl(ipl);
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(void) alpha_pal_swpipl(ALPHA_PSL_IPL_0);
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}
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}
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/*
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/*
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@ -491,9 +488,7 @@ softintr_dispatch(void)
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void
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void
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softint_trigger(uintptr_t machdep)
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softint_trigger(uintptr_t machdep)
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{
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{
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atomic_or_ulong(&curcpu()->ci_ssir, 1 << (x))
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/* XXX Needs to be per-CPU */
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atomic_or_ulong(&ssir, 1 << (x))
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}
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}
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#endif
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#endif
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.131 2020/09/05 16:29:07 thorpej Exp $ */
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/* $NetBSD: locore.s,v 1.132 2020/09/05 18:01:42 thorpej Exp $ */
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/*-
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/*-
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* Copyright (c) 1999, 2000, 2019 The NetBSD Foundation, Inc.
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* Copyright (c) 1999, 2000, 2019 The NetBSD Foundation, Inc.
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@ -67,7 +67,7 @@
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#include <machine/asm.h>
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#include <machine/asm.h>
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__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.131 2020/09/05 16:29:07 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.132 2020/09/05 18:01:42 thorpej Exp $");
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#include "assym.h"
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#include "assym.h"
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@ -239,8 +239,6 @@ XNESTED(esigcode,0)
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* exception_return: return from trap, exception, or syscall
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* exception_return: return from trap, exception, or syscall
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*/
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*/
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IMPORT(ssir, 8)
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LEAF(exception_return, 1) /* XXX should be NESTED */
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LEAF(exception_return, 1) /* XXX should be NESTED */
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br pv, 1f
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br pv, 1f
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1: LDGP(pv)
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1: LDGP(pv)
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@ -249,8 +247,13 @@ LEAF(exception_return, 1) /* XXX should be NESTED */
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and s1, ALPHA_PSL_IPL_MASK, t0 /* look at the saved IPL */
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and s1, ALPHA_PSL_IPL_MASK, t0 /* look at the saved IPL */
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bne t0, 5f /* != 0: can't do AST or SIR */
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bne t0, 5f /* != 0: can't do AST or SIR */
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/* see if we can do an SIR */
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/* GET_CURLWP clobbers v0, t0, t8...t11. */
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2: ldq t1, ssir /* SIR pending? */
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GET_CURLWP
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mov v0, s0 /* s0 = curlwp */
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/* see if a soft interrupt is pending. */
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2: ldq t1, L_CPU(s0) /* t1 = curlwp->l_cpu */
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ldq t1, CPU_INFO_SSIR(t1) /* soft int pending? */
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bne t1, 6f /* yes */
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bne t1, 6f /* yes */
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/* no */
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/* no */
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@ -258,16 +261,13 @@ LEAF(exception_return, 1) /* XXX should be NESTED */
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beq t0, 5f /* no: just return */
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beq t0, 5f /* no: just return */
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/* yes */
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/* yes */
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/* GET_CURLWP clobbers v0, t0, t8...t11. */
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3: GET_CURLWP
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/* check for AST */
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/* check for AST */
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ldl t3, L_MD_ASTPENDING(v0) /* AST pending? */
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3: ldl t3, L_MD_ASTPENDING(s0) /* AST pending? */
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bne t3, 7f /* yes */
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bne t3, 7f /* yes */
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/* no: headed back to user space */
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/* no: headed back to user space */
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/* Enable the FPU based on whether MDLWP_FPACTIVE is set. */
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/* Enable the FPU based on whether MDLWP_FPACTIVE is set. */
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4: ldq t2, L_MD_FLAGS(v0)
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4: ldq t2, L_MD_FLAGS(s0)
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cmplt t2, zero, a0
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cmplt t2, zero, a0
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call_pal PAL_OSF1_wrfen
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call_pal PAL_OSF1_wrfen
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@ -294,7 +294,7 @@ LEAF(exception_return, 1) /* XXX should be NESTED */
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br 2b
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br 2b
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/* We've got an AST */
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/* We've got an AST */
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7: stl zero, L_MD_ASTPENDING(v0) /* no AST pending */
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7: stl zero, L_MD_ASTPENDING(s0) /* no AST pending */
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ldiq a0, ALPHA_PSL_IPL_0 /* drop IPL to zero */
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ldiq a0, ALPHA_PSL_IPL_0 /* drop IPL to zero */
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call_pal PAL_OSF1_swpipl
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call_pal PAL_OSF1_swpipl
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.94 2020/09/04 15:50:09 thorpej Exp $ */
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/* $NetBSD: cpu.h,v 1.95 2020/09/05 18:01:42 thorpej Exp $ */
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/*-
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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@ -108,6 +108,7 @@ struct cpu_info {
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volatile int ci_mtx_oldspl; /* [MI] for spin mutex splx() */
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volatile int ci_mtx_oldspl; /* [MI] for spin mutex splx() */
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u_long ci_intrdepth; /* interrupt trap depth */
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u_long ci_intrdepth; /* interrupt trap depth */
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volatile u_long ci_ssir; /* simulated software interrupt reg */
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struct cpu_softc *ci_softc; /* pointer to our device */
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struct cpu_softc *ci_softc; /* pointer to our device */
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struct pmap *ci_pmap; /* currently-activated pmap */
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struct pmap *ci_pmap; /* currently-activated pmap */
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struct trapframe *ci_db_regs; /* registers for debuggers */
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struct trapframe *ci_db_regs; /* registers for debuggers */
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};
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};
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/* Ensure cpu_info::ci_curlwp is within the signed 16-bit displacement. */
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/* Ensure some cpu_info fields are within the signed 16-bit displacement. */
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__CTASSERT(offsetof(struct cpu_info, ci_curlwp) <= 0x7ff0);
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__CTASSERT(offsetof(struct cpu_info, ci_curlwp) <= 0x7ff0);
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__CTASSERT(offsetof(struct cpu_info, ci_ssir) <= 0x7ff0);
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#endif /* _KERNEL || _KMEMUSER */
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#endif /* _KERNEL || _KMEMUSER */
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.74 2020/09/05 16:29:08 thorpej Exp $ */
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/* $NetBSD: intr.h,v 1.75 2020/09/05 18:01:42 thorpej Exp $ */
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/*-
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/*-
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* Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc.
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* Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc.
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@ -132,20 +132,12 @@ makeiplcookie(ipl_t ipl)
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#ifdef _KERNEL
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#ifdef _KERNEL
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/* Simulated software interrupt register. */
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extern volatile unsigned long ssir;
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/* IPL-lowering/restoring macros */
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/* IPL-lowering/restoring macros */
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void spl0(void);
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void spllower(int);
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#define splx(s) spllower(s)
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#define spl0() spllower(ALPHA_PSL_IPL_0)
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static __inline void
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splx(int s)
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{
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if (s == ALPHA_PSL_IPL_0 && ssir != 0)
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spl0();
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else
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alpha_pal_swpipl(s);
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}
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/* IPL-raising functions/macros */
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/* IPL-raising functions/macros */
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static __inline int
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static __inline int
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_splraise(int s)
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_splraise(int s)
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