Clean up slightly, abstract pci_conf_print family's base address register
printing into a function, add a bit more pretty-printing of existing stuff. Implement pretty-printers for type 1 and type 2 headers. (Right now, these are just quick stabs based on some on-line bridge docs that I have handy on my laptop. Mmmm, meetings. I'll check the bits when I get back within reach of my official docs.)
This commit is contained in:
cgd
parent
f2e26f6125
commit
e3c75e1ca8
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.26 1998/05/18 17:25:17 cgd Exp $ */
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/* $NetBSD: pci_subr.c,v 1.27 1998/05/28 02:26:00 cgd Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -52,8 +52,14 @@
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static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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static void pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs, int));
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static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t,
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const pcireg_t *regs));
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/*
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* Descriptions of known PCI classes and subclasses.
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@ -326,6 +332,8 @@ pci_devinfo(id_reg, class_reg, showclass, cp)
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#define i2o(i) ((i) * 4)
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#define o2i(o) ((o) / 4)
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#define onoff(str, bit) \
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printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off");
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static void
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pci_conf_print_common(pc, tag, regs)
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@ -363,9 +371,6 @@ pci_conf_print_common(pc, tag, regs)
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printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
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#endif /* PCIVERBOSE */
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#define onoff(str, bit) \
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printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off");
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rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
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printf(" Command register: 0x%04x\n", rval & 0xffff);
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@ -409,8 +414,6 @@ pci_conf_print_common(pc, tag, regs)
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onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR);
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onoff("Parity error detected", PCI_STATUS_PARITY_DETECT);
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#undef onoff
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rval = regs[o2i(PCI_CLASS_REG)];
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for (classp = pci_class; classp->name != NULL; classp++) {
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if (PCI_CLASS(rval) == classp->val)
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@ -447,79 +450,90 @@ pci_conf_print_common(pc, tag, regs)
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}
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static void
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pci_conf_print_type1(pc, tag, regs)
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pci_conf_print_bar(pc, tag, regs, reg)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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int reg;
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{
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int s;
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pcireg_t mask, rval;
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/*
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* Section 6.2.5.1, `Address Maps', tells us that:
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*
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* 1) The builtin software should have already mapped the
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* device in a reasonable way.
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*
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* 2) A device which wants 2^n bytes of memory will hardwire
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* the bottom n bits of the address to 0. As recommended,
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* we write all 1s and see what we get back.
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*/
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rval = regs[o2i(reg)];
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if (rval != 0) {
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/*
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* The following sequence seems to make some devices
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* (e.g. host bus bridges, which don't normally
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* have their space mapped) very unhappy, to
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* the point of crashing the system.
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*
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* Therefore, if the mapping register is zero to
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* start out with, don't bother trying.
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*/
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s = splhigh();
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pci_conf_write(pc, tag, reg, 0xffffffff);
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mask = pci_conf_read(pc, tag, reg);
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pci_conf_write(pc, tag, reg, rval);
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splx(s);
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} else
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mask = 0;
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printf(" Base address register at 0x%02x: ", reg);
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if (rval == 0) {
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printf("not implemented(?)\n");
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} else if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
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const char *type, *cache;
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switch (PCI_MAPREG_MEM_TYPE(rval)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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type = "32-bit";
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break;
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case PCI_MAPREG_MEM_TYPE_32BIT_1M:
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type = "32-bit-1M";
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break;
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case PCI_MAPREG_MEM_TYPE_64BIT:
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type = "64-bit";
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break;
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default:
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type = "unknown (XXX)";
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break;
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}
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if (PCI_MAPREG_MEM_CACHEABLE(rval))
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cache = "";
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else
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cache = "non";
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printf("%s %scacheable memory\n", type, cache);
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_MEM_ADDR(rval),
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PCI_MAPREG_MEM_SIZE(mask));
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} else {
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printf("i/o\n");
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_IO_ADDR(rval),
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PCI_MAPREG_IO_SIZE(mask));
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}
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}
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static void
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pci_conf_print_type0(pc, tag, regs)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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{
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int off, s;
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pcireg_t mask, rval;
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int off;
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pcireg_t rval;
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for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4) {
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/*
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* Section 6.2.5.1, `Address Maps', tells us that:
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*
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* 1) The builtin software should have already mapped the
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* device in a reasonable way.
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*
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* 2) A device which wants 2^n bytes of memory will hardwire
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* the bottom n bits of the address to 0. As recommended,
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* we write all 1s and see what we get back.
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*/
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rval = regs[o2i(off)];
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if (rval != 0) {
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/*
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* The following sequence seems to make some devices
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* (e.g. host bus bridges, which don't normally
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* have their space mapped) very unhappy, to
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* the point of crashing the system.
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*
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* Therefore, if the mapping register is zero to
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* start out with, don't bother trying.
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*/
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s = splhigh();
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pci_conf_write(pc, tag, off, 0xffffffff);
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mask = pci_conf_read(pc, tag, off);
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pci_conf_write(pc, tag, off, rval);
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splx(s);
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} else
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mask = 0;
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printf(" Mapping register at 0x%02x: ", off);
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if (rval == 0) {
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printf("not implemented(?)\n");
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} else if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
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const char *type, *cache;
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switch (PCI_MAPREG_MEM_TYPE(rval)) {
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case PCI_MAPREG_MEM_TYPE_32BIT:
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type = "32-bit";
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break;
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case PCI_MAPREG_MEM_TYPE_32BIT_1M:
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type = "32-bit-1M";
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break;
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case PCI_MAPREG_MEM_TYPE_64BIT:
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type = "64-bit";
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break;
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default:
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type = "unknown (XXX)";
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break;
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}
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if (PCI_MAPREG_MEM_CACHEABLE(rval))
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cache = "";
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else
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cache = "non";
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printf("%s %scacheable memory\n", type, cache);
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_MEM_ADDR(rval),
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PCI_MAPREG_MEM_SIZE(mask));
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} else {
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printf("i/o\n");
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printf(" base address: 0x%08x, size: 0x%08x\n",
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PCI_MAPREG_IO_ADDR(rval),
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PCI_MAPREG_IO_SIZE(mask));
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}
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}
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for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4)
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pci_conf_print_bar(pc, tag, regs, off);
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printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
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@ -535,28 +549,273 @@ pci_conf_print_type1(pc, tag, regs)
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rval = regs[o2i(PCI_INTERRUPT_REG)];
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printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
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printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
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printf(" Interrupt pin: 0x%02x", PCI_INTERRUPT_PIN(rval));
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printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
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switch (PCI_INTERRUPT_PIN(rval)) {
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case PCI_INTERRUPT_PIN_NONE:
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printf(" (none)");
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printf("(none)");
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break;
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case PCI_INTERRUPT_PIN_A:
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printf(" (pin A)");
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printf("(pin A)");
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break;
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case PCI_INTERRUPT_PIN_B:
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printf(" (pin B)");
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printf("(pin B)");
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break;
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case PCI_INTERRUPT_PIN_C:
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printf(" (pin C)");
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printf("(pin C)");
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break;
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case PCI_INTERRUPT_PIN_D:
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printf(" (pin D)");
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printf("(pin D)");
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break;
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default:
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printf("(???)");
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break;
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}
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printf("\n");
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printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
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}
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static void
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pci_conf_print_type1(pc, tag, regs)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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{
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int off;
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pcireg_t rval;
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/*
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* XXX these need to be printed in more detail, need to be
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* XXX checked against specs/docs, etc.
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*
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* This layout was cribbed from the TI PCI2030 PCI-to-PCI
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* Bridge chip documentation, and may not be correct with
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* respect to various standards. (XXX)
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*/
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for (off = 0x10; off < 0x18; off += 4)
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pci_conf_print_bar(pc, tag, regs, off);
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printf(" Primary bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 0) & 0xff);
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printf(" Secondary bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 8) & 0xff);
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printf(" Subordinate bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 16) & 0xff);
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printf(" Secondary bus latency timer: 0x%02x\n",
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(regs[o2i(0x18)] >> 24) & 0xff);
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rval = (regs[o2i(0x1c)] >> 16) & 0xffff;
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printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */
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onoff("66 MHz capable", 0x0020);
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onoff("User Definable Features (UDF) support", 0x0040);
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onoff("Fast back-to-back capable", 0x0080);
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onoff("Data parity error detected", 0x0100);
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printf(" DEVSEL timing: ");
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switch (rval & 0x0600) {
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case 0x0000:
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printf("fast");
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break;
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case 0x0200:
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printf("medium");
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break;
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case 0x0400:
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printf("slow");
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break;
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default:
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printf("unknown/reserved"); /* XXX */
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break;
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}
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printf(" (0x%x)\n", (rval & 0x0600) >> 9);
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onoff("Signaled Target Abort", 0x0800);
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onoff("Received Target Abort", 0x1000);
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onoff("Received Master Abort", 0x2000);
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onoff("System Error", 0x4000);
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onoff("Parity Error", 0x8000);
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/* XXX Print more prettily */
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printf(" I/O region:\n");
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printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff);
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printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff);
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printf(" base upper 16 bits register: 0x%04x\n",
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(regs[o2i(0x30)] >> 0) & 0xffff);
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printf(" limit upper 16 bits register: 0x%04x\n",
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(regs[o2i(0x30)] >> 16) & 0xffff);
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/* XXX Print more prettily */
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printf(" Memory region:\n");
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printf(" base register: 0x%04x\n",
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(regs[o2i(0x20)] >> 0) & 0xffff);
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printf(" limit register: 0x%04x\n",
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(regs[o2i(0x20)] >> 16) & 0xffff);
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/* XXX Print more prettily */
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printf(" Prefetchable memory region:\n");
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printf(" base register: 0x%04x\n",
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(regs[o2i(0x24)] >> 0) & 0xffff);
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printf(" limit register: 0x%04x\n",
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(regs[o2i(0x24)] >> 16) & 0xffff);
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printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]);
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printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]);
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printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
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/* XXX */
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printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
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printf(" Interrupt line: 0x%02x\n",
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(regs[o2i(0x3c)] >> 0) & 0xff);
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printf(" Interrupt pin: 0x%02x ",
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(regs[o2i(0x3c)] >> 8) & 0xff);
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switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
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case PCI_INTERRUPT_PIN_NONE:
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printf("(none)");
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break;
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case PCI_INTERRUPT_PIN_A:
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printf("(pin A)");
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break;
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case PCI_INTERRUPT_PIN_B:
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printf("(pin B)");
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break;
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case PCI_INTERRUPT_PIN_C:
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printf("(pin C)");
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break;
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case PCI_INTERRUPT_PIN_D:
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printf("(pin D)");
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break;
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default:
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printf("(???)");
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break;
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}
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printf("\n");
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rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
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printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */
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onoff("Parity error response", 0x0001);
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onoff("Secondary SERR forwarding", 0x0002);
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onoff("ISA enable", 0x0004);
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onoff("VGA enable", 0x0008);
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onoff("Master abort reporting", 0x0020);
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onoff("Secondary bus reset", 0x0040);
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onoff("Fast back-to-back capable", 0x0080);
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}
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static void
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pci_conf_print_type2(pc, tag, regs)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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const pcireg_t *regs;
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{
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int off;
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pcireg_t rval;
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/*
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* XXX these need to be printed in more detail, need to be
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* XXX checked against specs/docs, etc.
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*
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* This layout was cribbed from the TI PCI1130 PCI-to-CardBus
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* controller chip documentation, and may not be correct with
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* respect to various standards. (XXX)
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*/
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for (off = 0x10; off < 0x14; off += 4)
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pci_conf_print_bar(pc, tag, regs, off);
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printf(" Reserved @ 0x14: 0x%04x\n",
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(regs[o2i(0x14)] >> 0) & 0xffff);
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rval = (regs[o2i(0x14)] >> 16) & 0xffff;
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printf(" Secondary status register: 0x%04x\n", rval);
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onoff("66 MHz capable", 0x0020);
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onoff("User Definable Features (UDF) support", 0x0040);
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onoff("Fast back-to-back capable", 0x0080);
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onoff("Data parity error detection", 0x0100);
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printf(" DEVSEL timing: ");
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switch (rval & 0x0600) {
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case 0x0000:
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printf("fast");
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break;
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case 0x0200:
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printf("medium");
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break;
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case 0x0400:
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printf("slow");
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break;
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default:
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printf("unknown/reserved"); /* XXX */
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break;
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}
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printf(" (0x%x)\n", (rval & 0x0600) >> 9);
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onoff("PCI target aborts terminate CardBus bus master transactions",
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0x0800);
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onoff("CardBus target aborts terminate PCI bus master transactions",
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0x1000);
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onoff("Bus initiator aborts terminate initiator transactions",
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0x2000);
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onoff("System error", 0x4000);
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onoff("Parity error", 0x8000);
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printf(" PCI bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 0) & 0xff);
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printf(" CardBus bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 8) & 0xff);
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printf(" Subordinate bus number: 0x%02x\n",
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(regs[o2i(0x18)] >> 16) & 0xff);
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printf(" CardBus latency timer: 0x%02x\n",
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(regs[o2i(0x18)] >> 24) & 0xff);
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/* XXX Print more prettily */
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||||
printf(" CardBus memory region 0:\n");
|
||||
printf(" base register: 0x%08x\n", regs[o2i(0x1c)]);
|
||||
printf(" limit register: 0x%08x\n", regs[o2i(0x20)]);
|
||||
printf(" CardBus memory region 1:\n");
|
||||
printf(" base register: 0x%08x\n", regs[o2i(0x24)]);
|
||||
printf(" limit register: 0x%08x\n", regs[o2i(0x28)]);
|
||||
printf(" CardBus I/O region 0:\n");
|
||||
printf(" base register: 0x%08x\n", regs[o2i(0x2c)]);
|
||||
printf(" limit register: 0x%08x\n", regs[o2i(0x30)]);
|
||||
printf(" CardBus I/O region 1:\n");
|
||||
printf(" base register: 0x%08x\n", regs[o2i(0x34)]);
|
||||
printf(" limit register: 0x%08x\n", regs[o2i(0x38)]);
|
||||
|
||||
printf(" Interrupt line: 0x%02x\n",
|
||||
(regs[o2i(0x3c)] >> 0) & 0xff);
|
||||
printf(" Interrupt pin: 0x%02x ",
|
||||
(regs[o2i(0x3c)] >> 8) & 0xff);
|
||||
switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
|
||||
case PCI_INTERRUPT_PIN_NONE:
|
||||
printf("(none)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_A:
|
||||
printf("(pin A)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_B:
|
||||
printf("(pin B)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_C:
|
||||
printf("(pin C)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_D:
|
||||
printf("(pin D)");
|
||||
break;
|
||||
default:
|
||||
printf("(???)");
|
||||
break;
|
||||
}
|
||||
printf("\n");
|
||||
rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
|
||||
printf(" Bridge control register: 0x%04x\n", rval);
|
||||
onoff("Parity error response", 0x0001);
|
||||
onoff("CardBus SERR forwarding", 0x0002);
|
||||
onoff("ISA enable", 0x0004);
|
||||
onoff("VGA enable", 0x0008);
|
||||
onoff("CardBus master abort reporting", 0x0020);
|
||||
onoff("CardBus reset", 0x0040);
|
||||
onoff("Functional interrupts routed by ExCA registers", 0x0080);
|
||||
onoff("Memory window 0 prefetchable", 0x0100);
|
||||
onoff("Memory window 1 prefetchable", 0x0200);
|
||||
onoff("Write posting enable", 0x0400);
|
||||
}
|
||||
|
||||
void
|
||||
pci_conf_print(pc, tag, printfn)
|
||||
pci_chipset_tag_t pc;
|
||||
|
|
@ -565,6 +824,7 @@ pci_conf_print(pc, tag, printfn)
|
|||
{
|
||||
pcireg_t regs[o2i(256)];
|
||||
int off, hdrtype;
|
||||
const char *typename;
|
||||
void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *);
|
||||
|
||||
printf("PCI configuration registers:\n");
|
||||
|
|
@ -587,19 +847,33 @@ pci_conf_print(pc, tag, printfn)
|
|||
|
||||
/* type-dependent header */
|
||||
hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
|
||||
printf(" Type %d header:\n", hdrtype);
|
||||
switch (hdrtype) { /* XXX make a table, eventually */
|
||||
case 0:
|
||||
/* Standard device header */
|
||||
typename = "\"normal\" device";
|
||||
typeprintfn = &pci_conf_print_type0;
|
||||
break;
|
||||
case 1:
|
||||
/* PCI-PCI bridge header */
|
||||
typename = "PCI-PCI bridge";
|
||||
typeprintfn = &pci_conf_print_type1;
|
||||
break;
|
||||
case 2:
|
||||
/* PCI-CardBus bridge header */
|
||||
typename = "PCI-CardBus bridge";
|
||||
typeprintfn = &pci_conf_print_type2;
|
||||
break;
|
||||
default:
|
||||
typename = NULL;
|
||||
typeprintfn = 0;
|
||||
}
|
||||
printf(" Type %d ", hdrtype);
|
||||
if (typename != NULL)
|
||||
printf("(%s) ", typename);
|
||||
printf("header:\n");
|
||||
for (off = 16; off < 64; off += 16)
|
||||
print16regs(off);
|
||||
printf("\n");
|
||||
switch (hdrtype) { /* XXX make a table, eventually */
|
||||
case 0:
|
||||
typeprintfn = &pci_conf_print_type1;
|
||||
break;
|
||||
case 1:
|
||||
/* XXX */
|
||||
default:
|
||||
typeprintfn = 0;
|
||||
}
|
||||
if (typeprintfn)
|
||||
(*typeprintfn)(pc, tag, regs);
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue