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This commit is contained in:
msaitoh 2016-08-08 07:10:53 +00:00
parent d623e4f514
commit e1ef0ff3eb
2 changed files with 3669 additions and 3649 deletions
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12
sys/dev/pci/pcidevs.h
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@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1248 2016/07/29 07:28:52 nonaka Exp $ */
/* $NetBSD: pcidevs.h,v 1.1249 2016/08/08 07:10:53 msaitoh Exp $ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1256 2016/07/29 07:28:19 nonaka Exp
* NetBSD: pcidevs,v 1.1257 2016/08/08 07:10:28 msaitoh Exp
*/
/*
@ -3668,7 +3668,8 @@
#define PCI_PRODUCT_INTEL_82B43_HB 0x2e40 /* 82B43 Host Bridge */
#define PCI_PRODUCT_INTEL_82B43_IGD 0x2e42 /* 82B43 Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_XE5_V3_DMI2 0x2f00 /* Xeon E5 v3 DMI2 */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_1 0x2f01 /* Xeon E5 v3 PCIe Root Port in DMI2 Mode */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_1_1 0x2f01 /* Xeon E5 v3 PCIe Root Port in DMI2 Mode */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_1_2 0x2f02 /* Xeon E5 v3 PCIe Root Port */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_2_1 0x2f04 /* Xeon E5 v3 PCIe Root Port */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_2_2 0x2f05 /* Xeon E5 v3 PCIe Root Port */
#define PCI_PRODUCT_INTEL_XE5_V3_PCIE_2_3 0x2f06 /* Xeon E5 v3 PCIe Root Port */
@ -3689,8 +3690,12 @@
#define PCI_PRODUCT_INTEL_XE5_V3_QDT_CH6 0x2f26 /* Xeon E5 v3 QDT DMA Channel 6 */
#define PCI_PRODUCT_INTEL_XE5_V3_QDT_CH7 0x2f27 /* Xeon E5 v3 QDT DMA Channel 7 */
#define PCI_PRODUCT_INTEL_XE5_V3_IIO_AM 0x2f28 /* Xeon E5 v3 Address Map, VTd, SMM */
#define PCI_PRODUCT_INTEL_XE5_V3_HOTPLUG 0x2f29 /* Xeon E5 v3 Hot Plug */
#define PCI_PRODUCT_INTEL_XE5_V3_IIO_RAM 0x2f2a /* Xeon E5 v3 RAS, CS, Global Errors */
#define PCI_PRODUCT_INTEL_XE5_V3_IIO_IOAPIC 0x2f2c /* Xeon E5 v3 I/O APIC */
#define PCI_PRODUCT_INTEL_XE5_V3_HA 0x2f30 /* Xeon E5 v3 Home Agent */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK2 0x2f32 /* Xeon E5 v3 QPI Link 0 */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK3 0x2f33 /* Xeon E5 v3 QPI Link 1 */
#define PCI_PRODUCT_INTEL_XE5_V3_R2PCIE_2 0x2f34 /* Xeon E5 v3 PCIe Ring Performance Monitoring */
#define PCI_PRODUCT_INTEL_XE5_V3_RQPI_PM_1 0x2f36 /* Xeon E5 v3 QPI Ring Performance Monitoring */
#define PCI_PRODUCT_INTEL_XE5_V3_RQPI_PM_2 0x2f37 /* Xeon E5 v3 QPI Ring Interface Monitoring */
@ -3702,6 +3707,7 @@
#define PCI_PRODUCT_INTEL_XE5_V3_UBOX_2 0x2f7d /* Xeon E5 v3 Scratchpad and Semaphores */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK0 0x2f80 /* Xeon E5 v3 QPI Link 0 */
#define PCI_PRODUCT_INTEL_XE5_V3_RQPI_RING 0x2f81 /* Xeon E5 v3 QPI Ring Interface */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK4 0x2f83 /* Xeon E5 v3 QPI Link 0 */
#define PCI_PRODUCT_INTEL_XE5_V3_QPI_LINK1 0x2f90 /* Xeon E5 v3 QPI Link 1 */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_1 0x2f98 /* Xeon E5 v3 Power Control Unit */
#define PCI_PRODUCT_INTEL_XE5_V3_PCU_2 0x2f99 /* Xeon E5 v3 Power Control Unit */

7306
sys/dev/pci/pcidevs_data.h
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