Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Initilize CP0 pagemask register properly.

Browse Source 
Fixes PR 30590 and some other mips port.
This commit is contained in:
tsutsui 2005-09-08 15:17:23 +00:00
parent 95d5cf1493
commit e17fe7c64d
1 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.178 2005/06/01 16:53:07 drochner Exp $ */
/* $NetBSD: mips_machdep.c,v 1.179 2005/09/08 15:17:23 tsutsui Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -119,7 +119,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.178 2005/06/01 16:53:07 drochner Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.179 2005/09/08 15:17:23 tsutsui Exp $");
#include "opt_cputype.h"
@ -216,10 +216,6 @@ struct segtab *segbase;
caddr_t msgbufaddr;
#if defined(MIPS3_4100) /* VR4100 core */
int default_pg_mask = 0x00001800;
#endif
/* the following is used externally (sysctl_hw) */
char machine[] = MACHINE; /* from <machine/param.h> */
char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
@ -886,12 +882,18 @@ mips_vector_init(void)
case CPU_ARCH_MIPS3:
case CPU_ARCH_MIPS4:
#if defined(MIPS3_5900) /* XXX */
mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
mips3_cp0_wired_write(0);
mips5900_TBIA(mips_num_tlb_entries);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
r5900_vector_init();
memcpy(mips_locoresw, mips5900_locoresw, sizeof(mips_locoresw));
#else /* MIPS3_5900 */
#if defined(MIPS3_4100)
mips3_cp0_pg_mask_write(MIPS4100_PG_SIZE_4K);
#else
mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
#endif
mips3_cp0_wired_write(0);
mips3_TBIA(mips_num_tlb_entries);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
@ -902,6 +904,7 @@ mips_vector_init(void)
#endif
#if defined(MIPS32)
case CPU_ARCH_MIPS32:
mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
mips3_cp0_wired_write(0);
mips32_TBIA(mips_num_tlb_entries);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
@ -911,6 +914,7 @@ mips_vector_init(void)
#endif
#if defined(MIPS64)
case CPU_ARCH_MIPS64:
mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_4K);
mips3_cp0_wired_write(0);
mips64_TBIA(mips_num_tlb_entries);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);