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Remove moved files.

This commit is contained in:
ragge 1999-06-20 18:19:19 +00:00
parent 37d80b004f
commit e0972091c8
10 changed files with 0 additions and 3211 deletions
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847
sys/arch/vax/uba/dhu.c
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@ -1,847 +0,0 @@
/* $NetBSD: dhu.c,v 1.13 1999/01/19 21:04:48 ragge Exp $ */
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/map.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <machine/trap.h>
#include <machine/scb.h>
#include <vax/uba/ubavar.h>
#include <vax/uba/dhureg.h>
/* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */
#define NDHULINE 16
#define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */
#define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */
struct dhu_softc {
struct device sc_dev; /* Device struct used by config */
dhuregs * sc_addr; /* controller reg address */
int sc_type; /* controller type, DHU or DHV */
struct {
struct tty *dhu_tty; /* what we work on */
int dhu_state; /* to manage TX output status */
int dhu_txaddr; /* UBA map address to TX buf */
short dhu_cc; /* character count on TX */
short dhu_modem; /* modem bits state */
} sc_dhu[NDHULINE];
};
#define IS_DHU 16 /* Unibus DHU-11 board linecount */
#define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */
#define STATE_IDLE 000 /* no current output in progress */
#define STATE_DMA_RUNNING 001 /* DMA TX in progress */
#define STATE_DMA_STOPPED 002 /* DMA TX was aborted */
#define STATE_TX_ONE_CHAR 004 /* did a single char directly */
/* Flags used to monitor modem bits, make them understood outside driver */
#define DML_DTR TIOCM_DTR
#define DML_RTS TIOCM_RTS
#define DML_CTS TIOCM_CTS
#define DML_DCD TIOCM_CD
#define DML_RI TIOCM_RI
#define DML_DSR TIOCM_DSR
#define DML_BRK 0100000 /* no equivalent, we will mask */
/* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */
/* a baud rate from the same group. So limiting to B is likely */
/* best, although clone boards like the ABLE QHV allow all settings. */
static struct speedtab dhuspeedtab[] = {
{ 0, 0 }, /* Groups */
{ 50, DHU_LPR_B50 }, /* A */
{ 75, DHU_LPR_B75 }, /* B */
{ 110, DHU_LPR_B110 }, /* A and B */
{ 134, DHU_LPR_B134 }, /* A and B */
{ 150, DHU_LPR_B150 }, /* B */
{ 300, DHU_LPR_B300 }, /* A and B */
{ 600, DHU_LPR_B600 }, /* A and B */
{ 1200, DHU_LPR_B1200 }, /* A and B */
{ 1800, DHU_LPR_B1800 }, /* B */
{ 2000, DHU_LPR_B2000 }, /* B */
{ 2400, DHU_LPR_B2400 }, /* A and B */
{ 4800, DHU_LPR_B4800 }, /* A and B */
{ 7200, DHU_LPR_B7200 }, /* A */
{ 9600, DHU_LPR_B9600 }, /* A and B */
{ 19200, DHU_LPR_B19200 }, /* B */
{ 38400, DHU_LPR_B38400 }, /* A */
{ -1, -1 }
};
static int dhu_match __P((struct device *, struct cfdata *, void *));
static void dhu_attach __P((struct device *, struct device *, void *));
static void dhurint __P((int));
static void dhuxint __P((int));
static void dhustart __P((struct tty *));
static int dhuparam __P((struct tty *, struct termios *));
static int dhuiflow __P((struct tty *, int));
static unsigned dhumctl __P((struct dhu_softc *,int, int, int));
int dhuopen __P((dev_t, int, int, struct proc *));
int dhuclose __P((dev_t, int, int, struct proc *));
int dhuread __P((dev_t, struct uio *, int));
int dhuwrite __P((dev_t, struct uio *, int));
int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *));
void dhustop __P((struct tty *, int));
struct tty * dhutty __P((dev_t));
struct cfattach dhu_ca = {
sizeof(struct dhu_softc), dhu_match, dhu_attach
};
extern struct cfdriver dhu_cd;
/* Autoconfig handles: setup the controller to interrupt, */
/* then complete the housecleaning for full operation */
static int
dhu_match(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct uba_attach_args *ua = aux;
register dhuregs *dhuaddr;
register int n;
dhuaddr = (dhuregs *) ua->ua_addr;
/* Reset controller to initialize, enable TX/RX interrupts */
/* to catch floating vector info elsewhere when completed */
dhuaddr->dhu_csr = (DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE);
/* Now wait up to 3 seconds for self-test to complete. */
for (n = 0; n < 300; n++) {
DELAY(10000);
if ((dhuaddr->dhu_csr & DHU_CSR_MASTER_RESET) == 0)
break;
}
/* If the RESET did not clear after 3 seconds, */
/* the controller must be broken. */
if (n >= 300)
return 0;
/* Check whether diagnostic run has signalled a failure. */
if ((dhuaddr->dhu_csr & DHU_CSR_DIAG_FAIL) != 0)
return 0;
/* Register the RX interrupt handler */
ua->ua_ivec = dhurint;
return 1;
}
static void
dhu_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
register struct dhu_softc *sc = (void *)self;
register struct uba_attach_args *ua = aux;
register dhuregs *dhuaddr;
register unsigned c;
register int n;
dhuaddr = (dhuregs *) ua->ua_addr;
/* Process the 8 bytes of diagnostic info put into */
/* the FIFO following the master reset operation. */
printf("\n%s:", self->dv_xname);
for (n = 0; n < 8; n++) {
c = dhuaddr->dhu_rbuf;
if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) {
if ((c&0200) == 0000)
printf(" rom(%d) version %d",
((c>>1)&01), ((c>>2)&037));
else if (((c>>2)&07) != 0)
printf(" diag-error(proc%d)=%x",
((c>>1)&01), ((c>>2)&07));
}
}
printf("\n");
c = dhuaddr->dhu_stat; /* get flag to distinguish DHU from DHV */
sc->sc_addr = dhuaddr;
sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV;
/* Now stuff TX interrupt handler in place */
scb_vecalloc(ua->ua_cvec + 4, dhuxint, self->dv_unit, SCB_ISTACK);
}
/* Receiver Interrupt */
static void
dhurint(unit)
int unit;
{
struct dhu_softc *sc = dhu_cd.cd_devs[unit];
register dhuregs *dhuaddr;
register struct tty *tp;
register int cc, line;
register unsigned c, delta;
int overrun = 0;
dhuaddr = sc->sc_addr;
while ((c = dhuaddr->dhu_rbuf) & DHU_RBUF_DATA_VALID) {
/* Ignore diagnostic FIFO entries. */
if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE)
continue;
cc = c & 0xFF;
line = DHU_LINE(c>>8);
tp = sc->sc_dhu[line].dhu_tty;
/* LINK.TYPE is set so we get modem control FIFO entries */
if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) {
c = (c << 8);
/* Do MDMBUF flow control, wakeup sleeping opens */
if (c & DHU_STAT_DCD) {
if (!(tp->t_state & TS_CARR_ON))
(void)(*linesw[tp->t_line].l_modem)(tp, 1);
}
else if ((tp->t_state & TS_CARR_ON) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
(void) dhumctl(sc, line, 0, DMSET);
/* Do CRTSCTS flow control */
delta = c ^ sc->sc_dhu[line].dhu_modem;
sc->sc_dhu[line].dhu_modem = c;
if ((delta & DHU_STAT_CTS) &&
(tp->t_state & TS_ISOPEN) &&
(tp->t_cflag & CRTSCTS)) {
if (c & DHU_STAT_CTS) {
tp->t_state &= ~TS_TTSTOP;
ttstart(tp);
} else {
tp->t_state |= TS_TTSTOP;
dhustop(tp, 0);
}
}
continue;
}
if (!(tp->t_state & TS_ISOPEN)) {
wakeup((caddr_t)&tp->t_rawq);
continue;
}
if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) {
log(LOG_WARNING, "%s: silo overflow, line %d\n",
sc->sc_dev.dv_xname, line);
overrun = 1;
}
/* A BREAK key will appear as a NULL with a framing error */
if (c & DHU_RBUF_FRAMING_ERR)
cc |= TTY_FE;
if (c & DHU_RBUF_PARITY_ERR)
cc |= TTY_PE;
(*linesw[tp->t_line].l_rint)(cc, tp);
}
return;
}
/* Transmitter Interrupt */
static void
dhuxint(unit)
int unit;
{
register struct dhu_softc *sc = dhu_cd.cd_devs[unit];
register dhuregs *dhuaddr;
register struct tty *tp;
register int line;
dhuaddr = sc->sc_addr;
line = DHU_LINE(dhuaddr->dhu_csr_hi);
tp = sc->sc_dhu[line].dhu_tty;
tp->t_state &= ~TS_BUSY;
if (tp->t_state & TS_FLUSH)
tp->t_state &= ~TS_FLUSH;
else {
if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED)
sc->sc_dhu[line].dhu_cc -= dhuaddr->dhu_tbufcnt;
ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc);
sc->sc_dhu[line].dhu_cc = 0;
}
sc->sc_dhu[line].dhu_state = STATE_IDLE;
if (tp->t_line)
(*linesw[tp->t_line].l_start)(tp);
else
dhustart(tp);
return;
}
int
dhuopen(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
register dhuregs *dhuaddr;
register struct tty *tp;
register int unit, line;
struct dhu_softc *sc;
int s, error = 0;
unit = DHU_M2U(minor(dev));
line = DHU_LINE(minor(dev));
if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL)
return (ENXIO);
sc = dhu_cd.cd_devs[unit];
if (line >= sc->sc_type)
return ENXIO;
tp = sc->sc_dhu[line].dhu_tty;
if (tp == NULL) {
tp = sc->sc_dhu[line].dhu_tty = ttymalloc();
if (tp == NULL)
return ENXIO;
sc->sc_dhu[line].dhu_state = STATE_IDLE;
sc->sc_dhu[line].dhu_txaddr =
uballoc((struct uba_softc *)sc->sc_dev.dv_parent,
tp->t_outq.c_cs, tp->t_outq.c_cn, 0);
dhuaddr = sc->sc_addr;
s = spltty();
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line);
sc->sc_dhu[line].dhu_modem = dhuaddr->dhu_stat;
(void) splx(s);
}
tp->t_oproc = dhustart;
tp->t_param = dhuparam;
tp->t_hwiflow = dhuiflow;
tp->t_dev = dev;
if ((tp->t_state & TS_ISOPEN) == 0) {
ttychars(tp);
if (tp->t_ispeed == 0) {
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
tp->t_cflag = TTYDEF_CFLAG;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
}
(void) dhuparam(tp, &tp->t_termios);
ttsetwater(tp);
} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
return (EBUSY);
/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD)
tp->t_state |= TS_CARR_ON;
s = spltty();
while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
!(tp->t_state & TS_CARR_ON)) {
tp->t_wopen++;
error = ttysleep(tp, (caddr_t)&tp->t_rawq,
TTIPRI | PCATCH, ttopen, 0);
tp->t_wopen--;
if (error)
break;
}
(void) splx(s);
if (error)
return (error);
return ((*linesw[tp->t_line].l_open)(dev, tp));
}
/*ARGSUSED*/
int
dhuclose(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
register struct tty *tp;
register int unit, line;
struct dhu_softc *sc;
unit = DHU_M2U(minor(dev));
line = DHU_LINE(minor(dev));
sc = dhu_cd.cd_devs[unit];
tp = sc->sc_dhu[line].dhu_tty;
(*linesw[tp->t_line].l_close)(tp, flag);
/* Make sure a BREAK state is not left enabled. */
(void) dhumctl(sc, line, DML_BRK, DMBIC);
/* Do a hangup if so required. */
if ((tp->t_cflag & HUPCL) || tp->t_wopen ||
!(tp->t_state & TS_ISOPEN))
(void) dhumctl(sc, line, 0, DMSET);
return (ttyclose(tp));
}
int
dhuread(dev, uio, flag)
dev_t dev;
struct uio *uio;
{
register struct dhu_softc *sc;
register struct tty *tp;
sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
}
int
dhuwrite(dev, uio, flag)
dev_t dev;
struct uio *uio;
{
register struct dhu_softc *sc;
register struct tty *tp;
sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
}
/*ARGSUSED*/
int
dhuioctl(dev, cmd, data, flag, p)
dev_t dev;
u_long cmd;
caddr_t data;
int flag;
struct proc *p;
{
register struct dhu_softc *sc;
register struct tty *tp;
register int unit, line;
int error;
unit = DHU_M2U(minor(dev));
line = DHU_LINE(minor(dev));
sc = dhu_cd.cd_devs[unit];
tp = sc->sc_dhu[line].dhu_tty;
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
error = ttioctl(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
switch (cmd) {
case TIOCSBRK:
(void) dhumctl(sc, line, DML_BRK, DMBIS);
break;
case TIOCCBRK:
(void) dhumctl(sc, line, DML_BRK, DMBIC);
break;
case TIOCSDTR:
(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS);
break;
case TIOCCDTR:
(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC);
break;
case TIOCMSET:
(void) dhumctl(sc, line, *(int *)data, DMSET);
break;
case TIOCMBIS:
(void) dhumctl(sc, line, *(int *)data, DMBIS);
break;
case TIOCMBIC:
(void) dhumctl(sc, line, *(int *)data, DMBIC);
break;
case TIOCMGET:
*(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK);
break;
default:
return (ENOTTY);
}
return (0);
}
struct tty *
dhutty(dev)
dev_t dev;
{
struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
return (tp);
}
/*ARGSUSED*/
void
dhustop(tp, flag)
register struct tty *tp;
{
register struct dhu_softc *sc;
register dhuregs *dhuaddr;
register int line;
int s;
s = spltty();
if (tp->t_state & TS_BUSY) {
sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
line = DHU_LINE(minor(tp->t_dev));
if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) {
sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED;
dhuaddr = sc->sc_addr;
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line);
dhuaddr->dhu_lnctrl |= DHU_LNCTRL_DMA_ABORT;
}
if (!(tp->t_state & TS_TTSTOP))
tp->t_state |= TS_FLUSH;
}
(void) splx(s);
}
static void
dhustart(tp)
register struct tty *tp;
{
register struct dhu_softc *sc;
register dhuregs *dhuaddr;
register int line, cc;
register int addr;
int s;
s = spltty();
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
goto out;
if (tp->t_outq.c_cc <= tp->t_lowat) {
if (tp->t_state & TS_ASLEEP) {
tp->t_state &= ~TS_ASLEEP;
wakeup((caddr_t)&tp->t_outq);
}
selwakeup(&tp->t_wsel);
}
if (tp->t_outq.c_cc == 0)
goto out;
cc = ndqb(&tp->t_outq, 0);
if (cc == 0)
goto out;
tp->t_state |= TS_BUSY;
sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
line = DHU_LINE(minor(tp->t_dev));
dhuaddr = sc->sc_addr;
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line);
sc->sc_dhu[line].dhu_cc = cc;
if (cc == 1) {
sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR;
dhuaddr->dhu_txchar = DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf;
} else {
sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING;
addr = UBAI_ADDR(sc->sc_dhu[line].dhu_txaddr) +
(tp->t_outq.c_cf - tp->t_outq.c_cs);
dhuaddr->dhu_tbufcnt = cc;
dhuaddr->dhu_tbufad1 = (addr & 0xFFFF);
dhuaddr->dhu_tbufad2 = ((addr>>16) & 0x3F) |
DHU_TBUFAD2_TX_ENABLE;
dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_DMA_ABORT;
dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_DMA_START;
}
out:
(void) splx(s);
return;
}
static int
dhuparam(tp, t)
register struct tty *tp;
register struct termios *t;
{
struct dhu_softc *sc;
register dhuregs *dhuaddr;
register int cflag = t->c_cflag;
int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab);
int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab);
register unsigned lpr, lnctrl;
int unit, line;
int s;
unit = DHU_M2U(minor(tp->t_dev));
line = DHU_LINE(minor(tp->t_dev));
sc = dhu_cd.cd_devs[unit];
/* check requested parameters */
if (ospeed < 0 || ispeed < 0)
return (EINVAL);
tp->t_ispeed = t->c_ispeed;
tp->t_ospeed = t->c_ospeed;
tp->t_cflag = cflag;
if (ospeed == 0) {
(void) dhumctl(sc, line, 0, DMSET); /* hang up line */
return (0);
}
s = spltty();
dhuaddr = sc->sc_addr;
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line);
lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ;
switch (cflag & CSIZE) {
case CS5:
lpr |= DHU_LPR_5_BIT_CHAR;
break;
case CS6:
lpr |= DHU_LPR_6_BIT_CHAR;
break;
case CS7:
lpr |= DHU_LPR_7_BIT_CHAR;
break;
default:
lpr |= DHU_LPR_8_BIT_CHAR;
break;
}
if (cflag & PARENB)
lpr |= DHU_LPR_PARENB;
if (!(cflag & PARODD))
lpr |= DHU_LPR_EPAR;
if (cflag & CSTOPB)
lpr |= DHU_LPR_2_STOP;
dhuaddr->dhu_lpr = lpr;
dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_TX_ENABLE;
lnctrl = dhuaddr->dhu_lnctrl;
/* Setting LINK.TYPE enables modem signal change interrupts. */
lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE);
/* Enable the auto XON/XOFF feature on the controller */
if (t->c_iflag & IXON)
lnctrl |= DHU_LNCTRL_OAUTO;
else
lnctrl &= ~DHU_LNCTRL_OAUTO;
if (t->c_iflag & IXOFF)
lnctrl |= DHU_LNCTRL_IAUTO;
else
lnctrl &= ~DHU_LNCTRL_IAUTO;
dhuaddr->dhu_lnctrl = lnctrl;
(void) splx(s);
return (0);
}
static int
dhuiflow(tp, flag)
struct tty *tp;
int flag;
{
register struct dhu_softc *sc;
register int line = DHU_LINE(minor(tp->t_dev));
if (tp->t_cflag & CRTSCTS) {
sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
(void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS));
return (1);
}
return (0);
}
static unsigned
dhumctl(sc, line, bits, how)
struct dhu_softc *sc;
int line, bits, how;
{
register dhuregs *dhuaddr;
register unsigned status;
register unsigned lnctrl;
register unsigned mbits;
int s;
s = spltty();
dhuaddr = sc->sc_addr;
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line);
mbits = 0;
/* external signals as seen from the port */
status = dhuaddr->dhu_stat;
if (status & DHU_STAT_CTS)
mbits |= DML_CTS;
if (status & DHU_STAT_DCD)
mbits |= DML_DCD;
if (status & DHU_STAT_DSR)
mbits |= DML_DSR;
if (status & DHU_STAT_RI)
mbits |= DML_RI;
/* internal signals/state delivered to port */
lnctrl = dhuaddr->dhu_lnctrl;
if (lnctrl & DHU_LNCTRL_RTS)
mbits |= DML_RTS;
if (lnctrl & DHU_LNCTRL_DTR)
mbits |= DML_DTR;
if (lnctrl & DHU_LNCTRL_BREAK)
mbits |= DML_BRK;
switch (how) {
case DMSET:
mbits = bits;
break;
case DMBIS:
mbits |= bits;
break;
case DMBIC:
mbits &= ~bits;
break;
case DMGET:
(void) splx(s);
return (mbits);
}
if (mbits & DML_RTS)
lnctrl |= DHU_LNCTRL_RTS;
else
lnctrl &= ~DHU_LNCTRL_RTS;
if (mbits & DML_DTR)
lnctrl |= DHU_LNCTRL_DTR;
else
lnctrl &= ~DHU_LNCTRL_DTR;
if (mbits & DML_BRK)
lnctrl |= DHU_LNCTRL_BREAK;
else
lnctrl &= ~DHU_LNCTRL_BREAK;
dhuaddr->dhu_lnctrl = lnctrl;
(void) splx(s);
return (mbits);
}

140
sys/arch/vax/uba/dhureg.h
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@ -1,140 +0,0 @@
/* $NetBSD: dhureg.h,v 1.2 1996/03/17 22:51:50 ragge Exp $ */
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
union w_b
{
u_short word;
struct {
u_char byte_lo;
u_char byte_hi;
} bytes;
};
struct DHUregs
{
volatile union w_b u_csr; /* Control/Status Register (R/W) */
volatile u_short dhu_rbuf; /* Receive Buffer (R only) */
#define dhu_txchar dhu_rbuf /* Transmit Character (W only) */
volatile u_short dhu_lpr; /* Line Parameter Register (R/W) */
volatile u_short dhu_stat; /* Line Status (R only) */
volatile u_short dhu_lnctrl; /* Line Control (R/W) */
volatile u_short dhu_tbufad1; /* Transmit Buffer Address 1 (R/W) */
volatile u_short dhu_tbufad2; /* Transmit Buffer Address 2 (R/W) */
volatile u_short dhu_tbufcnt; /* Transmit Buffer Count (R/W) */
};
#define dhu_csr u_csr.word
#define dhu_csr_lo u_csr.bytes.byte_lo
#define dhu_csr_hi u_csr.bytes.byte_hi
typedef struct DHUregs dhuregs;
/* CSR bits */
#define DHU_CSR_TX_ACTION 0100000
#define DHU_CSR_TXIE 0040000
#define DHU_CSR_DIAG_FAIL 0020000
#define DHU_CSR_TX_DMA_ERROR 0010000
#define DHU_CSR_TX_LINE_MASK 0007400
#define DHU_CSR_RX_DATA_AVAIL 0000200
#define DHU_CSR_RXIE 0000100
#define DHU_CSR_MASTER_RESET 0000040
#define DHU_CSR_UNUSED 0000020
#define DHU_CSR_CHANNEL_MASK 0000017
/* RBUF bits */
#define DHU_RBUF_DATA_VALID 0100000
#define DHU_RBUF_OVERRUN_ERR 0040000
#define DHU_RBUF_FRAMING_ERR 0020000
#define DHU_RBUF_PARITY_ERR 0010000
#define DHU_RBUF_RX_LINE_MASK 0007400
#define DHU_DIAG_CODE 0070001
#define DHU_MODEM_CODE 0070000
/* TXCHAR bits */
#define DHU_TXCHAR_DATA_VALID 0100000
/* LPR bits */
#define DHU_LPR_B50 0x0
#define DHU_LPR_B75 0x1
#define DHU_LPR_B110 0x2
#define DHU_LPR_B134 0x3
#define DHU_LPR_B150 0x4
#define DHU_LPR_B300 0x5
#define DHU_LPR_B600 0x6
#define DHU_LPR_B1200 0x7
#define DHU_LPR_B1800 0x8
#define DHU_LPR_B2000 0x9
#define DHU_LPR_B2400 0xA
#define DHU_LPR_B4800 0xB
#define DHU_LPR_B7200 0xC
#define DHU_LPR_B9600 0xD
#define DHU_LPR_B19200 0xE
#define DHU_LPR_B38400 0xF
#define DHU_LPR_5_BIT_CHAR 0000000
#define DHU_LPR_6_BIT_CHAR 0000010
#define DHU_LPR_7_BIT_CHAR 0000020
#define DHU_LPR_8_BIT_CHAR 0000030
#define DHU_LPR_PARENB 0000040
#define DHU_LPR_EPAR 0000100
#define DHU_LPR_2_STOP 0000200
/* STAT bits */
#define DHU_STAT_DSR 0100000
#define DHU_STAT_RI 0020000
#define DHU_STAT_DCD 0010000
#define DHU_STAT_CTS 0004000
#define DHU_STAT_DHU 0000400
/* LNCTRL bits */
#define DHU_LNCTRL_DMA_ABORT 0000001
#define DHU_LNCTRL_IAUTO 0000002
#define DHU_LNCTRL_RX_ENABLE 0000004
#define DHU_LNCTRL_BREAK 0000010
#define DHU_LNCTRL_OAUTO 0000020
#define DHU_LNCTRL_FORCE_XOFF 0000040
#define DHU_LNCTRL_LINK_TYPE 0000400
#define DHU_LNCTRL_DTR 0001000
#define DHU_LNCTRL_RTS 0010000
/* TBUFAD2 bits */
#define DHU_TBUFAD2_DMA_START 0000200
#define DHU_TBUFAD2_TX_ENABLE 0100000

524
sys/arch/vax/uba/dl.c
View File

@ -1,524 +0,0 @@
/* $NetBSD: dl.c,v 1.6 1999/01/19 21:04:48 ragge Exp $ */
/*-
* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1997 Ben Harris. All rights reserved.
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
* Copyright (c) 1982, 1986, 1990, 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* dl.c -- Device driver for the DL11 and DLV11 serial cards.
*
* OS-interface code derived from the dz and dca (hp300) drivers.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/map.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <machine/pte.h>
#include <machine/trap.h>
#include <machine/scb.h>
#include <vax/uba/ubareg.h>
#include <vax/uba/ubavar.h>
#include <vax/uba/dlreg.h>
#define DL_I2C(i) (i)
#define DL_C2I(c) (c)
struct dl_softc {
struct device sc_dev;
dlregs* sc_addr;
struct tty* sc_tty;
};
static int dl_match __P((struct device *, struct cfdata *, void *));
static void dl_attach __P((struct device *, struct device *, void *));
static void dlrint __P((int));
static void dlxint __P((int));
static void dlstart __P((struct tty *));
static int dlparam __P((struct tty *, struct termios *));
static void dlbrk __P((struct dl_softc *, int));
struct tty * dltty __P((dev_t));
int dlopen __P((dev_t, int, int, struct proc *));
int dlclose __P((dev_t, int, int, struct proc *));
int dlread __P((dev_t, struct uio *, int));
int dlwrite __P((dev_t, struct uio *, int));
int dlioctl __P((dev_t, int, caddr_t, int, struct proc *));
void dlstop __P((struct tty *, int));
struct cfattach dl_ca = {
sizeof(struct dl_softc), dl_match, dl_attach
};
extern struct cfdriver dl_cd;
/* Autoconfig handles: setup the controller to interrupt, */
/* then complete the housecleaning for full operation */
static int
dl_match (parent, cf, aux)
struct device * parent;
struct cfdata *cf;
void *aux;
{
struct uba_attach_args *ua = aux;
register dlregs *dladdr;
dladdr = (dlregs*) ua->ua_addr;
#ifdef DL_DEBUG
printf("Probing for dl at %lo ... ", (long)dladdr);
#endif
dladdr->dl_xcsr = DL_XCSR_TXIE;
if (dladdr->dl_xcsr != (DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
printf("failed (step 1; XCSR = %.4b)\n", dladdr->dl_xcsr,
DL_XCSR_BITS);
#endif
return 0;
}
/*
* We have to force an interrupt so the uba driver can work
* out where we are. Unfortunately, the only way to make a
* DL11 interrupt is to get it to send or receive a
* character. We'll send a NUL and hope it doesn't hurt
* anything.
*/
dladdr->u_xbuf.bytes.byte_lo = '\0';
#if 0 /* This test seems to fail 2/3 of the time :-( */
if (dladdr->dl_xcsr != (DL_XCSR_TXIE)) {
#ifdef DL_DEBUG
printf("failed (step 2; XCSR = %.4b)\n", dladdr->dl_xcsr,
DL_XCSR_BITS);
#endif
return 0;
}
#endif
DELAY(100000); /* delay 1/10 s for character to transmit */
if (dladdr->dl_xcsr != (DL_XCSR_TXIE | DL_XCSR_TX_READY)) {
#ifdef DL_DEBUG
printf("failed (step 3; XCSR = %.4b)\n", dladdr->dl_xcsr,
DL_XCSR_BITS);
#endif
return 0;
}
/* Register the TX interrupt handler */
ua->ua_ivec = dlxint;
/* What else do I need to do? */
return 1;
}
static void
dl_attach (parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct dl_softc *sc = (void *)self;
register struct uba_attach_args *ua = aux;
register dlregs *dladdr;
dladdr = (dlregs *) ua->ua_addr;
sc->sc_addr = dladdr;
/* Tidy up the device */
dladdr->dl_rcsr = DL_RCSR_RXIE;
dladdr->dl_xcsr = DL_XCSR_TXIE;
/* Initialize our softc structure. Should be done in open? */
sc->sc_tty = ttymalloc();
tty_attach(sc->sc_tty);
/* Now register the RX interrupt handler */
scb_vecalloc(ua->ua_cvec - 4, dlrint, self->dv_unit, SCB_ISTACK);
printf("\n");
}
/* Receiver Interrupt Handler */
static void
dlrint(cntlr)
int cntlr;
{
struct dl_softc *sc = dl_cd.cd_devs[cntlr];
volatile dlregs *dladdr;
register struct tty *tp;
register int cc;
register unsigned c;
dladdr = sc->sc_addr;
if (dladdr->dl_rcsr & DL_RCSR_RX_DONE) {
c = dladdr->dl_rbuf;
cc = c & 0xFF;
tp = sc->sc_tty;
if (!(tp->t_state & TS_ISOPEN)) {
wakeup((caddr_t)&tp->t_rawq);
return;
}
if (c & DL_RBUF_OVERRUN_ERR)
/*
* XXX: This should really be logged somwhere
* else where we can afford the time.
*/
log(LOG_WARNING, "%s: rx overrun\n",
sc->sc_dev.dv_xname);
if (c & DL_RBUF_FRAMING_ERR)
cc |= TTY_FE;
if (c & DL_RBUF_PARITY_ERR)
cc |= TTY_PE;
(*linesw[tp->t_line].l_rint)(cc, tp);
} else
log(LOG_WARNING, "%s: stray rx interrupt\n",
sc->sc_dev.dv_xname);
return;
}
/* Transmitter Interrupt Handler */
static void
dlxint(cntlr)
int cntlr;
{
struct dl_softc *sc = dl_cd.cd_devs[cntlr];
volatile dlregs *dladdr;
register struct tty *tp;
dladdr = sc->sc_addr;
tp = sc->sc_tty;
tp->t_state &= ~(TS_BUSY | TS_FLUSH);
if (tp->t_line)
(*linesw[tp->t_line].l_start)(tp);
else
dlstart(tp);
return;
}
int
dlopen(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
register struct tty *tp;
register int unit;
struct dl_softc *sc;
unit = DL_I2C(minor(dev));
if (unit >= dl_cd.cd_ndevs || dl_cd.cd_devs[unit] == NULL)
return ENXIO;
sc = dl_cd.cd_devs[unit];
tp = sc->sc_tty;
if (tp == NULL)
return ENODEV;
tp->t_oproc = dlstart;
tp->t_param = dlparam;
tp->t_dev = dev;
if (!(tp->t_state & TS_ISOPEN)) {
ttychars(tp);
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
/* No modem control, so set CLOCAL. */
tp->t_cflag = TTYDEF_CFLAG | CLOCAL;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
dlparam(tp, &tp->t_termios);
ttsetwater(tp);
} else if ((tp->t_state & TS_XCLUDE) && p->p_ucred->cr_uid != 0)
return EBUSY;
return ((*linesw[tp->t_line].l_open)(dev, tp));
}
/*ARGSUSED*/
int
dlclose(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
struct dl_softc *sc;
register struct tty *tp;
register int unit;
unit = DL_I2C(minor(dev));
sc = dl_cd.cd_devs[unit];
tp = sc->sc_tty;
(*linesw[tp->t_line].l_close)(tp, flag);
/* Make sure a BREAK state is not left enabled. */
dlbrk(sc, 0);
return (ttyclose(tp));
}
int
dlread(dev, uio, flag)
dev_t dev;
struct uio *uio;
int flag;
{
register struct tty *tp;
struct dl_softc *sc;
register int unit;
unit = DL_I2C(minor(dev));
sc = dl_cd.cd_devs[unit];
tp = sc->sc_tty;
return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
}
int
dlwrite(dev, uio, flag)
dev_t dev;
struct uio *uio;
int flag;
{
register struct tty *tp;
struct dl_softc *sc;
register int unit;
unit = DL_I2C(minor(dev));
sc = dl_cd.cd_devs[unit];
tp = sc->sc_tty;
return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
}
int
dlioctl(dev, cmd, data, flag, p)
dev_t dev;
int cmd;
caddr_t data;
int flag;
struct proc *p;
{
struct dl_softc *sc;
register struct tty *tp;
register int unit;
int error;
unit = DL_I2C(minor(dev));
sc = dl_cd.cd_devs[unit];
tp = sc->sc_tty;
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
error = ttioctl(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
switch (cmd) {
case TIOCSBRK:
dlbrk(sc, 1);
break;
case TIOCCBRK:
dlbrk(sc, 0);
break;
case TIOCMGET:
/* No modem control, assume they're all low. */
*(int *)data = 0;
break;
default:
return (ENOTTY);
}
return (0);
}
struct tty *
dltty(dev)
dev_t dev;
{
register struct dl_softc* sc;
sc = dl_cd.cd_devs[DL_I2C(minor(dev))];
return sc->sc_tty;
}
void
dlstop(tp, flag)
register struct tty *tp;
int flag;
{
register struct dl_softc *sc;
int unit, s;
unit = DL_I2C(minor(tp->t_dev));
sc = dl_cd.cd_devs[unit];
s = spltty();
if (tp->t_state & TS_BUSY)
if (!(tp->t_state & TS_TTSTOP))
tp->t_state |= TS_FLUSH;
splx(s);
}
static void
dlstart(tp)
register struct tty *tp;
{
register struct dl_softc *sc;
register dlregs *dladdr;
register int unit;
int s;
unit = DL_I2C(minor(tp->t_dev));
sc = dl_cd.cd_devs[unit];
s = spltty();
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
goto out;
if (tp->t_outq.c_cc <= tp->t_lowat) {
if (tp->t_state & TS_ASLEEP) {
tp->t_state &= ~TS_ASLEEP;
wakeup((caddr_t)&tp->t_outq);
}
selwakeup(&tp->t_wsel);
}
if (tp->t_outq.c_cc == 0)
goto out;
dladdr = sc->sc_addr;
if (dladdr->dl_xcsr & DL_XCSR_TX_READY) {
tp->t_state |= TS_BUSY;
dladdr->u_xbuf.bytes.byte_lo = getc(&tp->t_outq);
}
out:
splx(s);
return;
}
/*ARGSUSED*/
static int
dlparam(tp, t)
register struct tty *tp;
register struct termios *t;
{
/*
* All this kind of stuff (speed, character format, whatever)
* is set by jumpers on the card. Changing it is thus rather
* tricky for a mere device driver.
*/
return 0;
}
static void
dlbrk(sc, state)
register struct dl_softc *sc;
int state;
{
register dlregs *dladdr;
int s;
dladdr = sc->sc_addr;
s = spltty();
if (state)
dladdr->dl_xcsr |= DL_XCSR_TX_BREAK;
else
dladdr->dl_xcsr &= ~DL_XCSR_TX_BREAK;
splx(s);
}

82
sys/arch/vax/uba/dlreg.h
View File

@ -1,82 +0,0 @@
/* $NetBSD: dlreg.h,v 1.1 1997/02/04 19:13:19 ragge Exp $ */
/*
* Copyright (c) 1997 Ben Harris. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ben Harris.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* dlreg.h -- Definitions for the DL11 and DLV11 serial cards.
*
* Style in imitation of dzreg.h.
*/
union w_b
{
u_short word;
struct {
u_char byte_lo;
u_char byte_hi;
} bytes;
};
struct DLregs
{
volatile u_short dl_rcsr; /* Receive Control/Status Register (R/W) */
volatile u_short dl_rbuf; /* Receive Buffer (R) */
volatile u_short dl_xcsr; /* Transmit Control/Status Register (R/W) */
volatile union w_b u_xbuf; /* Transmit Buffer (W) */
#define dl_xbuf u_xbuf.bytes.byte_lo
};
typedef struct DLregs dlregs;
/* RCSR bits */
#define DL_RCSR_RX_DONE 0x0080 /* Receiver Done (R) */
#define DL_RCSR_RXIE 0x0040 /* Receiver Interrupt Enable (R/W) */
#define DL_RCSR_READER_ENABLE 0x0001 /* [paper-tape] Reader Enable (W) */
#define DL_RCSR_BITS "\20\1READER_ENABLE\7RXIE\10RX_DONE\n"
/* RBUF bits */
#define DL_RBUF_ERR 0x8000 /* Error (R) */
#define DL_RBUF_OVERRUN_ERR 0x4000 /* Overrun Error (R) */
#define DL_RBUF_FRAMING_ERR 0x2000 /* Framing Error (R) */
#define DL_RBUF_PARITY_ERR 0x1000 /* Parity Error (R) */
#define DL_RBUF_DATA_MASK 0x00FF /* Receive Data (R) */
#define DL_RBUF_BITS "\20\15PARITY_ERR\16FRAMING_ERR\17OVERRUN_ERR\20ERR\n"
/* XCSR bits */
#define DL_XCSR_TX_READY 0x0080 /* Transmitter Ready (R) */
#define DL_XCSR_TXIE 0x0040 /* Transmit Interrupt Enable (R/W) */
#define DL_XCSR_TX_BREAK 0x0001 /* Transmit Break (R/W) */
#define DL_XCSR_BITS "\20\1TX_BREAK\7TXIE\10TX_READY\n"
/* XBUF is just data byte right justified. */

703
sys/arch/vax/uba/dz.c
View File

@ -1,703 +0,0 @@
/* $NetBSD: dz.c,v 1.14 1999/03/13 15:16:48 ragge Exp $ */
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/map.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#ifdef DDB
#include <dev/cons.h>
#endif
#include <machine/pte.h>
#include <machine/trap.h>
#include <machine/cpu.h>
#include <vax/uba/ubareg.h>
#include <vax/uba/ubavar.h>
#include <vax/uba/dzreg.h>
#include <vax/uba/dzvar.h>
#include "ioconf.h"
/* A DZ-11 has 8 ports while a DZV/DZQ-11 has only 4. We use 8 by default */
#define NDZLINE 8
#define DZ_C2I(c) ((c)<<3) /* convert controller # to index */
#define DZ_I2C(c) ((c)>>3) /* convert minor to controller # */
#define DZ_PORT(u) ((u)&07) /* extract the port # */
/* Flags used to monitor modem bits, make them understood outside driver */
#define DML_DTR TIOCM_DTR
#define DML_DCD TIOCM_CD
#define DML_RI TIOCM_RI
#define DML_BRK 0100000 /* no equivalent, we will mask */
static struct speedtab dzspeedtab[] =
{
{ 0, 0 },
{ 50, DZ_LPR_B50 },
{ 75, DZ_LPR_B75 },
{ 110, DZ_LPR_B110 },
{ 134, DZ_LPR_B134 },
{ 150, DZ_LPR_B150 },
{ 300, DZ_LPR_B300 },
{ 600, DZ_LPR_B600 },
{ 1200, DZ_LPR_B1200 },
{ 1800, DZ_LPR_B1800 },
{ 2000, DZ_LPR_B2000 },
{ 2400, DZ_LPR_B2400 },
{ 3600, DZ_LPR_B3600 },
{ 4800, DZ_LPR_B4800 },
{ 7200, DZ_LPR_B7200 },
{ 9600, DZ_LPR_B9600 },
{ 19200, DZ_LPR_B19200 },
{ -1, -1 }
};
static void dzstart __P((struct tty *));
static int dzparam __P((struct tty *, struct termios *));
static unsigned dzmctl __P((struct dz_softc *, int, int, int));
static void dzscan __P((void *));
cdev_decl(dz);
/*
* The DZ series doesn't interrupt on carrier transitions,
* so we have to use a timer to watch it.
*/
int dz_timer = 0; /* true if timer started */
#define DZ_DZ 8 /* Unibus DZ-11 board linecount */
#define DZ_DZV 4 /* Q-bus DZV-11 or DZQ-11 */
void
dzattach(sc)
struct dz_softc *sc;
{
register int n;
sc->sc_rxint = sc->sc_brk = 0;
sc->sc_dr.dr_tcrw = (void *)sc->sc_dr.dr_tcr;
*sc->sc_dr.dr_csr = (DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
*sc->sc_dr.dr_dtr = 0; /* Make sure DTR bits are zero */
*sc->sc_dr.dr_break = 0; /* Status of BREAK bits, all off */
/* Initialize our softc structure. Should be done in open? */
for (n = 0; n < sc->sc_type; n++)
sc->sc_dz[n].dz_tty = ttymalloc();
/* Alas no interrupt on modem bit changes, so we manually scan */
if (dz_timer == 0) {
dz_timer = 1;
timeout(dzscan, (void *)0, hz);
}
printf("\n");
return;
}
/* Receiver Interrupt */
void
dzrint(cntlr)
int cntlr;
{
struct dz_softc *sc = dz_cd.cd_devs[cntlr];
register struct tty *tp;
register int cc, line;
register unsigned c;
int overrun = 0;
sc->sc_rxint++;
while ((c = *sc->sc_dr.dr_rbuf) & DZ_RBUF_DATA_VALID) {
cc = c & 0xFF;
line = DZ_PORT(c>>8);
tp = sc->sc_dz[line].dz_tty;
/* Must be caught early */
if (sc->sc_catch && (*sc->sc_catch)(line, cc))
continue;
if (!(tp->t_state & TS_ISOPEN)) {
wakeup((caddr_t)&tp->t_rawq);
continue;
}
if ((c & DZ_RBUF_OVERRUN_ERR) && overrun == 0) {
log(LOG_WARNING, "%s: silo overflow, line %d\n",
sc->sc_dev.dv_xname, line);
overrun = 1;
}
/* A BREAK key will appear as a NULL with a framing error */
if (c & DZ_RBUF_FRAMING_ERR)
cc |= TTY_FE;
if (c & DZ_RBUF_PARITY_ERR)
cc |= TTY_PE;
#if defined(DDB) && (defined(VAX410) || defined(VAX43) || defined(VAX46))
if (tp->t_dev == cn_tab->cn_dev) {
int j = kdbrint(cc);
if (j == 1) /* Escape received, just return */
continue;
if (j == 2) /* Second char wasn't 'D' */
(*linesw[tp->t_line].l_rint)(27, tp);
}
#endif
(*linesw[tp->t_line].l_rint)(cc, tp);
}
}
/* Transmitter Interrupt */
void
dzxint(cntlr)
int cntlr;
{
register struct dz_softc *sc = dz_cd.cd_devs[cntlr];
register struct tty *tp;
register struct clist *cl;
register int line, ch, csr;
u_char tcr;
/*
* Switch to POLLED mode.
* Some simple measurements indicated that even on
* one port, by freeing the scanner in the controller
* by either providing a character or turning off
* the port when output is complete, the transmitter
* was ready to accept more output when polled again.
* With just two ports running the game "worms,"
* almost every interrupt serviced both transmitters!
* Each UART is double buffered, so if the scanner
* is quick enough and timing works out, we can even
* feed the same port twice.
*
* Ragge 980517:
* Do not need to turn off interrupts, already at interrupt level.
* Remove the pdma stuff; no great need of it right now.
*/
while (((csr = *sc->sc_dr.dr_csr) & DZ_CSR_TX_READY) != 0) {
line = DZ_PORT(csr>>8);
tp = sc->sc_dz[line].dz_tty;
cl = &tp->t_outq;
tp->t_state &= ~TS_BUSY;
/* Just send out a char if we have one */
/* As long as we can fill the chip buffer, we just loop here */
if (cl->c_cc) {
tp->t_state |= TS_BUSY;
ch = getc(cl);
*sc->sc_dr.dr_tbuf = ch;
continue;
}
/* Nothing to send; clear the scan bit */
/* Clear xmit scanner bit; dzstart may set it again */
tcr = *sc->sc_dr.dr_tcrw & 255;
tcr &= ~(1 << line);
*sc->sc_dr.dr_tcr = tcr;
if (tp->t_state & TS_FLUSH)
tp->t_state &= ~TS_FLUSH;
else
ndflush (&tp->t_outq, cl->c_cc);
if (tp->t_line)
(*linesw[tp->t_line].l_start)(tp);
else
dzstart(tp);
}
}
int
dzopen(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
register struct tty *tp;
register int unit, line;
struct dz_softc *sc;
int s, error = 0;
unit = DZ_I2C(minor(dev));
line = DZ_PORT(minor(dev));
if (unit >= dz_cd.cd_ndevs || dz_cd.cd_devs[unit] == NULL)
return (ENXIO);
sc = dz_cd.cd_devs[unit];
if (line >= sc->sc_type)
return ENXIO;
tp = sc->sc_dz[line].dz_tty;
if (tp == NULL)
return (ENODEV);
tp->t_oproc = dzstart;
tp->t_param = dzparam;
tp->t_dev = dev;
if ((tp->t_state & TS_ISOPEN) == 0) {
ttychars(tp);
if (tp->t_ispeed == 0) {
tp->t_iflag = TTYDEF_IFLAG;
tp->t_oflag = TTYDEF_OFLAG;
tp->t_cflag = TTYDEF_CFLAG;
tp->t_lflag = TTYDEF_LFLAG;
tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
}
(void) dzparam(tp, &tp->t_termios);
ttsetwater(tp);
} else if ((tp->t_state & TS_XCLUDE) && p->p_ucred->cr_uid != 0)
return (EBUSY);
/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
if (dzmctl(sc, line, DML_DTR, DMBIS) & DML_DCD)
tp->t_state |= TS_CARR_ON;
s = spltty();
while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
!(tp->t_state & TS_CARR_ON)) {
tp->t_wopen++;
error = ttysleep(tp, (caddr_t)&tp->t_rawq,
TTIPRI | PCATCH, ttopen, 0);
tp->t_wopen--;
if (error)
break;
}
(void) splx(s);
if (error)
return (error);
return ((*linesw[tp->t_line].l_open)(dev, tp));
}
/*ARGSUSED*/
int
dzclose(dev, flag, mode, p)
dev_t dev;
int flag, mode;
struct proc *p;
{
struct dz_softc *sc;
register struct tty *tp;
register int unit, line;
unit = DZ_I2C(minor(dev));
line = DZ_PORT(minor(dev));
sc = dz_cd.cd_devs[unit];
tp = sc->sc_dz[line].dz_tty;
(*linesw[tp->t_line].l_close)(tp, flag);
/* Make sure a BREAK state is not left enabled. */
(void) dzmctl(sc, line, DML_BRK, DMBIC);
/* Do a hangup if so required. */
if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN))
(void) dzmctl(sc, line, 0, DMSET);
return (ttyclose(tp));
}
int
dzread (dev, uio, flag)
dev_t dev;
struct uio *uio;
{
register struct tty *tp;
struct dz_softc *sc;
sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
}
int
dzwrite (dev, uio, flag)
dev_t dev;
struct uio *uio;
{
register struct tty *tp;
struct dz_softc *sc;
sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
}
/*ARGSUSED*/
int
dzioctl (dev, cmd, data, flag, p)
dev_t dev;
u_long cmd;
caddr_t data;
int flag;
struct proc *p;
{
struct dz_softc *sc;
register struct tty *tp;
register int unit, line;
int error;
unit = DZ_I2C(minor(dev));
line = DZ_PORT(minor(dev));
sc = dz_cd.cd_devs[unit];
tp = sc->sc_dz[line].dz_tty;
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
error = ttioctl(tp, cmd, data, flag, p);
if (error >= 0)
return (error);
switch (cmd) {
case TIOCSBRK:
(void) dzmctl(sc, line, DML_BRK, DMBIS);
break;
case TIOCCBRK:
(void) dzmctl(sc, line, DML_BRK, DMBIC);
break;
case TIOCSDTR:
(void) dzmctl(sc, line, DML_DTR, DMBIS);
break;
case TIOCCDTR:
(void) dzmctl(sc, line, DML_DTR, DMBIC);
break;
case TIOCMSET:
(void) dzmctl(sc, line, *(int *)data, DMSET);
break;
case TIOCMBIS:
(void) dzmctl(sc, line, *(int *)data, DMBIS);
break;
case TIOCMBIC:
(void) dzmctl(sc, line, *(int *)data, DMBIC);
break;
case TIOCMGET:
*(int *)data = (dzmctl(sc, line, 0, DMGET) & ~DML_BRK);
break;
default:
return (ENOTTY);
}
return (0);
}
struct tty *
dztty (dev)
dev_t dev;
{
struct dz_softc *sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
struct tty *tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
return (tp);
}
/*ARGSUSED*/
void
dzstop(tp, flag)
register struct tty *tp;
{
if (tp->t_state & TS_BUSY)
if (!(tp->t_state & TS_TTSTOP))
tp->t_state |= TS_FLUSH;
}
void
dzstart(tp)
register struct tty *tp;
{
register struct dz_softc *sc;
register struct clist *cl;
register int unit, line, s;
char state;
unit = DZ_I2C(minor(tp->t_dev));
line = DZ_PORT(minor(tp->t_dev));
sc = dz_cd.cd_devs[unit];
s = spltty();
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
return;
cl = &tp->t_outq;
if (cl->c_cc <= tp->t_lowat) {
if (tp->t_state & TS_ASLEEP) {
tp->t_state &= ~TS_ASLEEP;
wakeup((caddr_t)cl);
}
selwakeup(&tp->t_wsel);
}
if (cl->c_cc == 0)
return;
tp->t_state |= TS_BUSY;
state = (*sc->sc_dr.dr_tcrw) & 255;
if ((state & (1 << line)) == 0) {
*sc->sc_dr.dr_tcr = state | (1 << line);
}
dzxint(sc->sc_dev.dv_unit);
splx(s);
}
static int
dzparam(tp, t)
register struct tty *tp;
register struct termios *t;
{
struct dz_softc *sc;
register int cflag = t->c_cflag;
int unit, line;
int ispeed = ttspeedtab(t->c_ispeed, dzspeedtab);
int ospeed = ttspeedtab(t->c_ospeed, dzspeedtab);
register unsigned lpr;
int s;
unit = DZ_I2C(minor(tp->t_dev));
line = DZ_PORT(minor(tp->t_dev));
sc = dz_cd.cd_devs[unit];
/* check requested parameters */
if (ospeed < 0 || ispeed < 0 || ispeed != ospeed)
return (EINVAL);
tp->t_ispeed = t->c_ispeed;
tp->t_ospeed = t->c_ospeed;
tp->t_cflag = cflag;
if (ospeed == 0) {
(void) dzmctl(sc, line, 0, DMSET); /* hang up line */
return (0);
}
s = spltty();
lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line;
switch (cflag & CSIZE)
{
case CS5:
lpr |= DZ_LPR_5_BIT_CHAR;
break;
case CS6:
lpr |= DZ_LPR_6_BIT_CHAR;
break;
case CS7:
lpr |= DZ_LPR_7_BIT_CHAR;
break;
default:
lpr |= DZ_LPR_8_BIT_CHAR;
break;
}
if (cflag & PARENB)
lpr |= DZ_LPR_PARENB;
if (cflag & PARODD)
lpr |= DZ_LPR_OPAR;
if (cflag & CSTOPB)
lpr |= DZ_LPR_2_STOP;
*sc->sc_dr.dr_lpr = lpr;
(void) splx(s);
return (0);
}
static unsigned
dzmctl(sc, line, bits, how)
register struct dz_softc *sc;
int line, bits, how;
{
register unsigned status;
register unsigned mbits;
register unsigned bit;
int s;
s = spltty();
mbits = 0;
bit = (1 << line);
/* external signals as seen from the port */
status = (*sc->sc_dr.dr_dcd | sc->sc_dsr);
if (status & bit)
mbits |= DML_DCD;
status = *sc->sc_dr.dr_ring;
if (status & bit)
mbits |= DML_RI;
/* internal signals/state delivered to port */
status = *sc->sc_dr.dr_dtr;
if (status & bit)
mbits |= DML_DTR;
if (sc->sc_brk & bit)
mbits |= DML_BRK;
switch (how)
{
case DMSET:
mbits = bits;
break;
case DMBIS:
mbits |= bits;
break;
case DMBIC:
mbits &= ~bits;
break;
case DMGET:
(void) splx(s);
return (mbits);
}
if (mbits & DML_DTR)
*sc->sc_dr.dr_dtr |= bit;
else
*sc->sc_dr.dr_dtr &= ~bit;
if (mbits & DML_BRK)
*sc->sc_dr.dr_break = (sc->sc_brk |= bit);
else
*sc->sc_dr.dr_break = (sc->sc_brk &= ~bit);
(void) splx(s);
return (mbits);
}
/*
* This is called by timeout() periodically.
* Check to see if modem status bits have changed.
*/
static void
dzscan(arg)
void *arg;
{
register struct dz_softc *sc;
register struct tty *tp;
register int n, bit, port;
unsigned csr;
int s;
s = spltty();
for (n = 0; n < dz_cd.cd_ndevs; n++) {
if (dz_cd.cd_devs[n] == NULL)
continue;
sc = dz_cd.cd_devs[n];
for (port = 0; port < sc->sc_type; port++) {
tp = sc->sc_dz[port].dz_tty;
bit = (1 << port);
if ((*sc->sc_dr.dr_dcd | sc->sc_dsr) & bit) {
if (!(tp->t_state & TS_CARR_ON))
(*linesw[tp->t_line].l_modem) (tp, 1);
} else if ((tp->t_state & TS_CARR_ON) &&
(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
*sc->sc_dr.dr_tcr =
((*sc->sc_dr.dr_tcrw)&255) & ~bit;
}
/*
* If the RX interrupt rate is this high, switch
* the controller to Silo Alarm - which means don't
* interrupt until the RX silo has 16 characters in
* it (the silo is 64 characters in all).
* Avoid oscillating SA on and off by not turning
* if off unless the rate is appropriately low.
*/
csr = *sc->sc_dr.dr_csr;
if (sc->sc_rxint > (16*10)) {
if ((csr & DZ_CSR_SAE) == 0)
*sc->sc_dr.dr_csr = (csr | DZ_CSR_SAE);
} else if ((csr & DZ_CSR_SAE) != 0)
if (sc->sc_rxint < 10)
*sc->sc_dr.dr_csr = (csr & ~(DZ_CSR_SAE));
sc->sc_rxint = 0;
}
(void) splx(s);
timeout(dzscan, (void *)0, hz);
return;
}

142
sys/arch/vax/uba/dz_uba.c
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@ -1,142 +0,0 @@
/* $NetBSD: dz_uba.c,v 1.3 1999/03/13 20:26:50 ragge Exp $ */
/*
* Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed at Ludd, University of
* Lule}, Sweden and its contributors.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
#include <sys/tty.h>
#include <sys/proc.h>
#include <sys/map.h>
#include <sys/buf.h>
#include <sys/conf.h>
#include <sys/file.h>
#include <sys/uio.h>
#include <sys/kernel.h>
#include <sys/syslog.h>
#include <sys/device.h>
#include <machine/pte.h>
#include <machine/trap.h>
#include <machine/scb.h>
#include <vax/uba/ubareg.h>
#include <vax/uba/ubavar.h>
#include <vax/uba/dzreg.h>
#include <vax/uba/dzvar.h>
#include "ioconf.h"
static int dz_uba_match __P((struct device *, struct cfdata *, void *));
static void dz_uba_attach __P((struct device *, struct device *, void *));
struct cfattach dz_uba_ca = {
sizeof(struct dz_softc), dz_uba_match, dz_uba_attach
};
/* Autoconfig handles: setup the controller to interrupt, */
/* then complete the housecleaning for full operation */
static int
dz_uba_match(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct uba_attach_args *ua = aux;
register dzregs *dzaddr;
register int n;
dzaddr = (dzregs *) ua->ua_addr;
/* Reset controller to initialize, enable TX interrupts */
/* to catch floating vector info elsewhere when completed */
dzaddr->dz_csr = (DZ_CSR_MSE | DZ_CSR_TXIE);
dzaddr->dz_tcr = 1; /* Force a TX interrupt */
DELAY(100000); /* delay 1/10 second */
dzaddr->dz_csr = DZ_CSR_RESET;
/* Now wait up to 3 seconds for reset/clear to complete. */
for (n = 0; n < 300; n++) {
DELAY(10000);
if ((dzaddr->dz_csr & DZ_CSR_RESET) == 0)
break;
}
/* If the RESET did not clear after 3 seconds, */
/* the controller must be broken. */
if (n >= 300)
return (0);
/* Register the TX interrupt handler */
ua->ua_ivec = dzxint;
return (1);
}
static void
dz_uba_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct dz_softc *sc = (void *)self;
register struct uba_attach_args *ua = aux;
register dzregs *da;
da = (dzregs *) ua->ua_addr;
sc->sc_dr.dr_csr = &da->dz_csr;
sc->sc_dr.dr_rbuf = &da->dz_rbuf;
sc->sc_dr.dr_dtr = &da->dz_dtr;
sc->sc_dr.dr_break = &da->dz_break;
sc->sc_dr.dr_tbuf = &da->dz_tbuf;
sc->sc_dr.dr_tcr = &da->dz_tcr;
sc->sc_dr.dr_dcd = &da->dz_dcd;
sc->sc_dr.dr_ring = &da->dz_ring;
#ifdef QBA
if (((struct uba_softc *)parent)->uh_type == QBA)
sc->sc_type = DZ_DZV;
else
#endif
sc->sc_type = DZ_DZ;
/* Now register the RX interrupt handler */
scb_vecalloc(ua->ua_cvec - 4, dzrint, self->dv_unit, SCB_ISTACK);
dzattach(sc);
}

120
sys/arch/vax/uba/dzreg.h
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@ -1,120 +0,0 @@
/* $NetBSD: dzreg.h,v 1.2 1998/05/17 18:51:13 ragge Exp $ */
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
union w_b
{
u_short word;
struct {
u_char byte_lo;
u_char byte_hi;
} bytes;
};
struct DZregs
{
volatile u_short dz_csr; /* Control/Status Register (R/W) */
volatile u_short dz_rbuf; /* Receive Buffer (R only) */
#define dz_lpr dz_rbuf /* Line Parameter Register (W only) */
volatile union w_b u_tcr; /* Transmit Control Register (R/W) */
volatile union w_b u_msr; /* Modem Status Register (R only) */
#define u_tdr u_msr /* Transmit Data Register (W only) */
};
#define dz_tcr u_tcr.bytes.byte_lo /* tx enable bits */
#define dz_dtr u_tcr.bytes.byte_hi /* DTR status bits */
#define dz_ring u_msr.bytes.byte_lo /* RI status bits */
#define dz_dcd u_msr.bytes.byte_hi /* DCD status bits */
#define dz_tbuf u_tdr.bytes.byte_lo /* transmit character */
#define dz_break u_tdr.bytes.byte_hi /* BREAK set/clr bits */
typedef struct DZregs dzregs;
struct dz_regs {
volatile unsigned short *dr_csr;
volatile unsigned short *dr_rbuf;
#define dr_lpr dr_rbuf
volatile unsigned char *dr_dtr;
volatile unsigned char *dr_break;
volatile unsigned char *dr_tbuf;
volatile unsigned char *dr_tcr;
volatile unsigned short *dr_tcrw;
volatile unsigned char *dr_ring;
volatile unsigned char *dr_dcd;
};
/* CSR bits */
#define DZ_CSR_TX_READY 0100000 /* Transmitter Ready */
#define DZ_CSR_TXIE 0040000 /* Transmitter Interrupt Enable */
#define DZ_CSR_SA 0020000 /* Silo Alarm */
#define DZ_CSR_SAE 0010000 /* Silo Alarm Enable */
#define DZ_CSR_TX_LINE_MASK 0007400 /* Which TX line */
#define DZ_CSR_RX_DONE 0000200 /* Receiver Done */
#define DZ_CSR_RXIE 0000100 /* Receiver Interrupt Enable */
#define DZ_CSR_MSE 0000040 /* Master Scan Enable */
#define DZ_CSR_RESET 0000020 /* Clear (reset) Controller */
#define DZ_CSR_MAINTENANCE 0000010
#define DZ_CSR_UNUSED 0000007
/* RBUF bits */
#define DZ_RBUF_DATA_VALID 0100000
#define DZ_RBUF_OVERRUN_ERR 0040000
#define DZ_RBUF_FRAMING_ERR 0020000
#define DZ_RBUF_PARITY_ERR 0010000
#define DZ_RBUF_RX_LINE_MASK 0007400
/* LPR bits */
#define DZ_LPR_UNUSED 0160000
#define DZ_LPR_RX_ENABLE 0010000
#define DZ_LPR_B50 0x0
#define DZ_LPR_B75 0x1
#define DZ_LPR_B110 0x2
#define DZ_LPR_B134 0x3
#define DZ_LPR_B150 0x4
#define DZ_LPR_B300 0x5
#define DZ_LPR_B600 0x6
#define DZ_LPR_B1200 0x7
#define DZ_LPR_B1800 0x8
#define DZ_LPR_B2000 0x9
#define DZ_LPR_B2400 0xA
#define DZ_LPR_B3600 0xB
#define DZ_LPR_B4800 0xC
#define DZ_LPR_B7200 0xD
#define DZ_LPR_B9600 0xE
#define DZ_LPR_B19200 0xF
#define DZ_LPR_OPAR 0000200
#define DZ_LPR_PARENB 0000100
#define DZ_LPR_2_STOP 0000040
#define DZ_LPR_5_BIT_CHAR 0000000
#define DZ_LPR_6_BIT_CHAR 0000010
#define DZ_LPR_7_BIT_CHAR 0000020
#define DZ_LPR_8_BIT_CHAR 0000030
#define DZ_LPR_CHANNEL_MASK 0000007

70
sys/arch/vax/uba/dzvar.h
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@ -1,70 +0,0 @@
/* $NetBSD: dzvar.h,v 1.3 1999/03/13 15:16:48 ragge Exp $ */
/*
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell and Rick Macklem.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* A DZ-11 has 8 ports while a DZV/DZQ-11 has only 4. We use 8 by default */
#define NDZLINE 8
#define DZ_DZ 8
#define DZ_DZV 4
#define DZ_DC 4
#define DZ_C2I(c) ((c)<<3) /* convert controller # to index */
#define DZ_I2C(c) ((c)>>3) /* convert minor to controller # */
#define DZ_PORT(u) ((u)&07) /* extract the port # */
struct dz_softc {
struct device sc_dev; /* Autoconf blaha */
struct dz_regs sc_dr; /* reg pointers */
int sc_type; /* DZ11 or DZV11? */
int sc_rxint; /* Receive interrupt count XXX */
u_char sc_brk; /* Break asserted on some lines */
u_char sc_dsr; /* DSR set bits if no mdm ctrl */
int (*sc_catch) __P((int, int)); /* Fast catch recv */
struct {
struct tty * dz_tty; /* what we work on */
#ifdef notyet
caddr_t dz_mem; /* pointers to clist output */
caddr_t dz_end; /* allowing pdma action */
#endif
} sc_dz[NDZLINE];
};
void dzattach __P((struct dz_softc *));
void dzrint __P((int));
void dzxint __P((int));

520
sys/arch/vax/uba/uda.c
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@ -1,520 +0,0 @@
/* $NetBSD: uda.c,v 1.28 1998/01/24 14:16:30 ragge Exp $ */
/*
* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
* Copyright (c) 1988 Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Chris Torek.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)uda.c 7.32 (Berkeley) 2/13/91
*/
/*
* UDA50 disk device driver
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <machine/sid.h>
#include <machine/pte.h>
#include <machine/cpu.h>
#include <vax/uba/ubareg.h>
#include <vax/uba/ubavar.h>
#include <vax/uba/udareg.h>
#include <vax/mscp/mscp.h>
#include <vax/mscp/mscpvar.h>
#include <vax/mscp/mscpreg.h>
/*
* Variants of SIMPLEQ macros for use with buf structs.
*/
#define BUFQ_INSERT_TAIL(head, elm) { \
(elm)->b_actf = NULL; \
*(head)->sqh_last = (elm); \
(head)->sqh_last = &(elm)->b_actf; \
}
#define BUFQ_REMOVE_HEAD(head, elm) { \
if (((head)->sqh_first = (elm)->b_actf) == NULL) \
(head)->sqh_last = &(head)->sqh_first; \
}
/*
* Software status, per controller.
*/
struct uda_softc {
struct device sc_dev; /* Autoconfig info */
struct uba_unit sc_unit; /* Struct common for UBA to communicate */
SIMPLEQ_HEAD(, buf) sc_bufq; /* bufs awaiting for resources */
struct mscp_pack *sc_uuda; /* Unibus address of uda struct */
struct mscp_pack sc_uda; /* Struct for uda communication */
struct udadevice *sc_udadev; /* pointer to ip/sa regs */
struct mscp *sc_mscp; /* Keep pointer to active mscp */
short sc_ipl; /* interrupt priority, Q-bus */
struct mscp_softc *sc_softc; /* MSCP info (per mscpvar.h) */
int sc_wticks; /* watchdog timer ticks */
};
static int udamatch __P((struct device *, struct cfdata *, void *));
static void udaattach __P((struct device *, struct device *, void *));
static void udareset __P((int));
static void mtcreset __P((int));
static void reset __P((struct uda_softc *));
static void udaintr __P((int));
static void mtcintr __P((int));
static void intr __P((struct uda_softc *));
int udaready __P((struct uba_unit *));
void udactlrdone __P((struct device *, int));
int udaprint __P((void *, const char *));
void udasaerror __P((struct device *, int));
int udago __P((struct device *, struct buf *));
extern struct cfdriver mtc_cd;
struct cfattach mtc_ca = {
sizeof(struct uda_softc), udamatch, udaattach
};
extern struct cfdriver uda_cd;
struct cfattach uda_ca = {
sizeof(struct uda_softc), udamatch, udaattach
};
/*
* More driver definitions, for generic MSCP code.
*/
struct mscp_ctlr uda_mscp_ctlr = {
udactlrdone,
udago,
udasaerror,
};
/*
* Miscellaneous private variables.
*/
static int ivec_no;
int
udaprint(aux, name)
void *aux;
const char *name;
{
if (name)
printf("%s: mscpbus", name);
return UNCONF;
}
/*
* Poke at a supposed UDA50 to see if it is there.
*/
int
udamatch(parent, cf, aux)
struct device *parent;
struct cfdata *cf;
void *aux;
{
struct uba_attach_args *ua = aux;
struct mscp_softc mi; /* Nice hack */
struct uba_softc *ubasc;
int tries;
#if QBA && notyet
extern volatile int rbr;
int s;
#endif
/* Get an interrupt vector. */
ubasc = (void *)parent;
ivec_no = ubasc->uh_lastiv - 4;
mi.mi_sa = &((struct udadevice *)ua->ua_addr)->udasa;
mi.mi_ip = &((struct udadevice *)ua->ua_addr)->udaip;
/*
* Initialise the controller (partially). The UDA50 programmer's
* manual states that if initialisation fails, it should be retried
* at least once, but after a second failure the port should be
* considered `down'; it also mentions that the controller should
* initialise within ten seconds. Or so I hear; I have not seen
* this manual myself.
*/
#if 0
s = spl6();
#endif
tries = 0;
again:
*mi.mi_ip = 0;
if (mscp_waitstep(&mi, MP_STEP1, MP_STEP1) == 0)
return 0; /* Nothing here... */
*mi.mi_sa = MP_ERR | (NCMDL2 << 11) | (NRSPL2 << 8) | MP_IE |
(ivec_no >> 2);
if (mscp_waitstep(&mi, MP_STEP2, MP_STEP2) == 0) {
printf("udaprobe: init step2 no change. sa=%x\n", *mi.mi_sa);
goto bad;
}
/* should have interrupted by now */
#if 0
rbr = qbgetpri();
#endif
if (strcmp(cf->cf_driver->cd_name, mtc_cd.cd_name)) {
ua->ua_ivec = udaintr;
ua->ua_reset = udareset;
} else {
ua->ua_ivec = mtcintr;
ua->ua_reset = mtcreset;
}
return 1;
bad:
if (++tries < 2)
goto again;
#if 0
splx(s);
#endif
return 0;
}
void
udaattach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct uda_softc *sc = (void *)self;
struct uba_attach_args *ua = aux;
struct uba_softc *uh = (void *)parent;
struct mscp_attach_args ma;
int ctlr, ubinfo;
printf("\n");
uh->uh_lastiv -= 4; /* remove dynamic interrupt vector */
#ifdef QBA
sc->sc_ipl = ua->ua_br;
#endif
ctlr = sc->sc_dev.dv_unit;
sc->sc_udadev = (struct udadevice *)ua->ua_addr;
SIMPLEQ_INIT(&sc->sc_bufq);
/*
* Fill in the uba_unit struct, so we can communicate with the uba.
*/
sc->sc_unit.uu_softc = sc; /* Backpointer to softc */
sc->sc_unit.uu_ready = udaready;/* go routine called from adapter */
sc->sc_unit.uu_keepbdp = vax_cputype == VAX_750 ? 1 : 0;
/*
* Map the communication area and command and
* response packets into Unibus space.
*/
ubinfo = uballoc((struct uba_softc *)sc->sc_dev.dv_parent,
(caddr_t) &sc->sc_uda, sizeof (struct mscp_pack), UBA_CANTWAIT);
#ifdef DIAGNOSTIC
if (ubinfo == 0) {
printf("%s: uballoc map failed\n", sc->sc_dev.dv_xname);
return;
}
#endif
sc->sc_uuda = (struct mscp_pack *) UBAI_ADDR(ubinfo);
bzero(&sc->sc_uda, sizeof (struct mscp_pack));
/*
* The only thing that differ UDA's and Tape ctlr's is
* their vcid. Beacuse there are no way to determine which
* ctlr type it is, we check what is generated and later
* set the correct vcid.
*/
ma.ma_type = (strcmp(self->dv_cfdata->cf_driver->cd_name,
mtc_cd.cd_name) ? MSCPBUS_DISK : MSCPBUS_TAPE);
ma.ma_mc = &uda_mscp_ctlr;
ma.ma_type |= MSCPBUS_UDA;
ma.ma_uuda = sc->sc_uuda;
ma.ma_uda = &sc->sc_uda;
ma.ma_softc = &sc->sc_softc;
ma.ma_ip = &sc->sc_udadev->udaip;
ma.ma_sa = ma.ma_sw = &sc->sc_udadev->udasa;
ma.ma_ivec = ivec_no;
ma.ma_ctlrnr = (ua->ua_iaddr == 0172150 ? 0 : 1); /* XXX */
ma.ma_adapnr = uh->uh_nr;
config_found(&sc->sc_dev, &ma, udaprint);
}
/*
* Start a transfer if there are free resources available, otherwise
* let it go in udaready, forget it for now.
*/
int
udago(usc, bp)
struct device *usc;
struct buf *bp;
{
struct uda_softc *sc = (void *)usc;
struct uba_unit *uu = &sc->sc_unit;
/*
* If we already are queued for resources, don't call ubaqueue
* again. (Then we would trash the wait queue). Just queue the
* buf and let the rest be done in udaready.
*/
if (sc->sc_bufq.sqh_first)
BUFQ_INSERT_TAIL(&sc->sc_bufq, bp)
else {
if (ubaqueue(uu, bp))
mscp_dgo(sc->sc_softc, (UBAI_ADDR(uu->uu_ubinfo) |
(UBAI_BDP(uu->uu_ubinfo) << 24)),uu->uu_ubinfo,bp);
else
BUFQ_INSERT_TAIL(&sc->sc_bufq, bp)
}
return 0;
}
/*
* Called if we have been blocked for resources, and resources
* have been freed again. Return 1 if we could start all
* transfers again, 0 if we still are waiting.
*/
int
udaready(uu)
struct uba_unit *uu;
{
struct uda_softc *sc = uu->uu_softc;
struct buf *bp;
while ((bp = sc->sc_bufq.sqh_first)) {
if (ubaqueue(uu, bp)) {
BUFQ_REMOVE_HEAD(&sc->sc_bufq, bp);
mscp_dgo(sc->sc_softc, (UBAI_ADDR(uu->uu_ubinfo) |
(UBAI_BDP(uu->uu_ubinfo) << 24)),uu->uu_ubinfo,bp);
} else
return 0;
}
return 1;
}
static struct saerr {
int code; /* error code (including UDA_ERR) */
char *desc; /* what it means: Efoo => foo error */
} saerr[] = {
{ 0100001, "Eunibus packet read" },
{ 0100002, "Eunibus packet write" },
{ 0100003, "EUDA ROM and RAM parity" },
{ 0100004, "EUDA RAM parity" },
{ 0100005, "EUDA ROM parity" },
{ 0100006, "Eunibus ring read" },
{ 0100007, "Eunibus ring write" },
{ 0100010, " unibus interrupt master failure" },
{ 0100011, "Ehost access timeout" },
{ 0100012, " host exceeded command limit" },
{ 0100013, " unibus bus master failure" },
{ 0100014, " DM XFC fatal error" },
{ 0100015, " hardware timeout of instruction loop" },
{ 0100016, " invalid virtual circuit id" },
{ 0100017, "Eunibus interrupt write" },
{ 0104000, "Efatal sequence" },
{ 0104040, " D proc ALU" },
{ 0104041, "ED proc control ROM parity" },
{ 0105102, "ED proc w/no BD#2 or RAM parity" },
{ 0105105, "ED proc RAM buffer" },
{ 0105152, "ED proc SDI" },
{ 0105153, "ED proc write mode wrap serdes" },
{ 0105154, "ED proc read mode serdes, RSGEN & ECC" },
{ 0106040, "EU proc ALU" },
{ 0106041, "EU proc control reg" },
{ 0106042, " U proc DFAIL/cntl ROM parity/BD #1 test CNT" },
{ 0106047, " U proc const PROM err w/D proc running SDI test" },
{ 0106055, " unexpected trap" },
{ 0106071, "EU proc const PROM" },
{ 0106072, "EU proc control ROM parity" },
{ 0106200, "Estep 1 data" },
{ 0107103, "EU proc RAM parity" },
{ 0107107, "EU proc RAM buffer" },
{ 0107115, " test count wrong (BD 12)" },
{ 0112300, "Estep 2" },
{ 0122240, "ENPR" },
{ 0122300, "Estep 3" },
{ 0142300, "Estep 4" },
{ 0, " unknown error code" }
};
/*
* If the error bit was set in the controller status register, gripe,
* then (optionally) reset the controller and requeue pending transfers.
*/
void
udasaerror(usc, doreset)
struct device *usc;
int doreset;
{
struct uda_softc *sc = (void *)usc;
register int code = sc->sc_udadev->udasa;
register struct saerr *e;
if ((code & MP_ERR) == 0)
return;
for (e = saerr; e->code; e++)
if (e->code == code)
break;
printf("%s: controller error, sa=0%o (%s%s)\n",
sc->sc_dev.dv_xname, code, e->desc + 1,
*e->desc == 'E' ? " error" : "");
#if 0 /* XXX we just avoid panic when autoconfig non-existent KFQSA devices */
if (doreset) {
mscp_requeue(sc->sc_softc);
/* (void) udainit(sc); XXX */
}
#endif
}
/*
* Interrupt routine. Depending on the state of the controller,
* continue initialisation, or acknowledge command and response
* interrupts, and process responses.
*/
static void
udaintr(ctlr)
int ctlr;
{
intr(uda_cd.cd_devs[ctlr]);
}
static void
mtcintr(ctlr)
int ctlr;
{
intr(mtc_cd.cd_devs[ctlr]);
}
static void
intr(sc)
struct uda_softc *sc;
{
volatile struct udadevice *udaddr = sc->sc_udadev;
struct uba_softc *uh;
struct mscp_pack *ud;
#ifdef QBA
if(vax_cputype == VAX_TYP_UV2)
splx(sc->sc_ipl); /* Qbus interrupt protocol is odd */
#endif
sc->sc_wticks = 0; /* reset interrupt watchdog */
if (udaddr->udasa & MP_ERR) { /* ctlr fatal error */
udasaerror(&sc->sc_dev, 1);
return;
}
ud = &sc->sc_uda;
/*
* Handle buffer purge requests.
*/
uh = (void *)sc->sc_dev.dv_parent;
if (ud->mp_ca.ca_bdp) {
if (uh->uh_ubapurge)
(*uh->uh_ubapurge)(uh, ud->mp_ca.ca_bdp);
ud->mp_ca.ca_bdp = 0;
udaddr->udasa = 0; /* signal purge complete */
}
mscp_intr(sc->sc_softc);
}
/*
* A Unibus reset has occurred on UBA uban. Reinitialise the controller(s)
* on that Unibus, and requeue outstanding I/O.
*/
void
udareset(ctlr)
int ctlr;
{
reset(uda_cd.cd_devs[ctlr]);
}
void
mtcreset(ctlr)
int ctlr;
{
reset(mtc_cd.cd_devs[ctlr]);
}
static void
reset(sc)
struct uda_softc *sc;
{
printf(" %s", sc->sc_dev.dv_xname);
/*
* Our BDP (if any) is gone; our command (if any) is
* flushed; the device is no longer mapped; and the
* UDA50 is not yet initialised.
*/
if (sc->sc_unit.uu_bdp) {
printf("<%d>", UBAI_BDP(sc->sc_unit.uu_bdp));
sc->sc_unit.uu_bdp = 0;
}
sc->sc_unit.uu_ubinfo = 0;
/* sc->sc_unit.uu_cmd = 0; XXX */
/* reset queues and requeue pending transfers */
mscp_requeue(sc->sc_softc);
/*
* If it fails to initialise we will notice later and
* try again (and again...). Do not call udastart()
* here; it will be done after the controller finishes
* initialisation.
*/
/* XXX if (udainit(sc)) */
printf(" (hung)");
}
void
udactlrdone(usc, info)
struct device *usc;
int info;
{
struct uda_softc *sc = (void *)usc;
/* XXX check if we shall release the BDP */
sc->sc_unit.uu_ubinfo = info;
ubadone(&sc->sc_unit);
}

63
sys/arch/vax/uba/udareg.h
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@ -1,63 +0,0 @@
/* $NetBSD: udareg.h,v 1.3 1996/07/01 21:24:50 ragge Exp $ */
/*
* Copyright (c) 1988 Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Chris Torek.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)udareg.h 7.3 (Berkeley) 5/8/91
*/
/*
* UDA50 registers and structures
*/
/*
* Writing any value to udaip starts initialisation. Reading from it
* when the UDA is running makes the UDA look through the command ring
* to find any new commands. Reading udasa gives status; writing it
* during initialisation sets things up.
*/
struct udadevice {
u_short udaip; /* initialisation and polling */
u_short udasa; /* status and address */
};
/*
* Bits in UDA status register after initialisation
*/
#define UDA_GO 0x0001 /* run */
#define UDASR_BITS \
"\20\20ERR\17STEP4\16STEP3\15STEP2\14STEP1\13NV\12QB\11DI\10IE\1GO"