apply gcc original rev. 1.51
> 2000-03-06 Clinton Popetz <cpopetz@cygnus.com> > > * config/sh/sh.c: (barrier_align): Handle a delay slot that is > filled with an insn from the jump target.
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@ -2572,7 +2572,7 @@ barrier_align (barrier_or_label)
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rtx barrier_or_label;
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{
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rtx next = next_real_insn (barrier_or_label), pat, prev;
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int slot, credit;
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int slot, credit, jump_to_next;
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if (! next)
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return 0;
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@ -2604,12 +2604,24 @@ barrier_align (barrier_or_label)
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if (! TARGET_SH2 || ! optimize)
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return CACHE_LOG;
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/* When fixing up pcloads, a constant table might be inserted just before
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the basic block that ends with the barrier. Thus, we can't trust the
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instruction lengths before that. */
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if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
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{
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/* Check if there is an immediately preceding branch to the insn beyond
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the barrier. We must weight the cost of discarding useful information
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from the current cache line when executing this branch and there is
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an alignment, against that of fetching unneeded insn in front of the
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branch target when there is no alignment. */
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/* There are two delay_slot cases to consider. One is the simple case
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where the preceding branch is to the insn beyond the barrier (simple
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delay slot filling), and the other is where the preceding branch has
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a delay slot that is a duplicate of the insn after the barrier
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(fill_eager_delay_slots) and the branch is to the insn after the insn
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after the barrier. */
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/* PREV is presumed to be the JUMP_INSN for the barrier under
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investigation. Skip to the insn before it. */
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prev = prev_real_insn (prev);
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@ -2618,11 +2630,21 @@ barrier_align (barrier_or_label)
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credit >= 0 && prev && GET_CODE (prev) == INSN;
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prev = prev_real_insn (prev))
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{
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jump_to_next = 0;
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if (GET_CODE (PATTERN (prev)) == USE
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|| GET_CODE (PATTERN (prev)) == CLOBBER)
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continue;
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if (GET_CODE (PATTERN (prev)) == SEQUENCE)
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{
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prev = XVECEXP (PATTERN (prev), 0, 1);
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if (INSN_UID (prev) == INSN_UID (next))
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{
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/* Delay slot was filled with insn at jump target. */
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jump_to_next = 1;
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continue;
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}
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}
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if (slot &&
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get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
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slot = 0;
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@ -2631,9 +2653,15 @@ barrier_align (barrier_or_label)
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if (prev
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&& GET_CODE (prev) == JUMP_INSN
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&& JUMP_LABEL (prev)
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&& next_real_insn (JUMP_LABEL (prev)) == next_real_insn (barrier_or_label)
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&& (credit - slot >= (GET_CODE (SET_SRC (PATTERN (prev))) == PC ? 2 : 0)))
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&& (jump_to_next || next_real_insn (JUMP_LABEL (prev)) == next))
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{
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rtx pat = PATTERN (prev);
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if (GET_CODE (pat) == PARALLEL)
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pat = XVECEXP (pat, 0, 0);
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if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
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return 0;
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}
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}
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return CACHE_LOG;
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}
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@ -2689,7 +2689,7 @@ barrier_align (barrier_or_label)
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rtx barrier_or_label;
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{
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rtx next = next_real_insn (barrier_or_label), pat, prev;
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int slot, credit;
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int slot, credit, jump_to_next;
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if (! next)
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return 0;
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@ -2732,6 +2732,13 @@ barrier_align (barrier_or_label)
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an alignment, against that of fetching unneeded insn in front of the
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branch target when there is no alignment. */
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/* There are two delay_slot cases to consider. One is the simple case
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where the preceding branch is to the insn beyond the barrier (simple
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delay slot filling), and the other is where the preceding branch has
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a delay slot that is a duplicate of the insn after the barrier
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(fill_eager_delay_slots) and the branch is to the insn after the insn
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after the barrier. */
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/* PREV is presumed to be the JUMP_INSN for the barrier under
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investigation. Skip to the insn before it. */
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prev = prev_real_insn (prev);
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@ -2740,11 +2747,21 @@ barrier_align (barrier_or_label)
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credit >= 0 && prev && GET_CODE (prev) == INSN;
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prev = prev_real_insn (prev))
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{
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jump_to_next = 0;
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if (GET_CODE (PATTERN (prev)) == USE
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|| GET_CODE (PATTERN (prev)) == CLOBBER)
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continue;
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if (GET_CODE (PATTERN (prev)) == SEQUENCE)
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{
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prev = XVECEXP (PATTERN (prev), 0, 1);
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if (INSN_UID (prev) == INSN_UID (next))
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{
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/* Delay slot was filled with insn at jump target. */
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jump_to_next = 1;
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continue;
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}
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}
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if (slot &&
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get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
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slot = 0;
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@ -2754,9 +2771,15 @@ barrier_align (barrier_or_label)
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&& GET_CODE (prev) == JUMP_INSN
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&& JUMP_LABEL (prev)
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&& next_real_insn (JUMP_LABEL (prev)) == next_real_insn (barrier_or_label)
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&& (credit - slot >= (GET_CODE (SET_SRC (PATTERN (prev))) == PC ? 2 : 0)))
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&& (jump_to_next || next_real_insn (JUMP_LABEL (prev)) == next))
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{
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rtx pat = PATTERN (prev);
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if (GET_CODE (pat) == PARALLEL)
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pat = XVECEXP (pat, 0, 0);
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if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
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return 0;
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}
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}
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return CACHE_LOG;
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}
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