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Tweak status value in struct clockframe before calling mips3_clockintr()

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so that spllowersoftclock(9) in hardclock(9) will be handled properly.
This commit is contained in:
tsutsui 2006-09-16 13:31:44 +00:00
parent b77c058061
commit dfef23e0d0
1 changed files with 26 additions and 34 deletions
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60
sys/arch/cobalt/cobalt/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.74 2006/09/10 14:27:38 tsutsui Exp $ */
/* $NetBSD: machdep.c,v 1.75 2006/09/16 13:31:44 tsutsui Exp $ */
/*
* Copyright (c) 2006 Izumi Tsutsui.
@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.74 2006/09/10 14:27:38 tsutsui Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.75 2006/09/16 13:31:44 tsutsui Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -673,50 +673,42 @@ cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
/* call the common MIPS3 clock interrupt handler */
cf.pc = pc;
cf.sr = status;
if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
if ((ipending & MIPS_INT_MASK &
~MIPS_INT_MASK_5) == 0) {
/*
* If all interrupts were enabled and
* there is no pending interrupts,
* set MIPS_SR_INT_IE so that
* spllowersoftclock(9) in hardclock(9)
* works properly.
*/
_splset(MIPS_SR_INT_IE);
} else {
/*
* If there are any pending interrputs,
* clear MIPS_SR_INT_IE in cf.sr so that
* spllowersoftclock(9) in hardclock(9) will
* not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
}
mips3_clockintr(&cf);
cause &= ~MIPS_INT_MASK_5;
}
_splset((status & MIPS_INT_MASK_5) | MIPS_SR_INT_IE);
if (ipending & MIPS_INT_MASK_0) {
if (__predict_false(ipending & MIPS_INT_MASK_0)) {
/* GT64x11 timer0 */
volatile uint32_t *irq_src =
(uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
if (__predict_true((*irq_src & T0EXP) != 0)) {
/* GT64x11 timer is no longer used for hardclock(9) */
*irq_src = 0;
#if 0 /* GT64x11 timer is no longer used for hardclock(9) */
cf.pc = pc;
cf.sr = status;
if ((status & MIPS_INT_MASK) == MIPS_INT_MASK) {
if ((ipending & MIPS_INT_MASK &
~MIPS_INT_MASK_0) == 0) {
/*
* If all interrupts were enabled and
* there is no pending interrupts,
* set MIPS_SR_INT_IE so that
* spllowerclock() in hardclock()
* works properly.
*/
#if 0 /* MIPS_SR_INT_IE is enabled above */
_splset(MIPS_SR_INT_IE);
#endif
} else {
/*
* If there are any pending interrputs,
* clear MIPS_SR_INT_IE in cf.sr so that
* spllowerclock() in hardclock() will
* not happen.
*/
cf.sr &= ~MIPS_SR_INT_IE;
}
}
hardclock(&cf);
hardclock_ev.ev_count++;
#endif
}
cause &= ~MIPS_INT_MASK_0;
}