Add support for the Artisea device operating in DPA mode.
Approved by briggs.
This commit is contained in:
rearnsha
parent
920296fb7f
commit
dfcdd57e20
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@ -1,4 +1,4 @@
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/* $NetBSD: artsata.c,v 1.4 2004/08/20 06:39:38 thorpej Exp $ */
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/* $NetBSD: artsata.c,v 1.5 2005/02/11 21:12:32 rearnsha Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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@ -38,11 +38,18 @@
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_i31244_reg.h>
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#include <dev/ata/satareg.h>
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#include <dev/ata/satavar.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/atavar.h>
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static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *);
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@ -62,6 +69,28 @@ static const struct pciide_product_desc pciide_artsata_products[] = {
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}
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};
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struct artisea_cmd_map
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{
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u_int8_t offset;
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u_int8_t size;
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};
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static const struct artisea_cmd_map artisea_dpa_cmd_map[] =
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{
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{ARTISEA_SUPDDR, 4}, /* 0 Data */
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{ARTISEA_SUPDER, 1}, /* 1 Error */
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{ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */
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{ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */
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{ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */
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{ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */
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{ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */
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{ARTISEA_SUPDCR, 1}, /* 7 Command */
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{ARTISEA_SUPDSR, 1}, /* 8 Status */
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{ARTISEA_SUPDFR, 2} /* 9 Feature */
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};
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#define ARTISEA_NUM_CHAN 4
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CFATTACH_DECL(artsata, sizeof(struct pciide_softc),
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artsata_match, artsata_attach, NULL, NULL);
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@ -88,6 +117,338 @@ artsata_attach(struct device *parent, struct device *self, void *aux)
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}
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static void
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artisea_drv_probe(struct ata_channel *chp)
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{
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
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uint32_t scontrol, sstatus;
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uint16_t scnt, sn, cl, ch;
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int i, s;
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/* XXX This should be done by other code. */
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for (i = 0; i < 2; i++) {
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chp->ch_drive[i].chnl_softc = chp;
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chp->ch_drive[i].drive = i;
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}
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/*
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* First we have to bring the PHYs online, in case the firmware
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* has not already done so. The 31244 leaves the disks off-line
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* on reset to avoid excessive power surges due to multiple spindle
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* spin up.
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*
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* The work-around for errata #1 says that we must write 0 to the
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* port first to be sure of correctly initializing the device.
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*
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* XXX will this try to bring multiple disks on-line too quickly?
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*/
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bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 0);
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scontrol = SControl_IPM_NONE | SControl_SPD_ANY | SControl_DET_INIT;
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bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol);
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scontrol &= ~SControl_DET_INIT;
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bus_space_write_4 (wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, scontrol);
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delay(50 * 1000);
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sstatus = bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR);
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switch (sstatus & SStatus_DET_mask) {
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case SStatus_DET_NODEV:
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/* No Device; be silent. */
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break;
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case SStatus_DET_DEV_NE:
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aprint_error("%s: port %d: device connected, but "
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"communication not established\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
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break;
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case SStatus_DET_OFFLINE:
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aprint_error("%s: port %d: PHY offline\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
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break;
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case SStatus_DET_DEV:
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
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WDSD_IBM);
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delay(10); /* 400ns delay */
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scnt = bus_space_read_2(wdr->cmd_iot,
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wdr->cmd_iohs[wd_seccnt], 0);
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sn = bus_space_read_2(wdr->cmd_iot,
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wdr->cmd_iohs[wd_sector], 0);
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cl = bus_space_read_2(wdr->cmd_iot,
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wdr->cmd_iohs[wd_cyl_lo], 0);
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ch = bus_space_read_2(wdr->cmd_iot,
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wdr->cmd_iohs[wd_cyl_hi], 0);
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printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
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scnt, sn, cl, ch);
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/*
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* scnt and sn are supposed to be 0x1 for ATAPI, but in some
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* cases we get wrong values here, so ignore it.
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*/
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s = splbio();
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if (cl == 0x14 && ch == 0xeb)
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chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
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else
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chp->ch_drive[0].drive_flags |= DRIVE_ATA;
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splx(s);
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aprint_normal("%s: port %d: device present, speed: %s\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
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sata_speed(sstatus));
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break;
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default:
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aprint_error("%s: port %d: unknown SStatus: 0x%08x\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
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sstatus);
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}
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}
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static void
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artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp,
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bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *))
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{
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struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
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struct ata_channel *wdc_cp = &cp->ata_channel;
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
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const char *intrstr;
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pci_intr_handle_t intrhandle;
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int i;
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cp->compat = 0;
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if (sc->sc_pci_ih == NULL) {
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error("%s: couldn't map native-PCI interrupt\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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goto bad;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
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intrhandle, IPL_BIO, pci_intr, sc);
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if (sc->sc_pci_ih != NULL) {
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aprint_normal("%s: using %s for native-PCI interrupt\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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intrstr ? intrstr : "unknown interrupt");
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} else {
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aprint_error(
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"%s: couldn't establish native-PCI interrupt",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (intrstr != NULL)
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aprint_normal(" at %s", intrstr);
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aprint_normal("\n");
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goto bad;
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}
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}
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cp->ih = sc->sc_pci_ih;
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wdr->cmd_iot = sc->sc_ba5_st;
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if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
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&wdr->cmd_baseioh) != 0) {
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aprint_error("%s: couldn't map %s channel cmd regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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wdr->ctl_iot = sc->sc_ba5_st;
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
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aprint_error("%s: couldn't map %s channel ctl regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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wdr->ctl_ioh = cp->ctl_baseioh;
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for (i = 0; i < WDC_NREG + 2; i++) {
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
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&wdr->cmd_iohs[i]) != 0) {
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aprint_error("%s: couldn't subregion %s channel "
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"cmd regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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}
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = wdr->cmd_iohs[0];
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wdcattach(wdc_cp);
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return;
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bad:
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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return;
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}
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static int
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artisea_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
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{
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struct pciide_channel *cp = &sc->pciide_channels[channel];
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sc->wdc_chanarray[channel] = &cp->ata_channel;
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cp->name = PCIIDE_CHANNEL_NAME(channel);
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cp->ata_channel.ch_channel = channel;
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cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
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cp->ata_channel.ch_queue =
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malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
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if (cp->ata_channel.ch_queue == NULL) {
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aprint_error("%s %s channel: "
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"can't allocate memory for command queue",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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return 0;
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}
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return 1;
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}
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static void
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artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *pc;
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int chan;
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u_int32_t dma_ctl;
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u_int32_t cacheline_len;
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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sc->sc_dma_ok = 1;
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/*
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* Errata #4 says that if the cacheline length is not set correctly,
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* we can get corrupt MWI and Memory-Block-Write transactions.
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*/
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cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
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PCI_BHLC_REG));
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if (cacheline_len == 0) {
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aprint_normal(", but unused (cacheline size not set in PCI conf)\n");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Final step of the work-around is to force the DMA engine to use
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* the cache-line length information.
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*/
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dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
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dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = pciide_dma_init;
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sc->sc_wdcdev.dma_start = pciide_dma_start;
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sc->sc_wdcdev.dma_finish = pciide_dma_finish;
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sc->sc_dma_iot = sc->sc_ba5_st;
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sc->sc_dmat = pa->pa_dmat;
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if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags &
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PCIIDE_OPTIONS_NODMA) {
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aprint_normal(
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", but unused (forced off by config file)\n");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Set up the default handles for the DMA registers.
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* Just reserve 32 bits for each handle, unless space
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* doesn't permit it.
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*/
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for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
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pc = &sc->pciide_channels[chan];
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
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&pc->dma_iohs[IDEDMA_CMD]) != 0 ||
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bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
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&pc->dma_iohs[IDEDMA_CTL]) != 0 ||
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bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
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&pc->dma_iohs[IDEDMA_TBL]) != 0) {
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sc->sc_dma_ok = 0;
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aprint_normal(", but can't subregion registers\n");
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return;
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}
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}
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aprint_normal("\n");
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}
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static void
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artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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pcireg_t interface;
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int channel;
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interface = PCI_INTERFACE(pa->pa_class);
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aprint_normal("%s: interface wired in DPA mode\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT,
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0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0)
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return;
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artisea_mapreg_dma(sc, pa);
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sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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}
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sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
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sc->sc_wdcdev.sc_atac.atac_probe = artisea_drv_probe;
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wdc_allocate_regs(&sc->sc_wdcdev);
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/*
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* Perform a quick check to ensure that the device isn't configured
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* in Spread-spectrum clocking mode. This feature is buggy and has
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* been removed from the latest documentation.
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*
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* Note that although this bit is in the Channel regs, it's the same
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* for all channels, so we check it just once here.
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*/
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if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
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ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
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aprint_error("%s: Spread-specturm clocking not supported by device\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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return;
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}
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/* Clear the LED0-only bit. */
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pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0,
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pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) &
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~SUECSR0_LED0_ONLY);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (artisea_chansetup(sc, channel, interface) == 0)
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continue;
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/* XXX We can probably do interrupts more efficiently. */
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artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr);
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}
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}
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static void
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artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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@ -99,6 +460,13 @@ artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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if (pciide_chipen(sc, pa) == 0)
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||||
return;
|
||||
|
||||
interface = PCI_INTERFACE(pa->pa_class);
|
||||
|
||||
if (interface == 0) {
|
||||
artisea_chip_map_dpa (sc, pa);
|
||||
return;
|
||||
}
|
||||
|
||||
aprint_normal("%s: bus-master DMA support present",
|
||||
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
|
||||
#ifndef PCIIDE_I31244_ENABLEDMA
|
||||
|
|
@ -130,8 +498,6 @@ artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
|
|||
|
||||
wdc_allocate_regs(&sc->sc_wdcdev);
|
||||
|
||||
interface = PCI_INTERFACE(pa->pa_class);
|
||||
|
||||
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
|
||||
channel++) {
|
||||
cp = &sc->pciide_channels[channel];
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pciide_i31244_reg.h,v 1.1 2003/03/18 01:41:54 thorpej Exp $ */
|
||||
/* $NetBSD: pciide_i31244_reg.h,v 1.2 2005/02/11 21:12:32 rearnsha Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
|
|
@ -50,11 +50,15 @@
|
|||
/*
|
||||
* Extended Control and Status Register 0
|
||||
*/
|
||||
#define ARTISEA_PCI_SUECR0 0x98
|
||||
#define SUECR0_LED0_ONLY (1U << 28) /* activity on LED0 only */
|
||||
#define SUECR0_SFSS (1U << 16) /* Superset Features
|
||||
#define ARTISEA_PCI_SUECSR0 0x98
|
||||
#define SUECSR0_LED0_ONLY (1U << 28) /* activity on LED0 only */
|
||||
#define SUECSR0_SFSS (1U << 16) /* Superset Features
|
||||
Secondary Select */
|
||||
|
||||
#define ARTISEA_PCI_SUDCSCR 0xa0
|
||||
#define SUDCSCR_DMA_WCAE 0x02 /* Write cache align enable */
|
||||
#define SUDCSCR_DMA_RCAE 0x01 /* Read cache align enable */
|
||||
|
||||
/*
|
||||
* DPA mode shared registers.
|
||||
*/
|
||||
|
|
@ -164,16 +168,16 @@
|
|||
#define SUPDSSER_ERR_M (1U << 1) /* recovered comm. */
|
||||
#define SUPDSSER_ERR_I (1U << 0) /* not implemented */
|
||||
|
||||
#define ARTISEA_SUPDDSCR 0x008 /* DPA SATA SControl register */
|
||||
#define SUPDDSCR_IPM_ANY (0 << 8) /* no IPM mode restrictions */
|
||||
#define SUPDDSCR_IPM_NO_PARTIAL (1U << 8) /* no PARTIAL mode */
|
||||
#define SUPDDSCR_IPM_NO_SLUMBER (2U << 8) /* no SLUMBER mode */
|
||||
#define SUPDDSCR_IPM_NONE (3U << 8) /* no PM allowed */
|
||||
#define SUPDDSCR_SPD_ANY (0 << 4) /* no speed restrictions */
|
||||
#define SUPDDSCR_SPD_G1 (1U << 4) /* <= Generation 1 */
|
||||
#define SUPDDSCR_DET_NORM (0 << 0) /* normal operation */
|
||||
#define SUPDDSCR_DET_INIT (1U << 0) /* comm. init */
|
||||
#define SUPDDSCR_DET_DISABLE (4U << 0) /* disable interface */
|
||||
#define ARTISEA_SUPDSSCR 0x008 /* DPA SATA SControl register */
|
||||
#define SUPDSSCR_IPM_ANY (0 << 8) /* no IPM mode restrictions */
|
||||
#define SUPDSSCR_IPM_NO_PARTIAL (1U << 8) /* no PARTIAL mode */
|
||||
#define SUPDSSCR_IPM_NO_SLUMBER (2U << 8) /* no SLUMBER mode */
|
||||
#define SUPDSSCR_IPM_NONE (3U << 8) /* no PM allowed */
|
||||
#define SUPDSSCR_SPD_ANY (0 << 4) /* no speed restrictions */
|
||||
#define SUPDSSCR_SPD_G1 (1U << 4) /* <= Generation 1 */
|
||||
#define SUPDSSCR_DET_NORM (0 << 0) /* normal operation */
|
||||
#define SUPDSSCR_DET_INIT (1U << 0) /* comm. init */
|
||||
#define SUPDSSCR_DET_DISABLE (4U << 0) /* disable interface */
|
||||
|
||||
#define ARTISEA_SUPDSDBR 0x00c /* DPA Set Device Bits register */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: pciidevar.h,v 1.28 2005/02/04 02:10:45 perry Exp $ */
|
||||
/* $NetBSD: pciidevar.h,v 1.29 2005/02/11 21:12:32 rearnsha Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
|
||||
|
|
@ -108,7 +108,7 @@ struct pciide_softc {
|
|||
/* for SiS */
|
||||
u_int8_t sis_type;
|
||||
|
||||
/* For Silicon Image SATALink, and Promise SATA */
|
||||
/* For Silicon Image SATALink, Artisea SATA and Promise SATA */
|
||||
bus_space_tag_t sc_ba5_st;
|
||||
bus_space_handle_t sc_ba5_sh;
|
||||
int sc_ba5_en;
|
||||
|
|
|
|||
Loading…
Reference in New Issue