Update from Ken Wellsch: The DHU driver can now handle DMA transfers.
This commit is contained in:
ragge
parent
3b5cb56887
commit
dfaa8f2e96
@ -1,4 +1,4 @@
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/* $NetBSD: dhu.c,v 1.1 1996/03/02 13:30:53 ragge Exp $ */
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/* $NetBSD: dhu.c,v 1.2 1996/03/17 22:51:48 ragge Exp $ */
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/*
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* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
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* Copyright (c) 1992, 1993
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@ -64,16 +64,49 @@
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#define NDHULINE (NDHU*16)
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/* This is an experiment to try and fake DHU behavior with a DHV.
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* The DHV does not have any programmable delay on input silo level
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* but interrupts immediately when the first character enters.
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* This is really kludgy and so I doubt it will stay. From what could
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* be measured, doing a timeout() delay reduced the input interrupt
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* rate by an order of magnitude (from over 700 to at most 30) with
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* heavy input (e.g. via kermit). Input performance increased 5% too
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* as more CPU cycles were available for the application to consume input.
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*/
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#define RX_DELAY 0 /* ticks to delay RX intr handling */
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struct dhu_softc
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{
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dhuregs * sc_addr; /* controller reg address */
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struct tty * sc_tty; /* what we work on */
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char * sc_mem; /* pointers to current tx */
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char * sc_end; /* character and end */
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unsigned sc_txaddr; /* UBA map address to TX buf */
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u_char sc_type; /* controller type, DHU or DHV */
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u_char sc_state; /* to manage TX output status */
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u_short sc_cc; /* character count on TX */
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u_short sc_modem; /* modem bits state */
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};
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struct dhu_softc dhu_softc[NDHULINE];
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#define IS_DHU 0 /* cntlr is a DHU */
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#define IS_DHV 1 /* cntlr is a DHV */
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#define STATE_IDLE 000 /* no current output in progress */
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#define STATE_DMA_RUNNING 001 /* DMA TX in progress */
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#define STATE_DMA_STOPPED 002 /* DMA TX was aborted */
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#define STATE_TX_ONE_CHAR 004 /* did a single char directly */
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/* Flags used to monitor modem bits, make them understood outside driver */
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#define DML_DTR TIOCM_DTR
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#define DML_RTS TIOCM_RTS
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#define DML_CTS TIOCM_CTS
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#define DML_DCD TIOCM_CD
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#define DML_RI TIOCM_RI
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#define DML_DSR TIOCM_DSR
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#define DML_BRK 0100000 /* no equivalent, we will mask */
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/* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */
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/* a baud rate from the same group. So limiting to B is likely */
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/* best, although clone boards like the ABLE QHV allow all settings. */
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@ -103,19 +136,24 @@ static struct speedtab dhuspeedtab[] =
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static int dhu_match __P((struct device *, void *, void *));
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static void dhu_attach __P((struct device *, struct device *, void *));
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struct cfdriver dhucd =
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{
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NULL, "dhu", dhu_match, dhu_attach, DV_DULL, sizeof(struct device),
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struct cfdriver dhu_cd = {
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NULL, "dhu", DV_TTY
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};
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struct cfattach dhu_ca = {
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sizeof(struct device), dhu_match, dhu_attach
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};
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static void dhuintr __P((int));
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static void dhurint __P((int));
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static void dhuxint __P((int));
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static void dhustart __P((struct tty *));
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static int dhuparam __P((struct tty *, struct termios *));
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static int dhuiflow __P((struct tty *, int));
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static int dhumctl __P((int, int, int));
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int dhustop __P((struct tty *, int));
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static unsigned dhumctl __P((int, int, int));
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/* Autoconfig handles: setup the controller to interrupt, */
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/* then complete the housecleaning for full operation */
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@ -136,7 +174,7 @@ dhu_match (parent, match, aux)
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dhuaddr = (dhuregs *) ua->ua_addr;
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/* Reset controller to initialize, enable tx/rx interrupts */
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/* Reset controller to initialize, enable TX/RX interrupts */
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/* to catch floating vector info elsewhere when completed */
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dhuaddr->dhu_csr = (DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE);
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@ -160,9 +198,9 @@ dhu_match (parent, match, aux)
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if ((dhuaddr->dhu_csr & DHU_CSR_DIAG_FAIL) != 0)
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return 0;
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/* Register the rx interrupt handler and pass unit # as arg */
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/* Register the RX interrupt handler and pass unit # as arg */
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ua->ua_ivec = dhuintr;
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ua->ua_ivec = dhurint;
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ua->ua_iarg = nunits;
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nunits++;
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@ -175,17 +213,16 @@ dhu_attach (parent, self, aux)
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void *aux;
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{
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register struct uba_attach_args *ua = aux;
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register struct uba_softc *sc = (struct uba_softc *)parent;
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register dhuregs *dhuaddr;
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register unsigned c;
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register int n;
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register int n, m;
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dhuaddr = (dhuregs *) ua->ua_addr;
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/* Process the 8 bytes of diagnostic info put into */
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/* the FIFO following the master reset operation. */
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printf ("\ndhv:");
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printf ("\ndhv%d:", self->dv_unit);
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for (n = 0; n < 8; n++) {
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c = dhuaddr->dhu_rbuf;
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@ -202,59 +239,69 @@ dhu_attach (parent, self, aux)
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/* Initialize our static softc structure. */
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for (n = 0; n < 8; n++) {
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dhu_softc[(self->dv_unit<<4)+n].sc_addr = dhuaddr;
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dhu_softc[(self->dv_unit<<4)+n].sc_tty = ttymalloc();
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c = dhuaddr->dhu_stat; /* get flag to distinguish DHU from DHV */
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for (n = 0; n < ((c & DHU_STAT_DHU)? 16: 8); n++) {
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m = ((self->dv_unit) << 4) + n;
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dhu_softc[m].sc_addr = dhuaddr;
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dhu_softc[m].sc_tty = ttymalloc();
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dhu_softc[m].sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV;
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dhu_softc[m].sc_state = STATE_IDLE;
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dhu_softc[m].sc_txaddr = uballoc (parent->dv_unit,
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dhu_softc[m].sc_tty->t_outq.c_cs,
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dhu_softc[m].sc_tty->t_outq.c_cn,
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UBA_CANTWAIT);
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}
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/* Now stuff tx interrupt handler in place */
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/* Now stuff TX interrupt handler in place */
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n = ua->ua_cvec + 1;
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sc->uh_idsp[n].hoppaddr = dhuintr;
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sc->uh_idsp[n].pushlarg = self->dv_unit;
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return;
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}
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/* Using a single interrupt entry point currently, to keep */
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/* CSR reads to a minimum (and avoid losing TX.ACTION signal) */
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static void
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dhuintr (cntlr)
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int cntlr;
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{
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register dhuregs *dhuaddr;
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register unsigned csr;
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dhuaddr = dhu_softc[cntlr].sc_addr;
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/* The DHV manual says TX.ACTION is cleared when */
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/* the CSR is read, so we've got to be careful. */
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while ((csr = dhuaddr->dhu_csr) & (DHU_CSR_TX_ACTION|
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DHU_CSR_RX_DATA_AVAIL))
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{
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if (csr & DHU_CSR_RX_DATA_AVAIL)
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dhurint (cntlr);
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if (csr & DHU_CSR_TX_ACTION)
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dhuxint ((cntlr<<4)|((csr>>8)&017));
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}
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/* XXX check for spurious interrupts? */
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ubasetvec (self, ua->ua_cvec+1, dhuxint);
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return;
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}
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/* Receiver Interrupt */
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#if RX_DELAY > 0
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static int RXtimeout = 0;
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static void
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dhurint (cntlr)
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int cntlr;
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{
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static void dhuRXint __P((void *));
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if (RXtimeout == 0) {
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RXtimeout = 1;
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timeout (dhuRXint, (void *)cntlr, RX_DELAY);
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}
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return;
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}
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static void
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dhuRXint (arg)
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void * arg;
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{
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#else
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static void
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dhurint (cntlr)
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int cntlr;
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{
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#endif
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register dhuregs *dhuaddr;
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register struct tty *tp;
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register int cc, unit;
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register unsigned c;
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register unsigned c, delta;
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int overrun = 0;
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#if RX_DELAY > 0
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int cntlr = (int) arg;
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int s;
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s = spltty();
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#endif
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dhuaddr = dhu_softc[cntlr].sc_addr;
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@ -281,11 +328,26 @@ dhurint (cntlr)
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else if ((tp->t_state & TS_CARR_ON) &&
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(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
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(void) dhumctl (unit, 0, DMSET);
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return;
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/* Do CRTSCTS flow control */
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delta = c ^ dhu_softc[unit].sc_modem;
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dhu_softc[unit].sc_modem = c;
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if ((delta & DHU_STAT_CTS) &&
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(tp->t_state & TS_ISOPEN) &&
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(tp->t_cflag & CRTSCTS)) {
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if (c & DHU_STAT_CTS) {
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tp->t_state &= ~TS_TTSTOP;
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ttstart (tp);
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} else {
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tp->t_state |= TS_TTSTOP;
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dhustop (tp, 0);
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}
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}
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continue;
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}
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if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) {
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log(LOG_WARNING, "dhv%d,%d: silo overflow\n",
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log(LOG_WARNING, "dhv(%d,%d): silo overflow\n",
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cntlr, (c >> 8) & 017);
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overrun = 1;
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}
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@ -297,40 +359,47 @@ dhurint (cntlr)
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(*linesw[tp->t_line].l_rint)(cc, tp);
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}
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#if RX_DELAY > 0
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RXtimeout = 0;
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(void) splx(s);
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#endif
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return;
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}
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/* Transmitter Interrupt */
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static void
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dhuxint (unit)
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int unit;
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dhuxint (cntlr)
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int cntlr;
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{
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register dhuregs *dhuaddr;
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register struct dhu_softc *sc;
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register struct tty *tp;
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register unsigned csr;
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register int unit;
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dhuaddr = dhu_softc[cntlr].sc_addr;
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csr = (dhuaddr->dhu_csr_hi) << 8;
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unit = (cntlr<<4)|((csr>>8)&017);
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sc = &dhu_softc[unit];
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/* Using simple character-at-a-time for now. */
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/* XXX should be checking status of a DMA transfer */
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if (sc->sc_mem < sc->sc_end) {
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dhuaddr = sc->sc_addr;
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dhuaddr->dhu_csr = (DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017));
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dhuaddr->dhu_txchar = DHU_TXCHAR_DATA_VALID | *sc->sc_mem++;
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return;
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}
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tp = sc->sc_tty;
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tp->t_state &= ~TS_BUSY;
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if (tp->t_state & TS_FLUSH)
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tp->t_state &= ~TS_FLUSH;
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else {
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ndflush(&tp->t_outq, sc->sc_mem - (caddr_t) tp->t_outq.c_cf);
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sc->sc_end = sc->sc_mem = tp->t_outq.c_cf;
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if (sc->sc_state == STATE_DMA_STOPPED)
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sc->sc_cc -= dhuaddr->dhu_tbufcnt;
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ndflush (&tp->t_outq, sc->sc_cc);
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sc->sc_cc = 0;
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}
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sc->sc_state = STATE_IDLE;
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if (tp->t_line)
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(*linesw[tp->t_line].l_start)(tp);
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else
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@ -357,15 +426,18 @@ dhuopen (dev, flag, mode, p)
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tp = dhu_softc[unit].sc_tty = ttymalloc();
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tp->t_oproc = dhustart;
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tp->t_param = dhuparam;
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tp->t_hwiflow = dhuiflow;
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tp->t_dev = dev;
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if ((tp->t_state & TS_ISOPEN) == 0) {
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tp->t_state |= TS_WOPEN;
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ttychars(tp);
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if (tp->t_ispeed == 0) {
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_cflag = TTYDEF_CFLAG;
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tp->t_lflag = TTYDEF_LFLAG;
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tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
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}
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(void) dhuparam(tp, &tp->t_termios);
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ttsetwater(tp);
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} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
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@ -489,7 +561,7 @@ dhuioctl (dev, cmd, data, flag, p)
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break;
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case TIOCMGET:
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*(int *)data = dhumctl (unit, 0, DMGET);
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*(int *)data = (dhumctl (unit, 0, DMGET) & ~DML_BRK);
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break;
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default:
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@ -498,38 +570,6 @@ dhuioctl (dev, cmd, data, flag, p)
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return (0);
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}
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/*ARGSUSED*/
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int
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dhustop (tp, flag)
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register struct tty *tp;
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{
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#ifdef notyet
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register dhuregs *dhuaddr;
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#endif
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register struct dhu_softc *sc;
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int unit = minor(tp->t_dev);
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int s;
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s = spltty();
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if (tp->t_state & TS_BUSY) {
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sc = &dhu_softc[unit];
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#ifdef notyet
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dhuaddr = sc->sc_addr;
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dhuaddr->dhu_csr = (DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017));
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dhuaddr->dhu_lnctrl |= DHU_LNCTRL_DMA_ABORT;
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/* Aborting a DMA operation leaves it restartable. */
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#else
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sc->sc_end = sc->sc_mem;
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#endif
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if (!(tp->t_state & TS_TTSTOP))
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tp->t_state |= TS_FLUSH;
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}
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(void) splx(s);
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return 0;
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}
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struct tty *
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dhutty (dev)
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dev_t dev;
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@ -538,6 +578,38 @@ dhutty (dev)
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return (tp);
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}
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/*ARGSUSED*/
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int
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dhustop (tp, flag)
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register struct tty *tp;
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{
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register dhuregs *dhuaddr;
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register struct dhu_softc *sc;
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int unit = minor(tp->t_dev);
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int s;
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s = spltty();
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if (tp->t_state & TS_BUSY)
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{
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sc = &dhu_softc[unit];
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if (sc->sc_state == STATE_DMA_RUNNING)
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{
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sc->sc_state = STATE_DMA_STOPPED;
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dhuaddr = sc->sc_addr;
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dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | (unit & 017));
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dhuaddr->dhu_lnctrl |= DHU_LNCTRL_DMA_ABORT;
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}
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if (!(tp->t_state & TS_TTSTOP))
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tp->t_state |= TS_FLUSH;
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}
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(void) splx(s);
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return 0;
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}
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static void
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dhustart (tp)
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register struct tty *tp;
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@ -545,6 +617,7 @@ dhustart (tp)
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register struct dhu_softc *sc;
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register dhuregs *dhuaddr;
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register int unit = minor(tp->t_dev);
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register unsigned addr;
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register int cc;
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int s;
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@ -567,19 +640,32 @@ dhustart (tp)
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tp->t_state |= TS_BUSY;
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sc = &dhu_softc[unit];
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sc->sc_end = sc->sc_mem = tp->t_outq.c_cf;
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sc->sc_end += cc;
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#ifdef notyet
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dhuaddr = sc->sc_addr;
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dhuaddr->dhu_csr = ( DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017) );
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/* XXX Still have to actually setup DMA action! */
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#else
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dhuaddr = sc->sc_addr;
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dhuaddr->dhu_csr = (DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017));
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dhuaddr->dhu_txchar = DHU_TXCHAR_DATA_VALID | *sc->sc_mem++;
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#endif
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dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | (unit & 017));
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sc->sc_cc = cc;
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if (cc == 1)
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{
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sc->sc_state = STATE_TX_ONE_CHAR;
|
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dhuaddr->dhu_txchar = DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf;
|
||||
}
|
||||
else
|
||||
{
|
||||
sc->sc_state = STATE_DMA_RUNNING;
|
||||
|
||||
addr = UBAI_ADDR(sc->sc_txaddr) +
|
||||
(tp->t_outq.c_cf - tp->t_outq.c_cs);
|
||||
|
||||
dhuaddr->dhu_tbufcnt = cc;
|
||||
dhuaddr->dhu_tbufad1 = (addr & 0xffff);
|
||||
dhuaddr->dhu_tbufad2 = ((addr>>16) & 0x3f) |
|
||||
DHU_TBUFAD2_TX_ENABLE;
|
||||
|
||||
dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_DMA_ABORT;
|
||||
dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_DMA_START;
|
||||
}
|
||||
out:
|
||||
(void) splx(s);
|
||||
return;
|
||||
@ -595,7 +681,7 @@ dhuparam (tp, t)
|
||||
int unit = minor(tp->t_dev);
|
||||
int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab);
|
||||
int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab);
|
||||
register unsigned lpr;
|
||||
register unsigned lpr, lnctrl;
|
||||
int s;
|
||||
|
||||
/* check requested parameters */
|
||||
@ -613,7 +699,7 @@ dhuparam (tp, t)
|
||||
|
||||
s = spltty();
|
||||
dhuaddr = dhu_softc[unit].sc_addr;
|
||||
dhuaddr->dhu_csr = ( DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017) );
|
||||
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | (unit & 017));
|
||||
|
||||
lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ;
|
||||
|
||||
@ -641,58 +727,90 @@ dhuparam (tp, t)
|
||||
|
||||
dhuaddr->dhu_lpr = lpr;
|
||||
|
||||
dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_TX_ENABLE;
|
||||
|
||||
lnctrl = dhuaddr->dhu_lnctrl;
|
||||
|
||||
/* Setting LINK.TYPE enables modem signal change interrupts. */
|
||||
|
||||
dhuaddr->dhu_lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE);
|
||||
dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_TX_ENABLE;
|
||||
lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE);
|
||||
|
||||
if (t->c_iflag & IXON)
|
||||
lnctrl |= DHU_LNCTRL_OAUTO;
|
||||
else
|
||||
lnctrl &= ~DHU_LNCTRL_OAUTO;
|
||||
|
||||
if (t->c_iflag & IXOFF)
|
||||
lnctrl |= DHU_LNCTRL_IAUTO;
|
||||
else
|
||||
lnctrl &= ~DHU_LNCTRL_IAUTO;
|
||||
|
||||
dhuaddr->dhu_lnctrl = lnctrl;
|
||||
|
||||
dhu_softc[unit].sc_modem = dhuaddr->dhu_stat;
|
||||
|
||||
(void) splx(s);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
dhuiflow (tp, flag)
|
||||
struct tty *tp;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(tp->t_dev);
|
||||
|
||||
if (tp->t_cflag & CRTSCTS) {
|
||||
(void) dhumctl (unit, DML_RTS, ((flag)? DMBIC: DMBIS));
|
||||
return (1);
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static unsigned
|
||||
dhumctl (unit, bits, how)
|
||||
int unit, bits, how;
|
||||
{
|
||||
register dhuregs *dhuaddr;
|
||||
register unsigned mdmstat;
|
||||
register int mbits;
|
||||
register unsigned status;
|
||||
register unsigned lnctrl;
|
||||
register unsigned mbits;
|
||||
int s;
|
||||
|
||||
s = spltty();
|
||||
|
||||
dhuaddr = dhu_softc[unit].sc_addr;
|
||||
dhuaddr->dhu_csr = ( DHU_CSR_RXIE | DHU_CSR_TXIE | (unit & 017) );
|
||||
dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | (unit & 017));
|
||||
|
||||
mbits = 0;
|
||||
|
||||
/* external signals as seen from the port */
|
||||
|
||||
mdmstat = dhuaddr->dhu_stat;
|
||||
status = dhuaddr->dhu_stat;
|
||||
|
||||
if (mdmstat & DHU_STAT_CTS)
|
||||
if (status & DHU_STAT_CTS)
|
||||
mbits |= DML_CTS;
|
||||
|
||||
if (mdmstat & DHU_STAT_DCD)
|
||||
if (status & DHU_STAT_DCD)
|
||||
mbits |= DML_DCD;
|
||||
|
||||
if (mdmstat & DHU_STAT_DSR)
|
||||
if (status & DHU_STAT_DSR)
|
||||
mbits |= DML_DSR;
|
||||
|
||||
if (mdmstat & DHU_STAT_RI)
|
||||
if (status & DHU_STAT_RI)
|
||||
mbits |= DML_RI;
|
||||
|
||||
/* internal signals/state delivered to port */
|
||||
|
||||
mdmstat = dhuaddr->dhu_lnctrl;
|
||||
lnctrl = dhuaddr->dhu_lnctrl;
|
||||
|
||||
if (mdmstat & DHU_LNCTRL_RTS)
|
||||
if (lnctrl & DHU_LNCTRL_RTS)
|
||||
mbits |= DML_RTS;
|
||||
|
||||
if (mdmstat & DHU_LNCTRL_DTR)
|
||||
if (lnctrl & DHU_LNCTRL_DTR)
|
||||
mbits |= DML_DTR;
|
||||
|
||||
if (mdmstat & DHU_LNCTRL_BREAK)
|
||||
if (lnctrl & DHU_LNCTRL_BREAK)
|
||||
mbits |= DML_BRK;
|
||||
|
||||
switch (how)
|
||||
@ -715,22 +833,24 @@ dhumctl (unit, bits, how)
|
||||
}
|
||||
|
||||
if (mbits & DML_RTS)
|
||||
dhuaddr->dhu_lnctrl |= DHU_LNCTRL_RTS;
|
||||
lnctrl |= DHU_LNCTRL_RTS;
|
||||
else
|
||||
dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_RTS;
|
||||
lnctrl &= ~DHU_LNCTRL_RTS;
|
||||
|
||||
if (mbits & DML_DTR)
|
||||
dhuaddr->dhu_lnctrl |= DHU_LNCTRL_DTR;
|
||||
lnctrl |= DHU_LNCTRL_DTR;
|
||||
else
|
||||
dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_DTR;
|
||||
lnctrl &= ~DHU_LNCTRL_DTR;
|
||||
|
||||
if (mbits & DML_BRK)
|
||||
dhuaddr->dhu_lnctrl |= DHU_LNCTRL_BREAK;
|
||||
lnctrl |= DHU_LNCTRL_BREAK;
|
||||
else
|
||||
dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_BREAK;
|
||||
lnctrl &= ~DHU_LNCTRL_BREAK;
|
||||
|
||||
dhuaddr->dhu_lnctrl = lnctrl;
|
||||
|
||||
(void) splx(s);
|
||||
return (mbits);
|
||||
}
|
||||
|
||||
#endif /* #if NTS > 0 */
|
||||
#endif /* #if NDHU > 0 */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: dhureg.h,v 1.1 1996/03/02 13:30:54 ragge Exp $ */
|
||||
/* $NetBSD: dhureg.h,v 1.2 1996/03/17 22:51:50 ragge Exp $ */
|
||||
/*
|
||||
* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
|
||||
*
|
||||
@ -31,9 +31,18 @@
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
union w_b
|
||||
{
|
||||
u_short word;
|
||||
struct {
|
||||
u_char byte_lo;
|
||||
u_char byte_hi;
|
||||
} bytes;
|
||||
};
|
||||
|
||||
struct DHUregs
|
||||
{
|
||||
volatile u_short dhu_csr; /* Control/Status Register (R/W) */
|
||||
volatile union w_b u_csr; /* Control/Status Register (R/W) */
|
||||
volatile u_short dhu_rbuf; /* Receive Buffer (R only) */
|
||||
#define dhu_txchar dhu_rbuf /* Transmit Character (W only) */
|
||||
volatile u_short dhu_lpr; /* Line Parameter Register (R/W) */
|
||||
@ -44,6 +53,10 @@ struct DHUregs
|
||||
volatile u_short dhu_tbufcnt; /* Transmit Buffer Count (R/W) */
|
||||
};
|
||||
|
||||
#define dhu_csr u_csr.word
|
||||
#define dhu_csr_lo u_csr.bytes.byte_lo
|
||||
#define dhu_csr_hi u_csr.bytes.byte_hi
|
||||
|
||||
typedef struct DHUregs dhuregs;
|
||||
|
||||
/* CSR bits */
|
||||
@ -125,13 +138,3 @@ typedef struct DHUregs dhuregs;
|
||||
|
||||
#define DHU_TBUFAD2_DMA_START 0000200
|
||||
#define DHU_TBUFAD2_TX_ENABLE 0100000
|
||||
|
||||
/* Flags used to monitor modem bits */
|
||||
|
||||
#define DML_DTR 0002
|
||||
#define DML_RTS 0004
|
||||
#define DML_BRK 0020
|
||||
#define DML_CTS 0040
|
||||
#define DML_DCD 0100
|
||||
#define DML_RI 0200
|
||||
#define DML_DSR 0400
|
||||
|
||||
Loading…
Reference in New Issue
Block a user