Support transfers > 4-bytes long by reading and writing using the
controller's packet-based interface instead of non-packet ("normal") mode.
This commit is contained in:
jmcneill
parent
137a13ddd4
commit
df78cf4a7d
@ -1,4 +1,4 @@
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/* $NetBSD: tegra_i2c.c,v 1.1 2015/05/10 23:50:21 jmcneill Exp $ */
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/* $NetBSD: tegra_i2c.c,v 1.2 2015/05/16 21:31:39 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -29,7 +29,7 @@
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#include "locators.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.1 2015/05/10 23:50:21 jmcneill Exp $");
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__KERNEL_RCSID(0, "$NetBSD: tegra_i2c.c,v 1.2 2015/05/16 21:31:39 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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@ -52,6 +52,7 @@ struct tegra_i2c_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_ih;
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u_int sc_port;
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struct i2c_controller sc_ic;
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kmutex_t sc_lock;
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@ -107,6 +108,7 @@ tegra_i2c_attach(device_t parent, device_t self, void *aux)
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sc->sc_bst = tio->tio_bst;
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bus_space_subregion(tio->tio_bst, tio->tio_bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_bsh);
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sc->sc_port = loc->loc_port;
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
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cv_init(&sc->sc_cv, device_xname(self));
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@ -144,7 +146,8 @@ tegra_i2c_init(struct tegra_i2c_softc *sc)
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__SHIFTIN(0x1, I2C_CLK_DIVISOR_HSMODE));
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I2C_WRITE(sc, I2C_INTERRUPT_MASK_REG, 0);
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I2C_WRITE(sc, I2C_CNFG_REG, I2C_CNFG_NEW_MASTER_FSM);
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I2C_WRITE(sc, I2C_CNFG_REG,
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I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN);
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I2C_SET_CLEAR(sc, I2C_SL_CNFG_REG, I2C_SL_CNFG_NEWSL, 0);
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}
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@ -242,43 +245,42 @@ done:
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static int
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tegra_i2c_wait(struct tegra_i2c_softc *sc, int flags)
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{
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const struct timeval timeout = { .tv_sec = 1, .tv_usec = 0 };
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struct timeval tnow, tend;
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uint32_t stat;
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int error;
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int error, retry;
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uint32_t stat = 0;
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getmicrotime(&tnow);
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timeradd(&tnow, &timeout, &tend);
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retry = (flags & I2C_F_POLL) ? 100000 : 100;
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for (;;) {
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getmicrotime(&tnow);
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if (timercmp(&tnow, &tend, >=)) {
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return ETIMEDOUT;
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}
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while (--retry > 0) {
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if ((flags & I2C_F_POLL) == 0) {
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struct timeval trem;
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timersub(&tend, &tnow, &trem);
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const u_int ms = (trem.tv_sec * 1000) +
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(trem.tv_usec / 1000);
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KASSERT(ms > 0);
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error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock,
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max(mstohz(ms), 1));
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max(mstohz(10), 1));
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if (error) {
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return error;
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}
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}
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stat = I2C_READ(sc, I2C_STATUS_REG);
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if ((stat & I2C_STATUS_BUSY) == 0) {
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stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
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if (stat & I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE) {
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break;
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}
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if (flags & I2C_F_POLL) {
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delay(1);
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delay(10);
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}
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}
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if (retry == 0) {
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stat = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
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device_printf(sc->sc_dev, "timed out, status = %#x\n", stat);
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return ETIMEDOUT;
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}
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const uint32_t err_mask =
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I2C_INTERRUPT_STATUS_NOACK |
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I2C_INTERRUPT_STATUS_ARB_LOST |
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I2C_INTERRUPT_MASK_TIMEOUT;
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if (__SHIFTOUT(stat, I2C_STATUS_CMD1_STAT) != 0)
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if (stat & err_mask) {
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device_printf(sc->sc_dev, "error, status = %#x\n", stat);
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return EIO;
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}
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return 0;
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}
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@ -287,33 +289,55 @@ static int
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tegra_i2c_write(struct tegra_i2c_softc *sc, i2c_addr_t addr, const uint8_t *buf,
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size_t buflen, int flags)
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{
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uint32_t data, cnfg;
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size_t n;
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const uint8_t *p = buf;
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size_t n, resid = buflen;
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uint32_t data;
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int retry;
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if (buflen > 4)
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return EINVAL;
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const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
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I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus);
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I2C_WRITE(sc, I2C_CMD_ADDR0_REG, addr << 1);
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for (n = 0, data = 0; n < buflen; n++) {
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data |= (uint32_t)buf[n] << (n * 8);
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/* Generic Header 0 */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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__SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,
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I2C_IOPACKET_WORD0_PROTHDRSZ) |
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__SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) |
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__SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |
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__SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,
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I2C_IOPACKET_WORD0_PROTOCOL) |
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__SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,
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I2C_IOPACKET_WORD0_PKTTYPE));
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/* Generic Header 1 */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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__SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));
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/* I2C Master Transmit Packet Header */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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I2C_IOPACKET_XMITHDR_IE |
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__SHIFTIN((addr << 1), I2C_IOPACKET_XMITHDR_SLAVE_ADDR));
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/* Transmit data */
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while (resid > 0) {
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retry = 10000;
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while (--retry > 0) {
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const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG);
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const u_int cnt =
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__SHIFTOUT(fs, I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT);
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if (cnt > 0)
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break;
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delay(10);
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}
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if (retry == 0) {
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device_printf(sc->sc_dev, "TX FIFO timeout\n");
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return ETIMEDOUT;
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}
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for (n = 0, data = 0; n < min(resid, 4); n++) {
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data |= (uint32_t)p[n] << (n * 8);
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}
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG, data);
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resid -= min(resid, 4);
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p += min(resid, 4);
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}
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I2C_WRITE(sc, I2C_CMD_DATA1_REG, data);
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cnfg = I2C_READ(sc, I2C_CNFG_REG);
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cnfg &= ~I2C_CNFG_DEBOUNCE_CNT;
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cnfg |= __SHIFTIN(2, I2C_CNFG_DEBOUNCE_CNT);
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cnfg &= ~I2C_CNFG_LENGTH;
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cnfg |= __SHIFTIN(buflen - 1, I2C_CNFG_LENGTH);
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cnfg &= ~I2C_CNFG_SLV2;
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cnfg &= ~I2C_CNFG_CMD1;
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cnfg &= ~I2C_CNFG_NOACK;
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cnfg &= ~I2C_CNFG_A_MOD;
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I2C_WRITE(sc, I2C_CNFG_REG, cnfg);
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I2C_SET_CLEAR(sc, I2C_BUS_CONFIG_LOAD_REG,
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I2C_BUS_CONFIG_LOAD_MSTR_CONFIG_LOAD, 0);
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I2C_SET_CLEAR(sc, I2C_CNFG_REG, I2C_CNFG_SEND, 0);
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return tegra_i2c_wait(sc, flags);
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}
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@ -322,30 +346,57 @@ static int
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tegra_i2c_read(struct tegra_i2c_softc *sc, i2c_addr_t addr, uint8_t *buf,
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size_t buflen, int flags)
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{
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uint32_t data, cnfg;
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int error;
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size_t n;
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uint8_t *p = buf;
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size_t n, resid = buflen;
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uint32_t data;
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int error, retry;
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if (buflen > 4)
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return EINVAL;
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const uint32_t istatus = I2C_READ(sc, I2C_INTERRUPT_STATUS_REG);
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I2C_WRITE(sc, I2C_INTERRUPT_STATUS_REG, istatus);
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I2C_WRITE(sc, I2C_CMD_ADDR0_REG, (addr << 1) | 1);
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cnfg = I2C_READ(sc, I2C_CNFG_REG);
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cnfg &= ~I2C_CNFG_SLV2;
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cnfg |= I2C_CNFG_CMD1;
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cnfg &= ~I2C_CNFG_LENGTH;
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cnfg |= __SHIFTIN(buflen - 1, I2C_CNFG_LENGTH);
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I2C_WRITE(sc, I2C_CNFG_REG, cnfg);
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/* Generic Header 0 */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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__SHIFTIN(I2C_IOPACKET_WORD0_PROTHDRSZ_REQ,
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I2C_IOPACKET_WORD0_PROTHDRSZ) |
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__SHIFTIN(sc->sc_port, I2C_IOPACKET_WORD0_CONTROLLERID) |
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__SHIFTIN(1, I2C_IOPACKET_WORD0_PKTID) |
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__SHIFTIN(I2C_IOPACKET_WORD0_PROTOCOL_I2C,
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I2C_IOPACKET_WORD0_PROTOCOL) |
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__SHIFTIN(I2C_IOPACKET_WORD0_PKTTYPE_REQ,
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I2C_IOPACKET_WORD0_PKTTYPE));
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/* Generic Header 1 */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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__SHIFTIN(buflen - 1, I2C_IOPACKET_WORD1_PAYLOADSIZE));
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/* I2C Master Transmit Packet Header */
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I2C_WRITE(sc, I2C_TX_PACKET_FIFO_REG,
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I2C_IOPACKET_XMITHDR_IE | I2C_IOPACKET_XMITHDR_READ |
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__SHIFTIN((addr << 1) | 1, I2C_IOPACKET_XMITHDR_SLAVE_ADDR));
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I2C_SET_CLEAR(sc, I2C_CNFG_REG, I2C_CNFG_SEND, 0);
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error = tegra_i2c_wait(sc, flags);
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if (error)
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if ((error = tegra_i2c_wait(sc, flags)) != 0) {
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return error;
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}
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data = I2C_READ(sc, I2C_CMD_DATA1_REG);
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for (n = 0; n < buflen; n++) {
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buf[n] = (data >> (n * 8)) & 0xff;
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while (resid > 0) {
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retry = 10000;
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while (--retry > 0) {
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const uint32_t fs = I2C_READ(sc, I2C_FIFO_STATUS_REG);
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const u_int cnt =
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__SHIFTOUT(fs, I2C_FIFO_STATUS_RX_FIFO_FULL_CNT);
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if (cnt > 0)
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break;
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delay(10);
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}
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if (retry == 0) {
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device_printf(sc->sc_dev, "RX FIFO timeout\n");
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return ETIMEDOUT;
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}
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data = I2C_READ(sc, I2C_RX_FIFO_REG);
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for (n = 0; n < min(resid, 4); n++) {
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p[n] = (data >> (n * 8)) & 0xff;
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}
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resid -= min(resid, 4);
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p += min(resid, 4);
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}
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return 0;
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@ -1,4 +1,4 @@
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/* $NetBSD: tegra_i2creg.h,v 1.1 2015/05/10 23:50:21 jmcneill Exp $ */
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/* $NetBSD: tegra_i2creg.h,v 1.2 2015/05/16 21:31:39 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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@ -76,7 +76,15 @@
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#define I2C_SL_INT_SET_REG 0x48
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#define I2C_TX_PACKET_FIFO_REG 0x50
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#define I2C_RX_FIFO_REG 0x54
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#define I2C_PACKET_TRANSFER_STATUS_REG 0x58
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#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_COMPLETE __BIT(24)
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#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_PKT_ID __BITS(23,16)
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#define I2C_PACKET_TRANSFER_STATUS_TRANSFER_BYTENUM __BITS(15,4)
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#define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR __BIT(3)
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#define I2C_PACKET_TRANSFER_STATUS_NOACK_FOR_DATA __BIT(2)
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#define I2C_PACKET_TRANSFER_STATUS_ARB_LOST __BIT(1)
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#define I2C_PACKET_TRANSFER_STATUS_CONTROLLER_BUSY __BIT(0)
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#define I2C_FIFO_CONTROL_REG 0x5c
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#define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG __BITS(15,13)
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@ -91,9 +99,9 @@
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#define I2C_FIFO_STATUS_REG 0x60
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#define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON __BIT(25)
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#define I2C_FIFO_STATUS_SLV_TX_FIFO_EMPTY_CNT __BITS(23,20)
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#define I2C_FIFO_STATUS_SLV_RX_FIFO_EMPTY_CNT __BITS(19,16)
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#define I2C_FIFO_STATUS_SLV_RX_FIFO_FULL_CNT __BITS(19,16)
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#define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT __BITS(7,4)
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#define I2C_FIFO_STATUS_RX_FIFO_EMPTY_CNT __BITS(3,0)
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#define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT __BITS(3,0)
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#define I2C_INTERRUPT_MASK_REG 0x64
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#define I2C_INTERRUPT_MASK_TIMEOUT __BIT(8)
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@ -105,6 +113,13 @@
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#define I2C_INTERRUPT_MASK_RFIFO_DATA_REQ __BIT(0)
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#define I2C_INTERRUPT_STATUS_REG 0x68
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#define I2C_INTERRUPT_STATUS_TIMEOUT __BIT(8)
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#define I2C_INTERRUPT_STATUS_PACKET_XFER_COMPLETE __BIT(7)
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#define I2C_INTERRUPT_STATUS_ALL_PACKETS_XFER_COMPLETE __BIT(6)
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#define I2C_INTERRUPT_STATUS_NOACK __BIT(3)
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#define I2C_INTERRUPT_STATUS_ARB_LOST __BIT(2)
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#define I2C_INTERRUPT_STATUS_TFIFO_DATA_REQ __BIT(1)
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#define I2C_INTERRUPT_STATUS_RFIFO_DATA_REQ __BIT(0)
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#define I2C_CLK_DIVISOR_REG 0x6c
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#define I2C_CLK_DIVISOR_STD_FAST_MODE __BITS(31,16)
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@ -131,4 +146,45 @@
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#define I2C_HS_INTERFACE_TIMING0_REG 0x9c
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#define I2C_HS_INTERFACE_TIMING1_REG 0xa0
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/*
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* I/O Packets
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*/
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#define I2C_IOPACKET_WORD0_PROTHDRSZ __BITS(29,28)
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#define I2C_IOPACKET_WORD0_PROTHDRSZ_REQ 0
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#define I2C_IOPACKET_WORD0_PROTHDRSZ_RES 1
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#define I2C_IOPACKET_WORD0_PKTID __BITS(23,16)
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#define I2C_IOPACKET_WORD0_CONTROLLERID __BITS(15,12)
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#define I2C_IOPACKET_WORD0_PROTOCOL __BITS(7,4)
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#define I2C_IOPACKET_WORD0_PROTOCOL_I2C 1
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#define I2C_IOPACKET_WORD0_PKTTYPE __BITS(2,0)
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#define I2C_IOPACKET_WORD0_PKTTYPE_REQ 0
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#define I2C_IOPACKET_WORD0_PKTTYPE_RES 1
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#define I2C_IOPACKET_WORD0_PKTTYPE_INT 2
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#define I2C_IOPACKET_WORD0_PKTTYPE_STOP 3
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#define I2C_IOPACKET_WORD1_PAYLOADSIZE __BITS(11,0)
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#define I2C_IOPACKET_XMITHDR_RESP_PKT_FREQ __BIT(25)
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#define I2C_IOPACKET_XMITHDR_RESP_PKT_ENABLE __BIT(24)
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#define I2C_IOPACKET_XMITHDR_HS_MODE __BIT(22)
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#define I2C_IOPACKET_XMITHDR_CONTINUE_ON_NACK __BIT(21)
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#define I2C_IOPACKET_XMITHDR_SEND_START_BYTE __BIT(20)
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#define I2C_IOPACKET_XMITHDR_READ __BIT(19)
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#define I2C_IOPACKET_XMITHDR_ADDRESS_MODE __BIT(18)
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#define I2C_IOPACKET_XMITHDR_IE __BIT(17)
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#define I2C_IOPACKET_XMITHDR_REPEAT_STARTSTOP __BIT(16)
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#define I2C_IOPACKET_XMITHDR_CONTINUE_XFER __BIT(15)
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#define I2C_IOPACKET_XMITHDR_HS_MASTER_ADDR __BITS(14,12)
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#define I2C_IOPACKET_XMITHDR_SLAVE_ADDR __BITS(9,0)
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#define I2C_IOPACKET_RESPHDR_RFIFO_OVF __BIT(26)
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#define I2C_IOPACKET_RESPHDR_TFIFO_OVF __BIT(25)
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#define I2C_IOPACKET_RESPHDR_TRANSFER_COMPLETE __BIT(24)
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#define I2C_IOPACKET_RESPHDR_TRANSFER_PKT_ID __BITS(23,16)
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#define I2C_IOPACKET_RESPHDR_TRANSFER_BYTENUM __BITS(15,4)
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#define I2C_IOPACKET_RESPHDR_NOACK_FOR_ADDR __BIT(3)
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#define I2C_IOPACKET_RESPHDR_NOACK_FOR_DATA __BIT(2)
|
||||
#define I2C_IOPACKET_RESPHDR_ARB_LOST __BIT(1)
|
||||
#define I2C_IOPACKET_RESPHDR_CONTROLLER_BUSY __BIT(0)
|
||||
|
||||
#endif /* _ARM_TEGRA_I2CREG_H */
|
||||
|
||||
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Reference in New Issue
Block a user