From df5956af2487baf277011b960dbc879939a5b5a7 Mon Sep 17 00:00:00 2001 From: thorpej Date: Fri, 19 Dec 2003 03:33:52 +0000 Subject: [PATCH] Use a register map to find the offsets of various per-channel registers in the BA5 space. --- sys/dev/pci/satalink.c | 124 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 120 insertions(+), 4 deletions(-) diff --git a/sys/dev/pci/satalink.c b/sys/dev/pci/satalink.c index 41d3a4f5f187..2fa962067c78 100644 --- a/sys/dev/pci/satalink.c +++ b/sys/dev/pci/satalink.c @@ -1,4 +1,4 @@ -/* $NetBSD: satalink.c,v 1.3 2003/12/15 00:37:38 thorpej Exp $ */ +/* $NetBSD: satalink.c,v 1.4 2003/12/19 03:33:52 thorpej Exp $ */ /*- * Copyright (c) 2003 The NetBSD Foundation, Inc. @@ -48,6 +48,116 @@ #include +/* + * Register map for BA5 register space, indexed by channel. + */ +static const struct { + bus_addr_t ba5_IDEDMA_CMD; + bus_addr_t ba5_IDEDMA_CTL; + bus_addr_t ba5_IDEDMA_TBL; + bus_addr_t ba5_IDEDMA_CMD2; + bus_addr_t ba5_IDEDMA_CTL2; + bus_addr_t ba5_IDE_TF0; + bus_addr_t ba5_IDE_TF1; + bus_addr_t ba5_IDE_TF2; + bus_addr_t ba5_IDE_TF3; + bus_addr_t ba5_IDE_TF4; + bus_addr_t ba5_IDE_TF5; + bus_addr_t ba5_IDE_TF6; + bus_addr_t ba5_IDE_TF7; + bus_addr_t ba5_IDE_TF8; + bus_addr_t ba5_IDE_RAD; + bus_addr_t ba5_IDE_TF9; + bus_addr_t ba5_IDE_TF10; + bus_addr_t ba5_IDE_TF11; + bus_addr_t ba5_IDE_TF12; + bus_addr_t ba5_IDE_TF13; + bus_addr_t ba5_IDE_TF14; + bus_addr_t ba5_IDE_TF15; + bus_addr_t ba5_IDE_TF16; + bus_addr_t ba5_IDE_TF17; + bus_addr_t ba5_IDE_TF18; + bus_addr_t ba5_IDE_TF19; + bus_addr_t ba5_IDE_RABC; + bus_addr_t ba5_IDE_CMD_STS; + bus_addr_t ba5_IDE_CFG_STS; + bus_addr_t ba5_IDE_DTM; + bus_addr_t ba5_SControl; + bus_addr_t ba5_SStatus; + bus_addr_t ba5_SError; +} satalink_ba5_regmap[] = { + { + .ba5_IDEDMA_CMD = 0x000, + .ba5_IDEDMA_CTL = 0x002, + .ba5_IDEDMA_TBL = 0x004, + .ba5_IDEDMA_CMD2 = 0x010, + .ba5_IDEDMA_CTL2 = 0x012, + .ba5_IDE_TF0 = 0x080, /* wd_data */ + .ba5_IDE_TF1 = 0x081, /* wd_error */ + .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ + .ba5_IDE_TF3 = 0x083, /* wd_sector */ + .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ + .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ + .ba5_IDE_TF6 = 0x086, /* wd_sdh */ + .ba5_IDE_TF7 = 0x087, /* wd_command */ + .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ + .ba5_IDE_RAD = 0x08c, + .ba5_IDE_TF9 = 0x091, /* Features 2 */ + .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ + .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ + .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ + .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ + .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ + .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ + .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ + .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ + .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ + .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ + .ba5_IDE_RABC = 0x09c, + .ba5_IDE_CMD_STS = 0x0a0, + .ba5_IDE_CFG_STS = 0x0a1, + .ba5_IDE_DTM = 0x0b4, + .ba5_SControl = 0x100, + .ba5_SStatus = 0x104, + .ba5_SError = 0x108, + }, + { + .ba5_IDEDMA_CMD = 0x008, + .ba5_IDEDMA_CTL = 0x00a, + .ba5_IDEDMA_TBL = 0x00c, + .ba5_IDEDMA_CMD2 = 0x018, + .ba5_IDEDMA_CTL2 = 0x01a, + .ba5_IDE_TF0 = 0x0c0, /* wd_data */ + .ba5_IDE_TF1 = 0x0c1, /* wd_error */ + .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ + .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ + .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ + .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ + .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ + .ba5_IDE_TF7 = 0x0c7, /* wd_command */ + .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ + .ba5_IDE_RAD = 0x0cc, + .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ + .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ + .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ + .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ + .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ + .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ + .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ + .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ + .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ + .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ + .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ + .ba5_IDE_RABC = 0x0dc, + .ba5_IDE_CMD_STS = 0x0e0, + .ba5_IDE_CFG_STS = 0x0e1, + .ba5_IDE_DTM = 0x0f4, + .ba5_SControl = 0x180, + .ba5_SStatus = 0x184, + .ba5_SError = 0x188, + } +}; + static int satalink_match(struct device *, struct cfdata *, void *); static void satalink_attach(struct device *, struct device *, void *); @@ -105,6 +215,9 @@ ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA)); } +#define BA5_READ_4(sc, chan, reg) \ + ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) + static __inline void ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) { @@ -119,6 +232,9 @@ ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) } } +#define BA5_WRITE_4(sc, chan, reg, val) \ + ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) + static void sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) { @@ -258,13 +374,13 @@ sii3112_drv_probe(struct channel_softc *chp) */ scontrol |= SControl_IPM_NONE; - ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); + BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); delay(500); scontrol &= ~SControl_DET_INIT; - ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); + BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); delay(500); - sstatus = ba5_read_4(sc, chp->channel == 0 ? 0x104 : 0x184); + sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); switch (sstatus & SStatus_DET_mask) { case SStatus_DET_NODEV: /* No device; be silent. */