factor out common reset code.
This commit is contained in:
christos
parent
6ebb93d58e
commit
decf940784
@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.121 2009/01/27 21:13:57 ad Exp $ */
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/* $NetBSD: machdep.c,v 1.122 2009/01/27 21:59:25 christos Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008
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@ -112,7 +112,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.121 2009/01/27 21:13:57 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.122 2009/01/27 21:59:25 christos Exp $");
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/* #define XENDEBUG_LOW */
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@ -1546,44 +1546,7 @@ cpu_reset(void)
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HYPERVISOR_reboot();
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#else
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/*
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* The keyboard controller has 4 random output pins, one of which is
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* connected to the RESET pin on the CPU in many PCs. We tell the
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* keyboard controller to pulse this line a couple of times.
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*/
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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/*
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* Attempt to force a reset via the Reset Control register at
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* I/O port 0xcf9. Bit 2 forces a system reset when it
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* transitions from 0 to 1. Bit 1 selects the type of reset
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* to attempt: 0 selects a "soft" reset, and 1 selects a
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* "hard" reset. We try a "hard" reset. The first write sets
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* bit 1 to select a "hard" reset and clears bit 2. The
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* second write forces a 0 -> 1 transition in bit 2 to trigger
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* a reset.
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*/
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outb(0xcf9, 0x2);
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outb(0xcf9, 0x6);
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delay(500000); /* wait 0.5 sec to see if that did it */
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/*
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* Attempt to force a reset via the Fast A20 and Init register
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* at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
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* Bit 0 asserts INIT# when set to 1. We are careful to only
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* preserve bit 1 while setting bit 0. We also must clear bit
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* 0 before setting it if it isn't already clear.
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*/
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b = inb(0x92);
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if (b != 0xff) {
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if ((b & 0x1) != 0)
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outb(0x92, b & 0xfe);
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outb(0x92, b | 0x1);
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delay(500000); /* wait 0.5 sec to see if that did it */
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}
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x86_reset();
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/*
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* Try to cause a triple fault and watchdog reset by making the IDT
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.656 2009/01/27 21:13:57 ad Exp $ */
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/* $NetBSD: machdep.c,v 1.657 2009/01/27 21:59:24 christos Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006, 2008 The NetBSD Foundation, Inc.
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@ -65,7 +65,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.656 2009/01/27 21:13:57 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.657 2009/01/27 21:59:24 christos Exp $");
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#include "opt_beep.h"
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#include "opt_compat_ibcs2.h"
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@ -1671,44 +1671,7 @@ cpu_reset()
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outl(0xcfc, 0xf);
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}
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/*
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* The keyboard controller has 4 random output pins, one of which is
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* connected to the RESET pin on the CPU in many PCs. We tell the
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* keyboard controller to pulse this line a couple of times.
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*/
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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/*
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* Attempt to force a reset via the Reset Control register at
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* I/O port 0xcf9. Bit 2 forces a system reset when it
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* transitions from 0 to 1. Bit 1 selects the type of reset
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* to attempt: 0 selects a "soft" reset, and 1 selects a
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* "hard" reset. We try a "hard" reset. The first write sets
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* bit 1 to select a "hard" reset and clears bit 2. The
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* second write forces a 0 -> 1 transition in bit 2 to trigger
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* a reset.
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*/
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outb(0xcf9, 0x2);
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outb(0xcf9, 0x6);
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delay(500000); /* wait 0.5 sec to see if that did it */
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/*
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* Attempt to force a reset via the Fast A20 and Init register
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* at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
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* Bit 0 asserts INIT# when set to 1. We are careful to only
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* preserve bit 1 while setting bit 0. We also must clear bit
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* 0 before setting it if it isn't already clear.
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*/
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b = inb(0x92);
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if (b != 0xff) {
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if ((b & 0x1) != 0)
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outb(0x92, b & 0xfe);
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outb(0x92, b | 0x1);
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delay(500000); /* wait 0.5 sec to see if that did it */
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}
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x86_reset();
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/*
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* Try to cause a triple fault and watchdog reset by making the IDT
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.10 2008/12/19 15:11:55 cegger Exp $ */
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/* $NetBSD: cpufunc.h,v 1.11 2009/01/27 21:59:24 christos Exp $ */
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/*-
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* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
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@ -106,6 +106,8 @@ void x86_write_psl(u_long);
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u_long x86_read_flags(void);
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void x86_write_flags(u_long);
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void x86_reset(void);
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/*
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* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
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*
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@ -1,4 +1,4 @@
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/* $NetBSD: x86_machdep.c,v 1.27 2008/12/15 22:20:52 cegger Exp $ */
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/* $NetBSD: x86_machdep.c,v 1.28 2009/01/27 21:59:24 christos Exp $ */
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/*-
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* Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.27 2008/12/15 22:20:52 cegger Exp $");
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__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.28 2009/01/27 21:59:24 christos Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -776,3 +776,47 @@ initx86_load_memmap(paddr_t first_avail)
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return 0;
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}
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#endif
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void
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x86_reset(void)
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{
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uint8_t b;
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/*
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* The keyboard controller has 4 random output pins, one of which is
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* connected to the RESET pin on the CPU in many PCs. We tell the
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* keyboard controller to pulse this line a couple of times.
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*/
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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delay(100000);
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/*
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* Attempt to force a reset via the Reset Control register at
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* I/O port 0xcf9. Bit 2 forces a system reset when it
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* transitions from 0 to 1. Bit 1 selects the type of reset
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* to attempt: 0 selects a "soft" reset, and 1 selects a
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* "hard" reset. We try a "hard" reset. The first write sets
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* bit 1 to select a "hard" reset and clears bit 2. The
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* second write forces a 0 -> 1 transition in bit 2 to trigger
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* a reset.
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*/
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outb(0xcf9, 0x2);
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outb(0xcf9, 0x6);
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DELAY(500000); /* wait 0.5 sec to see if that did it */
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/*
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* Attempt to force a reset via the Fast A20 and Init register
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* at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
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* Bit 0 asserts INIT# when set to 1. We are careful to only
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* preserve bit 1 while setting bit 0. We also must clear bit
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* 0 before setting it if it isn't already clear.
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*/
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b = inb(0x92);
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if (b != 0xff) {
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if ((b & 0x1) != 0)
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outb(0x92, b & 0xfe);
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outb(0x92, b | 0x1);
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DELAY(500000); /* wait 0.5 sec to see if that did it */
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}
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}
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