Use bus_dma(9) to instruct IOASIC DMA to load transferring addresses,
eliminating MIPS cache machinary exposure here.
This commit is contained in:
nisimura
parent
f9e6343390
commit
de01642cac
@ -1,4 +1,4 @@
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/* $NetBSD: asc_ioasic.c,v 1.6 2000/03/06 03:09:43 mhitch Exp $ */
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/* $NetBSD: asc_ioasic.c,v 1.7 2000/06/03 07:55:17 nisimura Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -37,7 +37,7 @@
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.6 2000/03/06 03:09:43 mhitch Exp $");
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__KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.7 2000/06/03 07:55:17 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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@ -61,16 +61,18 @@ __KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.6 2000/03/06 03:09:43 mhitch Exp $"
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struct asc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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bus_space_handle_t sc_scsi_bsh;
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap;
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bus_space_tag_t sc_bst; /* bus space tag */
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bus_space_handle_t sc_bsh; /* bus space handle */
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bus_space_handle_t sc_scsi_bsh; /* ASC register handle */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dmamap */
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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size_t sc_dmasize;
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int sc_active; /* DMA active ? */
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int sc_ispullup; /* DMA into main memory? */
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size_t *sc_dmalen;
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size_t sc_dmasize;
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unsigned sc_flags;
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#define ASC_ISPULLUP 0x0001
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#define ASC_DMAACTIVE 0x0002
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#define ASC_MAPLOADED 0x0004
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};
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static int asc_ioasic_match __P((struct device *, struct cfdata *, void *));
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@ -141,11 +143,15 @@ asc_ioasic_attach(parent, self, aux)
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sc->sc_glue = &asc_ioasic_glue;
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asc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst;
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asc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
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asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
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if (bus_space_subregion(asc->sc_bst,
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asc->sc_bsh,
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if (bus_space_subregion(asc->sc_bst, asc->sc_bsh,
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IOASIC_SLOT_12_START, 0x100, &asc->sc_scsi_bsh)) {
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printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
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printf(": failed to map device registers\n");
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return;
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}
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asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
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if (bus_dmamap_create(asc->sc_dmat, NBPG * 2,
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2, NBPG, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap)) {
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printf(": failed to create DMA map\n");
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return;
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}
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@ -207,7 +213,115 @@ asc_ioasic_reset(sc)
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0);
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asc->sc_active = 0;
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if (asc->sc_flags & ASC_MAPLOADED)
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
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}
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#define TWOPAGE(a) (NBPG*2 - ((a) & (NBPG-1)))
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int
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asc_ioasic_setup(sc, addr, len, ispullup, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int ispullup;
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size_t *dmasize;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr, scr, *p;
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size_t size;
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vaddr_t cp;
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paddr_t ptr0, ptr1;
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NCR_DMA(("%s: start %d@%p,%s\n", sc->sc_dev.dv_xname,
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*asc->sc_dmalen, *asc->sc_dmaaddr, ispullup ? "IN" : "OUT"));
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/* upto two 4KB pages */
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size = min(*dmasize, TWOPAGE((size_t)*addr));
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asc->sc_dmaaddr = addr;
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asc->sc_dmalen = len;
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asc->sc_dmasize = size;
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asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0;
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*dmasize = size; /* return trimmed transfer size */
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/* stop DMA engine first */
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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/* have dmamap for the transfering addresses */
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if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap,
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*addr, size,
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NULL /* kernel address */, BUS_DMA_NOWAIT))
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panic("%s: cannot allocate DMA address", sc->sc_dev.dv_xname);
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/* take care of 8B constraint on starting address */
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cp = (vaddr_t)*addr;
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if ((cp & 7) == 0) {
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/* comfortably aligned to 8B boundary */
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0);
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}
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else {
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/* truncate to the boundary */
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p = (u_int32_t *)(cp & ~7);
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/* how many 16bit quantities in subject */
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scr = (cp >> 1) & 3;
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/* trim down physical address too */
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asc->sc_dmamap->dm_segs[0].ds_addr &= ~7;
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if ((asc->sc_flags & ASC_ISPULLUP) == 0) {
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/* push down to SCSI device */
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scr |= 4;
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/* round up physical address in this case */
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asc->sc_dmamap->dm_segs[0].ds_addr += 8;
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}
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/* pack fixup data in SDR0/SDR1 pair and instruct SCR */
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR0, p[0]);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR1, p[1]);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SCR, scr);
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}
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ptr0 = asc->sc_dmamap->dm_segs[0].ds_addr;
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ptr1 = (asc->sc_dmamap->dm_nsegs > 1)
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? asc->sc_dmamap->dm_segs[1].ds_addr : ~0;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_DMAPTR,
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IOASIC_DMA_ADDR(ptr0));
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_NEXTPTR,
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IOASIC_DMA_ADDR(ptr1));
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/* synchronize dmamap contents with memory image */
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, size,
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(ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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asc->sc_flags |= ASC_MAPLOADED;
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return 0;
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}
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void
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asc_ioasic_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr;
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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if (asc->sc_flags & ASC_ISPULLUP)
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ssr |= IOASIC_CSR_SCSI_DIR;
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else {
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/* ULTRIX does in this way */
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ssr &= ~IOASIC_CSR_SCSI_DIR;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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}
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ssr |= IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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asc->sc_flags |= ASC_DMAACTIVE;
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}
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#define SCRDEBUG(x)
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@ -220,8 +334,8 @@ asc_ioasic_intr(sc)
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int trans, resid;
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u_int tcl, tcm, ssr, scr, intr;
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if (asc->sc_active == 0)
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panic("dmaintr: DMA wasn't active");
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if ((asc->sc_flags & ASC_DMAACTIVE) == 0)
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panic("ioasic_intr: DMA wasn't active");
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#define IOASIC_ASC_ERRORS \
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(IOASIC_INTR_SCSI_PTR_LOAD|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E)
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@ -232,15 +346,17 @@ asc_ioasic_intr(sc)
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* Check for these bits here, and clear them if needed.
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*/
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intr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR);
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if ((intr & IOASIC_ASC_ERRORS) != 0)
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR,
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intr & ~IOASIC_ASC_ERRORS);
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if ((intr & IOASIC_ASC_ERRORS) != 0) {
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intr &= ~IOASIC_ASC_ERRORS;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR, intr);
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}
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/* DMA has stopped */
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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asc->sc_active = 0;
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asc->sc_flags &= ~ASC_DMAACTIVE;
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if (asc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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@ -252,7 +368,7 @@ asc_ioasic_intr(sc)
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}
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resid = 0;
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if (!asc->sc_ispullup &&
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if ((asc->sc_flags & ASC_ISPULLUP) == 0 &&
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(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("ioasic_intr: empty FIFO of %d ", resid));
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DELAY(1);
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@ -270,8 +386,14 @@ asc_ioasic_intr(sc)
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NCR_DMA(("ioasic_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
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tcl, tcm, trans, resid));
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, asc->sc_dmasize,
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(asc->sc_flags & ASC_ISPULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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scr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR);
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if (asc->sc_ispullup && scr != 0) {
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if ((asc->sc_flags & ASC_ISPULLUP) && scr != 0) {
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u_int32_t ptr;
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u_int16_t *p;
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union {
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@ -301,121 +423,32 @@ SCRDEBUG(("SCSI_SCR -> %x, DMAPTR: %p\n", scr, (void *)ptr));
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p[2] = scratch.half[2];
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}
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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asc->sc_flags &= ~ASC_MAPLOADED;
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*asc->sc_dmalen -= trans;
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*asc->sc_dmaaddr += trans;
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return 0;
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}
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#define TWOPAGE(a) (NBPG*2 - ((a) & (NBPG-1)))
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int
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asc_ioasic_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr, scr;
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size_t size;
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vaddr_t cp;
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paddr_t ptr0, ptr1;
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extern paddr_t kvtophys __P((vaddr_t));
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asc->sc_dmaaddr = addr;
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asc->sc_dmalen = len;
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asc->sc_ispullup = datain;
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NCR_DMA(("ioasic_setup: start %d@%p %s\n",
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*asc->sc_dmalen, *asc->sc_dmaaddr, datain ? "IN" : "OUT"));
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/* upto two 4KB pages */
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size = min(*dmasize, TWOPAGE((size_t)*addr));
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*dmasize = asc->sc_dmasize = size;
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NCR_DMA(("ioasic_setup: dmasize = %d\n", asc->sc_dmasize));
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/* stop DMA engine first */
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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/* If R4K, writeback and invalidate the buffer */
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if (CPUISMIPS3)
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mips3_HitFlushDCache((vaddr_t)*addr, size);
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cp = (vaddr_t)*addr;
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if ((cp & 7) == 0)
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scr = 0;
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else {
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u_int32_t *p;
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p = (u_int32_t *)(cp & ~7);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR0, p[0]);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR1, p[1]);
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scr = (cp >> 1) & 3;
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cp &= ~7;
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if (asc->sc_ispullup == 0) {
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scr |= 4;
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cp += 8;
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}
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SCRDEBUG(("SCSI_SCR <- %x, DMAPTR: %p\n", scr, (void *)kvtophys(cp)));
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}
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ptr0 = kvtophys(cp);
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cp = mips_trunc_page(cp + NBPG);
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ptr1 = ((vaddr_t)*addr + size > cp) ? kvtophys(cp) : ~0;
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/* If not R4K, need to invalidate cache lines for physical segments */
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if (!CPUISMIPS3 && datain) {
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if (ptr1 == ~0)
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr0), size);
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else {
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int size0 = NBPG - (ptr0 & (NBPG - 1));
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int size1 = size - size0;
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr0), size0);
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MachFlushDCache(MIPS_PHYS_TO_KSEG0(ptr1), size1);
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}
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}
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, scr);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_DMAPTR, IOASIC_DMA_ADDR(ptr0));
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_NEXTPTR, IOASIC_DMA_ADDR(ptr1));
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return 0;
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}
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void
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asc_ioasic_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr;
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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if (asc->sc_ispullup)
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ssr |= IOASIC_CSR_SCSI_DIR;
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else {
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/* ULTRIX does in this way */
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ssr &= ~IOASIC_CSR_SCSI_DIR;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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}
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ssr |= IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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asc->sc_active = 1;
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}
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/* NEVER CALLED BY MI 53C9x ENGINE INDEED */
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void
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asc_ioasic_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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if (asc->sc_flags & ASC_MAPLOADED) {
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, asc->sc_dmasize,
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(asc->sc_flags & ASC_ISPULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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}
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asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
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}
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static u_char
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@ -457,7 +490,7 @@ asc_dma_isactive(sc)
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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return asc->sc_active;
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return !!(asc->sc_flags & ASC_DMAACTIVE);
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}
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static void
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