A12 crossbar switch driver.
This commit is contained in:
ross
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/* $NetBSD: if_xb.c,v 1.1 1998/09/23 21:14:58 ross Exp $ */
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/* [Notice revision 2.2]
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* Copyright (c) 1997, 1998 Avalon Computer Systems, Inc.
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* All rights reserved.
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*
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* Author: Ross Harvey
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright and
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* author notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* 4. This copyright will be assigned to The NetBSD Foundation on
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* 1/1/2000 unless these terms (including possibly the assignment
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* date) are updated in writing by Avalon prior to the latest specified
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* assignment date.
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*
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* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AVALON OR THE CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Notes.
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*
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* Since the NetBSD build rules force the use of function prototypes, even on
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* functions that are defined before they are called, I've taken advantage of
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* the opportunity and organized this module in top down fashion, with
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* functions generally calling down the page rather than up. It's different.
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* I think I'm getting to like it this way.
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*
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* The crossbar interface is not exactly a peripheral device, and it cannot
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* appear on anything other than an alpha-based Avalon A12. The crossbar
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* controller is built into the core logic.
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*
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* If this version of the driver supports MPS transport, it may have some
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* large static data declarations. Don't worry about it, as Avalon a12
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* support should not appear in a GENERIC or INSTALL kernel.
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*
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* (Every A12 ever shipped had 512 MB per CPU except one site, which had 256
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* MB. Partly has a result of this, it is unlikely that a kernel configured
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* for an A12 would be exactly the thing to use on most workstations, so we
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* don't really need to worry that we might be configured in a generic or
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* site-wide kernel image.)
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*
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* This preliminary crossbar driver supports IP transport using PIO. Although
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* it would be nice to have a DMA driver, do note that the crossbar register
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* port is 128 bits wide, so we have 128-bit PIO. (The 21164 write buffer
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* will combine two 64-bit stores before they get off-chip.) Also, the rtmon
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* driver wasn't DMA either, so at least the NetBSD driver is as good as any
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* other that exists now.
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*
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* We'll do DMA and specialized transport ops later. Given the high speed of
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* the PIO mode, no current applications require DMA bandwidth, but everyone
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* benefits from low latency. The PIO mode is actually lower in latency
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* anyway.
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*/
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#include "opt_avalon_a12.h" /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: if_xb.c,v 1.1 1998/09/23 21:14:58 ross Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/mbuf.h>
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#include <sys/sockio.h>
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#include <vm/vm.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/route.h>
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#include <netinet/in.h>
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#include <netinet/in_var.h>
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#include <machine/autoconf.h>
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#include <machine/rpb.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/dec/clockvar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/a12creg.h>
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#include <alpha/pci/a12cvar.h>
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#include <alpha/pci/pci_a12.h>
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#if 1
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#define XB_DEBUG xb_debug
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#else
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#define XB_DEBUG 0
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#endif
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#undef Static
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#if 1
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#define Static
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#else
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#define Static static
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#endif
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#define IF_XB() /* Generate ctags(1) key */
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#define XBAR_MTU (9*1024) /* Quite an arbitrary number */
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#define XBAR_MAXFRAMEHDR 48 /* Used to compute if_mtu */
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#define XB_DEFAULT_MTU() (XBAR_MTU - XBAR_MAXFRAMEHDR)
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#define FIFO_WORDCOUNT 60
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static int xb_put_blk __P((struct mbuf *));
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static int xb_put __P((struct mbuf *));
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static long xb_fifo_empty(void);
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int xbmatch __P((struct device *, struct cfdata *, void *));
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void xbattach __P((struct device *, struct device *, void *));
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struct xb_softc {
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struct device d;
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} xb_softc;
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struct cfattach xb_ca = {
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sizeof(struct xb_softc), xbmatch, xbattach,
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};
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extern struct cfdriver xb_cd;
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long *xb_incoming;
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int xb_incoming_max = XBAR_MTU;
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typedef struct ccode_struct {
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int64_t lo64, /* magic channel address s-word, high part*/
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hi64; /* magic channel address s-word, low part */
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} ccode_type;
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/*
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* Switch channel codes. Prepending one of these words will get you through
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* the switch, which will eat the word, open the addressed channel, and
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* forward the rest of the switch frame. Obviously, this helps if the second
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* switch word in the frame is the address word for a cascaded switch. (This
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* can be repeated for an arbitrary depth of MSN.) The words aren't quite as
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* wierd as they look: the switch is really lots of narrow switches in an
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* array, and they don't switch an even number of hex digits. Also, there is
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* a parity bit on most of the subunits.
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*/
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ccode_type channel[]={
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{ 0x0000000000000000, 0x0000000000000000 },
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{ 0x8882108421084210, 0x1104210842108421 },
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{ 0x4441084210842108, 0x2208421084210842 },
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{ 0xccc318c6318c6318, 0x330c6318c6318c63 },
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{ 0x2220842108421084, 0x4410842108421084 },
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{ 0xaaa294a5294a5294, 0x5514a5294a5294a5 },
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{ 0x66618c6318c6318c, 0x6618c6318c6318c6 },
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{ 0xeee39ce739ce739c, 0x771ce739ce739ce7 },
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{ 0x1110421084210842, 0x8821084210842108 },
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{ 0x99925294a5294a52, 0x9925294a5294a529 },
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{ 0x55514a5294a5294a, 0xaa294a5294a5294a },
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{ 0xddd35ad6b5ad6b5a, 0xbb2d6b5ad6b5ad6b },
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{ 0x3330c6318c6318c6, 0xcc318c6318c6318c },
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{ 0xbbb2d6b5ad6b5ad6, 0xdd35ad6b5ad6b5ad }
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};
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Static enum xb_intr_rcv_state_t {
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XBIR_PKTHDR = 0, XBIR_TRANS
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} xb_intr_rcv_state;
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struct xb_config { int am_i_used; } xb_configuration;
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Static struct ifnet xbi;
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Static int frame_len;
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static int xb_debug;
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Static void xb_start __P((struct ifnet *));
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Static void xb_mcrp_write __P((long *, int, int));
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static __inline void xb_onefree __P((void));
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static long set_interrupt_on_fifo_empty(void);
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static void xb_init(struct ifnet *);
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static int xb_intr __P((void *));
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static void xb_intr_rcv __P((void));
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Static void quickload __P((volatile long *, long *));
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static void xb_init_config __P((struct xb_config *, int));
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static int xb_output __P((struct ifnet *, struct mbuf *, struct sockaddr *,
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struct rtentry *));
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static int xb_ioctl __P((struct ifnet *, u_long, caddr_t));
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static void xb_stop __P((void));
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static void a12_xbar_setup __P((void));
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/* There Can Be Only One */
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int xbfound;
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int
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xbmatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pcibus_attach_args *pba = aux;
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return cputype == ST_AVALON_A12
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&& strcmp(pba->pba_busname, xb_cd.cd_name) == 0
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&& !xbfound;
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}
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void
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xbattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct xb_config *ccp;
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bcopy(self->dv_xname, xbi.if_xname, IFNAMSIZ);
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xbfound = 1;
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ccp = &xb_configuration;
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xb_init_config(ccp, 1);
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printf(": driver %s mtu %d\n", "$Revision: 1.1 $", xbi.if_mtu);
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}
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static void
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xb_init_config(ccp, mallocsafe)
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struct xb_config *ccp;
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int mallocsafe;
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{
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/*
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* The driver actually only needs about 64 bytes of buffer but with a
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* nice contiguous frame we can call m_devget()
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*/
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if (mallocsafe && xb_incoming == NULL) {
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xb_incoming = malloc(xb_incoming_max, M_DEVBUF, M_NOWAIT);
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if (xb_incoming == NULL)
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DIE();
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}
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a12_xbar_setup();
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a12_intr_register_xb(xb_intr);
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}
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/*
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* From The A12 Theory of Operation. Used with permission.
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* --- --- ------ -- ---------
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*
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* Message Channel Status Register
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*
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* 31 0
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* | |
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* 10987654 32109876 54321098 76543210
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*
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* ........ ........ 0oiefaAr TR...... MCSR
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*
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* Field Type Name Function
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*
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* R R,W1C RBC Receive Block Complete
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* T R,W1C TBC Transmit Block Complete
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* r R IMP Incoming message pending
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* A R IMFAE Incoming message fifo almost empty
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* a R OMFAF Outgoing message fifo almost full
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* f R OMFF Outgoing message fifo full
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* e R OMFE Outgoing message fifo empty
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* i R DMAin Incoming DMA channel armed
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* o R DMAout Outgoing DMA channel armed
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*
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* Interrupts Generated from MCSR
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*
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* IMChInt <= (RBC or IMP) and not DMAin
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* OMChInt <= ((TBC and not OMFAF) or (OMFE and OMR.E(6))
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* ) and not DMAout
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*
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*/
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static int
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xb_intr(p)
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void *p;
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{
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int n;
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long mcsrval;
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/*
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* The actual conditions under which this interrupt is generated are
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* a bit complicated, and no status flag is available that reads out
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* the final values of the interrupt inputs. But, it doesn't really
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* matter. Simply check for receive data and transmitter IFF_OACTIVE.
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*/
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while ((mcsrval = REGVAL(A12_MCSR)) & A12_MCSR_IMP)
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for(n = mcsrval & A12_MCSR_IMFAE ? 1 : 5; n; --n)
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xb_intr_rcv();
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if (xbi.if_flags & IFF_OACTIVE
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&& mcsrval & A12_MCSR_OMFE) {
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xbi.if_flags &= ~IFF_OACTIVE;
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REGVAL(A12_OMR) &= ~A12_OMR_OMF_ENABLE;
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alpha_wmb();
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xb_start(&xbi);
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}
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return 0;
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}
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/*
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* The interface logic will shoot us down with MCE (Missing Close Error) or
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* ECE (Embedded Close Error) if we aren't in sync with the hardware w.r.t.
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* frame boundaries. As those are panic-level errors: Don't Get Them.
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*/
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static void
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xb_intr_rcv()
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{
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struct mbuf *m;
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long frameword[2];
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static long *xb_ibp;
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int s = 0; /* XXX gcc */
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switch (xb_intr_rcv_state) {
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case XBIR_PKTHDR:
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xb_ibp = xb_incoming;
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quickload(REGADDR(A12_FIFO), frameword); /* frame_len >= 16 */
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frame_len = frameword[0];
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if (!(20 <= frame_len && frame_len+16 <= xb_incoming_max))
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DIE();
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/*
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* The extra word when frames are of an aligned size is due
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* to the way the the output routines work. After the mbuf is
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* sent xb_put_blk(NULL) is called. If there is a leftover
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* 127-bit-or-less fragment then the close word rides on it,
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* otherwise it gets an entire 128 bits of zeroes.
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*/
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if (frame_len & 0xf)
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frame_len = (frame_len + 0xf) >> 4;
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else frame_len = (frame_len >> 4) + 1;
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--frame_len; /* we read the frame len + the first packet int64 */
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*xb_ibp++ = frameword[1];
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xb_intr_rcv_state = XBIR_TRANS;
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break;
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case XBIR_TRANS:
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if (frame_len > 1)
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quickload(REGADDR(A12_FIFO), frameword);
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else if (frame_len == 1) {
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quickload(REGADDR(A12_FIFO_LWE), frameword);
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xb_intr_rcv_state = XBIR_PKTHDR;
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} else if (XB_DEBUG)
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DIE();
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--frame_len;
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xb_ibp[0] = frameword[0];
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xb_ibp[1] = frameword[1];
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xb_ibp += 2;
|
||||||
|
if (xb_intr_rcv_state == XBIR_PKTHDR) {
|
||||||
|
if (XB_DEBUG) {
|
||||||
|
s = splimp();
|
||||||
|
if (s != splimp())
|
||||||
|
DIE();
|
||||||
|
}
|
||||||
|
++xbi.if_ipackets;
|
||||||
|
if (IF_QFULL(&ipintrq)) {
|
||||||
|
IF_DROP(&ipintrq);
|
||||||
|
++xbi.if_iqdrops;
|
||||||
|
} else {
|
||||||
|
m = m_devget((caddr_t)xb_incoming,
|
||||||
|
(caddr_t)xb_ibp - (caddr_t)xb_incoming,
|
||||||
|
0, &xbi, 0L);
|
||||||
|
if (m) {
|
||||||
|
xbi.if_ibytes += m->m_pkthdr.len;
|
||||||
|
IF_ENQUEUE(&ipintrq, m);
|
||||||
|
} else
|
||||||
|
++xbi.if_ierrors;
|
||||||
|
}
|
||||||
|
if (XB_DEBUG)
|
||||||
|
splx(s);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
DIE();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Make it easy for gcc to load a[0..1] without interlocking between
|
||||||
|
* a[0] and a[1]. (If it did, that would be two external bus cycles.)
|
||||||
|
*/
|
||||||
|
Static void
|
||||||
|
quickload(volatile long *a, long *b)
|
||||||
|
{
|
||||||
|
long t1,t2;
|
||||||
|
|
||||||
|
t1 = a[0];
|
||||||
|
t2 = a[1];
|
||||||
|
b[0] = t1;
|
||||||
|
b[1] = t2;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Verify during debugging that we have not overflowed the FIFO
|
||||||
|
*/
|
||||||
|
static __inline void
|
||||||
|
xb_onefree()
|
||||||
|
{
|
||||||
|
if (XB_DEBUG && REGVAL(A12_MCSR) & A12_MCSR_OMFF)
|
||||||
|
DIE();
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
xb_init(ifp)
|
||||||
|
struct ifnet *ifp;
|
||||||
|
{
|
||||||
|
ifp->if_flags |= IFF_RUNNING;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
xb_stop()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
xb_ioctl(ifp, cmd, data)
|
||||||
|
struct ifnet *ifp;
|
||||||
|
u_long cmd;
|
||||||
|
caddr_t data;
|
||||||
|
{
|
||||||
|
struct ifaddr *ifa = (struct ifaddr *)data;
|
||||||
|
int s, error = 0;
|
||||||
|
|
||||||
|
s = splimp();
|
||||||
|
switch (cmd) {
|
||||||
|
case SIOCSIFADDR:
|
||||||
|
xbi.if_flags |= IFF_UP;
|
||||||
|
switch (ifa->ifa_addr->sa_family) {
|
||||||
|
#ifdef INET
|
||||||
|
case AF_INET:
|
||||||
|
xb_init(ifp);
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
|
default:
|
||||||
|
xb_init(ifp);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case SIOCSIFFLAGS:
|
||||||
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
||||||
|
(ifp->if_flags & IFF_RUNNING) != 0) {
|
||||||
|
xb_stop();
|
||||||
|
ifp->if_flags &= ~IFF_RUNNING;
|
||||||
|
} else if ((ifp->if_flags & IFF_UP) != 0 &&
|
||||||
|
(ifp->if_flags & IFF_RUNNING) == 0) {
|
||||||
|
xb_start(ifp);
|
||||||
|
} else
|
||||||
|
xb_init(ifp);
|
||||||
|
if (ifp->if_flags & IFF_DEBUG)
|
||||||
|
xb_debug = 1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
error = EINVAL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
splx(s);
|
||||||
|
return error;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* XXX - someday, keep a software copy of A12_OMR. We can execute up to
|
||||||
|
* 200 or 300 instructions in the time it takes to do the read part of an
|
||||||
|
* external bus cycle RMW op. (Or 10 - 20 cache cycles.)
|
||||||
|
*/
|
||||||
|
static __inline long
|
||||||
|
xb_fifo_empty(void)
|
||||||
|
{
|
||||||
|
return REGVAL(A12_MCSR) & A12_MCSR_OMFE;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* rtmon frames
|
||||||
|
*
|
||||||
|
* [ (... data) : commid : sourcepid : dstpid : ktype : length : frametype ]
|
||||||
|
*
|
||||||
|
* At the moment, NetBSD ip frames are not compatible with rtmon frames:
|
||||||
|
*
|
||||||
|
* [ ... data : length ]
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
xb_output(ifp, m0, dst, rt0)
|
||||||
|
struct ifnet *ifp;
|
||||||
|
struct mbuf *m0;
|
||||||
|
struct sockaddr *dst;
|
||||||
|
struct rtentry *rt0;
|
||||||
|
{
|
||||||
|
int i,s;
|
||||||
|
struct mbuf *m = m0;
|
||||||
|
char *lladdr;
|
||||||
|
caddr_t xbh;
|
||||||
|
long xbo_framesize;
|
||||||
|
struct sockaddr_dl *llsa;
|
||||||
|
int xbaddr;
|
||||||
|
|
||||||
|
#ifdef DIAGNOSTIC
|
||||||
|
if (ifp != &xbi)
|
||||||
|
DIE();
|
||||||
|
#endif
|
||||||
|
if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) != (IFF_UP|IFF_RUNNING)) {
|
||||||
|
m_freem(m);
|
||||||
|
return ENETDOWN;
|
||||||
|
}
|
||||||
|
ifp->if_lastchange = time;
|
||||||
|
/*
|
||||||
|
* We want an IP packet with a link level route, on a silver platter.
|
||||||
|
*/
|
||||||
|
if (rt0 == NULL
|
||||||
|
|| (rt0->rt_flags & (RTF_GATEWAY | RTF_LLINFO))
|
||||||
|
|| (llsa = (struct sockaddr_dl *)rt0->rt_gateway) == NULL
|
||||||
|
|| llsa->sdl_family != AF_LINK
|
||||||
|
|| llsa->sdl_slen != 0) {
|
||||||
|
++ifp->if_oerrors;
|
||||||
|
m_freem(m);
|
||||||
|
return EHOSTUNREACH;
|
||||||
|
}
|
||||||
|
if (dst == NULL
|
||||||
|
|| dst->sa_family != AF_INET) {
|
||||||
|
/*
|
||||||
|
* This is because we give all received packets to ipintrq
|
||||||
|
* right now.
|
||||||
|
*/
|
||||||
|
What();
|
||||||
|
m_freem(m);
|
||||||
|
++ifp->if_noproto;
|
||||||
|
return EAFNOSUPPORT;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* The a12MppSwitch is a wormhole routed MSN consisting of a number
|
||||||
|
* (usually n==1) of 14 channel crossbar switches. Each route through
|
||||||
|
* a switch requires a 128 bit address word that specifies the channel
|
||||||
|
* to emerge on. The address word is eaten by the switch and the
|
||||||
|
* rest of the packet is routed through.
|
||||||
|
*/
|
||||||
|
lladdr = LLADDR(llsa);
|
||||||
|
if (llsa->sdl_alen != 1) /* XXX */
|
||||||
|
DIE(); /* OK someday, but totally unexpected right now */
|
||||||
|
/*
|
||||||
|
* Alternatively, we could lookup the address word and output
|
||||||
|
* it with PIO when the mbuf is dequeued
|
||||||
|
*/
|
||||||
|
xbo_framesize = m->m_pkthdr.len + 8;
|
||||||
|
M_PREPEND(m, 16 * llsa->sdl_alen + 8, M_DONTWAIT);
|
||||||
|
if (m == NULL)
|
||||||
|
return ENOBUFS;
|
||||||
|
xbh = mtod(m, caddr_t);
|
||||||
|
for (i=0; i<llsa->sdl_alen; ++i) {
|
||||||
|
xbaddr = (lladdr[i] & 0xff) - 1;
|
||||||
|
if (!(0 <= xbaddr && xbaddr <= 11)) /* XXX */
|
||||||
|
DIE(); /* 12 or 13 will be OK later */
|
||||||
|
bcopy(&channel[xbaddr].lo64, xbh, 16);
|
||||||
|
xbh += 16;
|
||||||
|
}
|
||||||
|
bcopy(&xbo_framesize, xbh, 8);
|
||||||
|
s = splimp();
|
||||||
|
if (IF_QFULL(&ifp->if_snd)) {
|
||||||
|
IF_DROP(&ifp->if_snd);
|
||||||
|
++ifp->if_oerrors;
|
||||||
|
splx(s);
|
||||||
|
m_freem(m);
|
||||||
|
return ENOBUFS;
|
||||||
|
}
|
||||||
|
ifp->if_obytes += m->m_pkthdr.len;
|
||||||
|
++ifp->if_opackets;
|
||||||
|
IF_ENQUEUE(&ifp->if_snd, m);
|
||||||
|
if ((ifp->if_flags & IFF_OACTIVE) == 0)
|
||||||
|
xb_start(ifp);
|
||||||
|
splx(s);
|
||||||
|
if (m->m_flags & M_MCAST)
|
||||||
|
ifp->if_omcasts++;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
xb_start(ifp)
|
||||||
|
struct ifnet *ifp;
|
||||||
|
{
|
||||||
|
struct mbuf *m;
|
||||||
|
|
||||||
|
if ((xbi.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
|
||||||
|
return;
|
||||||
|
for (;;) {
|
||||||
|
IF_DEQUEUE(&xbi.if_snd, m);
|
||||||
|
if (m == 0)
|
||||||
|
return;
|
||||||
|
/*
|
||||||
|
* XXX The variable-length switch address words cause problems
|
||||||
|
* for bpf, for now, leave it out. XXX It's not too hard to
|
||||||
|
* fix, though, as there are lots of techniques that will
|
||||||
|
* identify the number of switch address words.
|
||||||
|
*/
|
||||||
|
if (!xb_put(m)) {
|
||||||
|
xbi.if_flags |= IFF_OACTIVE;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
xb_put(m)
|
||||||
|
struct mbuf *m;
|
||||||
|
{
|
||||||
|
struct mbuf *n;
|
||||||
|
int len;
|
||||||
|
|
||||||
|
if (XB_DEBUG && (alpha_pal_rdps() & 7) < 3)
|
||||||
|
DIE(); /* this "cannot happen", of course */
|
||||||
|
for (; m; m = n) {
|
||||||
|
len = m->m_len;
|
||||||
|
if (len == 0 || xb_put_blk(m))
|
||||||
|
MFREE(m, n);
|
||||||
|
else return 0;
|
||||||
|
}
|
||||||
|
xb_put_blk(NULL);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Write a single mbuf to the transmit channel fifo. We can only write 128-bit
|
||||||
|
* words. Right now, we pad at the end. It is possible to pad at the
|
||||||
|
* beginning, especially since lots of games can be played at the receiver
|
||||||
|
* with the mbuf data pointer. Padding at the beginning requires a pad-count
|
||||||
|
* field in a header, but it means you can always DMA the data, regardless of
|
||||||
|
* alignment. Of course, we don't DMA at all, right now.
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
xb_put_blk(m)
|
||||||
|
struct mbuf *m;
|
||||||
|
{
|
||||||
|
static long leftover[2]; /* 0-15 bytes from last xb_put_blk() */
|
||||||
|
static int leftover_len; /* non-aligned amount from last call */
|
||||||
|
long xfertmp[8]; /* aligned switch word buffer */
|
||||||
|
int frag_len, /* fifo stream unit */
|
||||||
|
fifo_len, /* space left in fifo */
|
||||||
|
fillin, /* amount needed to complete a switch word */
|
||||||
|
full, /* remember to restart on fifo full */
|
||||||
|
len; /* amount of mbuf left to do */
|
||||||
|
caddr_t blk; /* location we are at in mbuf */
|
||||||
|
static int fifo_free; /* current # of switch words free in fifo */
|
||||||
|
|
||||||
|
#define XFERADJ() ((caddr_t)xfertmp+leftover_len)
|
||||||
|
|
||||||
|
/* There is always room for the close word */
|
||||||
|
|
||||||
|
if (m == NULL) {
|
||||||
|
if (leftover_len)
|
||||||
|
leftover_len = 0;
|
||||||
|
else leftover[0] = leftover[1] = 0;
|
||||||
|
xb_mcrp_write(leftover, 1, 1);
|
||||||
|
--fifo_free;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
restart:
|
||||||
|
if (fifo_free < 2) {
|
||||||
|
if (!xb_fifo_empty()) {
|
||||||
|
if(!set_interrupt_on_fifo_empty()) {
|
||||||
|
/* still empty */
|
||||||
|
xbi.if_flags |= IFF_OACTIVE;
|
||||||
|
IF_PREPEND(&xbi.if_snd, m);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
fifo_free = FIFO_WORDCOUNT;
|
||||||
|
}
|
||||||
|
len = m->m_len;
|
||||||
|
if (len == 0)
|
||||||
|
return 1; /* clean finish, nothing left over */
|
||||||
|
blk = mtod(m, caddr_t);
|
||||||
|
if (leftover_len) {
|
||||||
|
/* See function intro comment regarding padding */
|
||||||
|
if (leftover_len + len < sizeof leftover) {
|
||||||
|
/* Heh, not even enough to write out */
|
||||||
|
bcopy(blk, XFERADJ(), len);
|
||||||
|
leftover_len += len;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
xfertmp[0] = leftover[0];
|
||||||
|
xfertmp[1] = leftover[1];
|
||||||
|
fillin = sizeof leftover - leftover_len;
|
||||||
|
bcopy(blk, XFERADJ(), fillin);
|
||||||
|
blk += fillin;
|
||||||
|
len -= fillin;
|
||||||
|
xb_mcrp_write(xfertmp, 1, 0);
|
||||||
|
leftover_len = 0;
|
||||||
|
--fifo_free;
|
||||||
|
}
|
||||||
|
/* fifo_free is known to be >= 1 at this point */
|
||||||
|
while (len >= 16) {
|
||||||
|
full = 0;
|
||||||
|
frag_len = sizeof xfertmp;
|
||||||
|
if (frag_len > len)
|
||||||
|
frag_len = len;
|
||||||
|
fifo_len = fifo_free * 16;
|
||||||
|
if (frag_len > fifo_len) {
|
||||||
|
frag_len = fifo_len;
|
||||||
|
full = 1;
|
||||||
|
}
|
||||||
|
frag_len &= ~0xf;
|
||||||
|
bcopy(blk, xfertmp, frag_len);
|
||||||
|
frag_len >>= 4; /* Round down to switch word size */
|
||||||
|
xb_mcrp_write(xfertmp, frag_len, 0);
|
||||||
|
fifo_free -= frag_len;
|
||||||
|
frag_len <<= 4;
|
||||||
|
len -= frag_len;
|
||||||
|
blk += frag_len;
|
||||||
|
if (full) {
|
||||||
|
m_adj(m, blk - mtod(m, caddr_t));
|
||||||
|
goto restart;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
bcopy(blk, leftover, len);
|
||||||
|
leftover_len = len;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static long
|
||||||
|
set_interrupt_on_fifo_empty(void)
|
||||||
|
{
|
||||||
|
REGVAL(A12_OMR) |= A12_OMR_OMF_ENABLE;
|
||||||
|
alpha_mb();
|
||||||
|
if(xb_fifo_empty()) {
|
||||||
|
REGVAL(A12_OMR) &= ~A12_OMR_OMF_ENABLE;
|
||||||
|
alpha_mb();
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
/*
|
||||||
|
* Write an aligned block of switch words to the FIFO
|
||||||
|
*/
|
||||||
|
Static void
|
||||||
|
xb_mcrp_write(d, n, islast)
|
||||||
|
long *d;
|
||||||
|
{
|
||||||
|
volatile long *xb_fifo = islast ? REGADDR(A12_FIFO_LWE)
|
||||||
|
: REGADDR(A12_FIFO);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (XB_DEBUG && islast && n != 1)
|
||||||
|
DIE();
|
||||||
|
n <<= 1;
|
||||||
|
for (i = 0; i < n; i += 2) {
|
||||||
|
xb_onefree();
|
||||||
|
xb_fifo[0] = d[i];
|
||||||
|
xb_fifo[1] = d[i+1];
|
||||||
|
alpha_wmb();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
const
|
||||||
|
int32_t xbar_bc_addr = XBAR_BROADCAST;
|
||||||
|
*/
|
||||||
|
|
||||||
|
static void
|
||||||
|
a12_xbar_setup()
|
||||||
|
{
|
||||||
|
xbi.if_softc = &xb_softc;
|
||||||
|
xbi.if_start = xb_start;
|
||||||
|
xbi.if_ioctl = xb_ioctl;
|
||||||
|
xbi.if_flags = IFF_BROADCAST /* ha ha */
|
||||||
|
| IFF_SIMPLEX;
|
||||||
|
|
||||||
|
if_attach(&xbi);
|
||||||
|
|
||||||
|
xbi.if_type = IFT_A12MPPSWITCH;
|
||||||
|
xbi.if_addrlen = 32;
|
||||||
|
xbi.if_hdrlen = 32;
|
||||||
|
xbi.if_mtu = XB_DEFAULT_MTU();
|
||||||
|
xbi.if_output = xb_output;
|
||||||
|
/* xbi.if_broadcastaddr = (u_int8_t)&xbar_bc_addr; */
|
||||||
|
|
||||||
|
#if NBPFILTER > 0
|
||||||
|
bpfattach(&xbi.if_bpf, &xbi, DLT_NULL, 0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,82 @@
|
||||||
|
/* $NetBSD: if_xb.h,v 1.1 1998/09/23 21:14:58 ross Exp $ */
|
||||||
|
|
||||||
|
/* [Notice revision 2.2]
|
||||||
|
* Copyright (c) 1997, 1998 Avalon Computer Systems, Inc.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Author: Ross Harvey
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright and
|
||||||
|
* author notice, this list of conditions, and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
|
||||||
|
* its contributors may be used to endorse or promote products derived
|
||||||
|
* from this software without specific prior written permission.
|
||||||
|
* 4. This copyright will be assigned to The NetBSD Foundation on
|
||||||
|
* 1/1/2000 unless these terms (including possibly the assignment
|
||||||
|
* date) are updated in writing by Avalon prior to the latest specified
|
||||||
|
* assignment date.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
|
||||||
|
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||||
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AVALON OR THE CONTRIBUTORS
|
||||||
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ALPHA_PCI_A12CVAR_H_
|
||||||
|
#define _ALPHA_PCI_A12CVAR_H_
|
||||||
|
|
||||||
|
#define A12CVAR() /* generate ctags(1) key */
|
||||||
|
|
||||||
|
#include <dev/isa/isavar.h>
|
||||||
|
#include <dev/pci/pcivar.h>
|
||||||
|
#include <alpha/pci/pci_sgmap_pte64.h>
|
||||||
|
/*
|
||||||
|
* A12 Core Logic -a12c- configuration.
|
||||||
|
*/
|
||||||
|
struct a12c_config {
|
||||||
|
int ac_initted;
|
||||||
|
|
||||||
|
bus_space_tag_t ac_iot, ac_memt;
|
||||||
|
struct alpha_pci_chipset ac_pc;
|
||||||
|
|
||||||
|
struct alpha_bus_dma_tag ac_dmat_direct;
|
||||||
|
struct alpha_bus_dma_tag ac_dmat_sgmap;
|
||||||
|
|
||||||
|
struct alpha_sgmap ac_sgmap;
|
||||||
|
|
||||||
|
u_int32_t ac_hae_mem;
|
||||||
|
u_int32_t ac_hae_io;
|
||||||
|
|
||||||
|
struct extent *ac_io_ex, *ac_d_mem_ex, *ac_s_mem_ex;
|
||||||
|
int ac_mallocsafe;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct a12c_softc {
|
||||||
|
struct device sc_dev;
|
||||||
|
|
||||||
|
struct a12c_config *sc_ccp;
|
||||||
|
};
|
||||||
|
|
||||||
|
void a12c_init __P((struct a12c_config *, int));
|
||||||
|
void a12c_pci_init __P((pci_chipset_tag_t, void *));
|
||||||
|
void a12c_dma_init __P((struct a12c_config *));
|
||||||
|
|
||||||
|
bus_space_tag_t a12c_bus_io_init __P((void *));
|
||||||
|
bus_space_tag_t a12c_bus_mem_init __P((void *));
|
||||||
|
|
||||||
|
void a12_xbar_intr __P((void));
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue