Setup irq correctly (PR#1179)
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brezak
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0bdd4aa7c2
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dd3d2e28ed
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@ -1,4 +1,4 @@
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/* $NetBSD: wss.c,v 1.5 1995/05/08 22:02:32 brezak Exp $ */
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/* $NetBSD: wss.c,v 1.6 1995/07/07 02:15:12 brezak Exp $ */
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/*
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* Copyright (c) 1994 John Brezak
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@ -52,10 +52,9 @@
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmavar.h>
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#include <i386/isa/icu.h> /* XXX BROKEN; WHY? */
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#include <dev/ic/ad1848reg.h>
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#include <dev/isa/ad1848var.h>
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#include <dev/isa/ad1848reg.h>
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#include <dev/isa/wssreg.h>
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/*
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@ -77,8 +76,7 @@
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#define WSS_RECORD_CLASS 10
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#define WSS_MONITOR_CLASS 11
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#define DEBUG /*XXX*/
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#ifdef DEBUG
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#ifdef AUDIO_DEBUG
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#define DPRINTF(x) if (wssdebug) printf x
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int wssdebug = 0;
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#else
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@ -91,7 +89,6 @@ struct wss_softc {
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void *sc_ih; /* interrupt vectoring */
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struct ad1848_softc sc_ad1848;
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#define wss_iobase sc_ad1848.sc_iobase
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#define wss_irq sc_ad1848.sc_irq
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#define wss_drq sc_ad1848.sc_drq
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@ -186,19 +183,27 @@ wssprobe(parent, self, aux)
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-1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
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};
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static u_char dma_bits[4] = {1, 2, 0, 3};
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char bits;
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if (!WSS_BASE_VALID(ia->ia_iobase)) {
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printf("wss: configured iobase %d invalid\n", ia->ia_iobase);
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printf("wss: configured iobase %x invalid\n", ia->ia_iobase);
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return 0;
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}
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sc->wss_iobase = iobase;
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sc->sc_ad1848.sc_iobase = iobase;
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/* Is there an ad1848 chip at the WSS iobase ? */
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if (ad1848_probe(&sc->sc_ad1848) == 0)
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return 0;
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ia->ia_iosize = WSS_NPORT;
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/* Setup WSS interrupt and DMA */
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if (!WSS_DRQ_VALID(ia->ia_drq)) {
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printf("wss: configured dma chan %d invalid\n", ia->ia_drq);
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return 0;
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}
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sc->wss_drq = ia->ia_drq;
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#ifdef NEWCONFIG
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/*
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* If the IRQ wasn't compiled in, auto-detect it.
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@ -206,27 +211,21 @@ wssprobe(parent, self, aux)
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if (ia->ia_irq == IRQUNK) {
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ia->ia_irq = isa_discoverintr(ad1848_forceintr, &sc->sc_ad1848);
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if (!WSS_IRQ_VALID(ia->ia_irq)) {
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printf("wss: couldn't auto-detect interrupt");
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printf("wss: couldn't auto-detect interrupt\n");
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return 0;
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}
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}
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else
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#endif
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ia->ia_iosize = WSS_NPORT;
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/* Setup WSS interrupt and DMA */
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if ((bits = interrupt_bits[sc->wss_irq]) == -1) {
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printf("wss: invalid interrupt configuration (irq=%d)\n", sc->wss_irq);
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return 0;
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if (!WSS_IRQ_VALID(ia->ia_irq)) {
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printf("wss: configured interrupt %d invalid\n", ia->ia_irq);
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return 0;
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}
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#if 0
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/* XXX Dual-DMA */
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outb(sc->wss_iobase+WSS_CONFIG, (bits | 0x40));
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if ((inb(sc->wss_iobase+WSS_STATUS) & 0x40) == 0)
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printf("wss: IRQ?\n");
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#endif
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outb(sc->wss_iobase+WSS_CONFIG, (bits | dma_bits[sc->wss_drq]));
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sc->wss_irq = ia->ia_irq;
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outb(iobase+WSS_CONFIG,
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(interrupt_bits[ia->ia_irq] | dma_bits[ia->ia_drq]));
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return 1;
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}
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@ -243,25 +242,25 @@ wssattach(parent, self, aux)
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register struct wss_softc *sc = (struct wss_softc *)self;
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struct isa_attach_args *ia = (struct isa_attach_args *)aux;
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register u_short iobase = ia->ia_iobase;
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sc->wss_iobase = iobase;
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sc->wss_drq = ia->ia_drq;
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int err;
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sc->sc_ad1848.sc_recdrq = ia->ia_drq;
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#ifdef NEWCONFIG
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isa_establish(&sc->sc_id, &sc->sc_dev);
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#endif
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sc->sc_ih = isa_intr_establish(ia->ia_irq, ISA_IST_EDGE, ISA_IPL_BIO,
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ad1848_intr, &sc->sc_ad1848);
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sc->sc_ih = isa_intr_establish(ia->ia_irq, ISA_IST_EDGE, ISA_IPL_AUDIO,
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ad1848_intr, &sc->sc_ad1848);
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ad1848_attach(&sc->sc_ad1848);
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printf(" (vers %d)", inb(sc->wss_iobase+WSS_STATUS) & 0x1f);
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printf(" (vers %d)", inb(iobase+WSS_STATUS) & WSS_VERSMASK);
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printf("\n");
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sc->sc_ad1848.parent = sc;
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if (audio_hardware_attach(&wss_hw_if, &sc->sc_ad1848) != 0)
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printf("wss: could not attach to audio pseudo-device driver\n");
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if ((err = audio_hardware_attach(&wss_hw_if, &sc->sc_ad1848)) != 0)
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printf("wss: could not attach to audio pseudo-device driver (%d)\n", err);
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}
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static int
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@ -1,4 +1,4 @@
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/* $NetBSD: wssreg.h,v 1.2 1995/05/08 22:02:35 brezak Exp $ */
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/* $NetBSD: wssreg.h,v 1.3 1995/07/07 02:15:15 brezak Exp $ */
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/*
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* Copyright (c) 1991-1993 Regents of the University of California.
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@ -42,20 +42,23 @@
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/*
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* Macros to detect valid hardware configuration data.
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*/
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#define WSS_IRQ_VALID(mask) ((mask) & 0x00ac) /* IRQ 2,3,5,7 */
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#define WSS_IRQ_VALID(irq) ((irq) == 7 || (irq) == 9 || \
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(irq) == 10 || (irq) == 11)
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#define WSS_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3)
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#define WSS_BASE_VALID(base) ((base) == 0x0530 || \
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(base) == 0x0604 || \
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(base) == 0x0e80 || \
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(base) == 0x0f40)
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/* Default WSS base */
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/* WSS registers */
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#define WSS_BASE_ADDRESS 0x0530
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/* WSS registers */
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#define WSS_CONFIG 0x00
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#define WSS_STATUS 0x03
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#define WSS_CONFIG 0x00 /* write only */
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#define WSS_STATUS 0x03 /* read only */
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#define WSS_VERS 0x04
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/* WSS status register bits */
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#define WSS_16SLOT 0x80
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#define WSS_DUALDMA 0x40
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#define WSS_IRQACTIVE 0x40
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#define WSS_VERS 0x04
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#define WSS_VERSMASK 0x3f
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