Don't need to flush the d$ for MMU bypass accesses.
This commit is contained in:
eeh
parent
2fb16bb43f
commit
dcb399fc7c
@ -1,7 +1,7 @@
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/* $NetBSD: ctlreg.h,v 1.29 2002/01/14 20:44:30 eeh Exp $ */
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/* $NetBSD: ctlreg.h,v 1.30 2002/04/24 23:54:24 eeh Exp $ */
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/*
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* Copyright (c) 1996-2001 Eduardo Horvath
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* Copyright (c) 1996-2002 Eduardo Horvath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -478,20 +478,10 @@ lduba(paddr_t loc, int asi)
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{
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register unsigned int _lduba_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" lduba [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_lduba_v), "=r" (loc):
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; "
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" lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lduba_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; "
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" lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lduba_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lduba_v);
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}
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#else
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@ -502,15 +492,13 @@ lduba(paddr_t loc, int asi)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; "
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" sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; "
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
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" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; "
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" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; "
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" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
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" membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_lduba_v), "=&r" (_pstate) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
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" or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) :
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@ -528,20 +516,10 @@ lduha(paddr_t loc, int asi)
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{
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register unsigned int _lduha_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" lduha [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v), "=r" (loc) :
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
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" wr %%g0, 0x82, %%asi" :
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"=r" (_lduha_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
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" wr %%g0, 0x82, %%asi" :
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"=r" (_lduha_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lduha_v);
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}
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#else
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@ -553,14 +531,13 @@ lduha(paddr_t loc, int asi) {
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; "
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
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" rdpr %%pstate,%1; wrpr %1,8,%%pstate; "
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" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; "
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" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
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" membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_lduha_v), "=&r" (_pstate) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
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" or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) :
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@ -578,19 +555,9 @@ lda(paddr_t loc, int asi)
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{
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register unsigned int _lda_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" lda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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}
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@ -600,20 +567,10 @@ ldswa(paddr_t loc, int asi)
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{
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register int _lda_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" ldswa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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}
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#else /* __arch64__ */
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@ -626,13 +583,11 @@ lda(paddr_t loc, int asi)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
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" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; "
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" sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; "
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" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %5; membar #Sync; "
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" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; "
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" lda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
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" or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
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@ -651,13 +606,12 @@ ldswa(paddr_t loc, int asi)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
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" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;"
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" wrpr %1,8,%%pstate; sllx %3,32,%0;"
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" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; "
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" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
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" wr %%g0, 0x82, %%asi" :
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" membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_lda_v), "=&r" (_pstate) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
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" or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
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@ -675,20 +629,10 @@ ldda(paddr_t loc, int asi)
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{
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register long long _lda_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" ldda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (loc) :
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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}
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#else
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@ -701,13 +645,11 @@ ldda(paddr_t loc, int asi)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
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" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;"
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" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; "
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" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
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" wr %%g0, 0x82, %%asi" :
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" wrpr %1,8,%%pstate; sllx %3,32,%0; or %0,%2,%0; membar #Sync;"
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" ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_lda_v), "=&r" (_pstate) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
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" or %0,%1,%0; ldda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
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@ -725,20 +667,10 @@ ldxa(paddr_t loc, int asi)
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{
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register unsigned long _lda_v;
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; "
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
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" ldxa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
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" stxa %%g0,[%1] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
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"r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; "
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" ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
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"=r" (_lda_v) :
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"r" ((unsigned long)(loc)), "r" (asi));
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return (_lda_v);
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}
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#else
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@ -750,14 +682,13 @@ ldxa(paddr_t loc, int asi)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %4,%%g0,%%asi; "
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" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; "
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" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; "
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" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
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__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; "
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" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; "
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" ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; "
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" srlx %0,32,%1; srl %0,0,%0; wr %%g0, 0x82, %%asi" :
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) :
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"r" ((unsigned long)(loc)), "r" (_loc_hi),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (asi));
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} else {
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
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" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; "
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@ -775,19 +706,10 @@ ldxa(paddr_t loc, int asi)
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static __inline__ void
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stba(paddr_t loc, int asi, u_char value)
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{
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %3,%%g0,%%asi; stba %1,[%2]%%asi;"
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" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
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" wr %%g0, 0x82, %%asi" :
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"=&r" (loc) :
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"r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (asi), "n" (ASI_DCACHE_TAG));
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} else {
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__asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; "
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" wr %%g0, 0x82, %%asi" : :
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"r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (asi));
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}
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__asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; "
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" wr %%g0, 0x82, %%asi" : :
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"r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (asi));
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}
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#else
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static __inline__ void
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@ -797,13 +719,12 @@ stba(paddr_t loc, int asi, u_char value)
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_loc_hi = (((u_int64_t)loc)>>32);
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if (PHYS_ASI(asi)) {
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;"
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" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; "
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" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
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" wr %%g0, 0x82, %%asi" :
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__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; "
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" rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; "
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" wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
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"=&r" (_loc_hi), "=&r" (_pstate) :
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"r" ((int)(value)), "r" ((unsigned long)(loc)),
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"r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG));
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"r" (_loc_hi), "r" (asi));
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} else {
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__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
|
||||
" or %2,%0,%0; stba %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) :
|
||||
@ -818,19 +739,10 @@ stba(paddr_t loc, int asi, u_char value)
|
||||
static __inline__ void
|
||||
stha(paddr_t loc, int asi, u_short value)
|
||||
{
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %3,%%g0,%%asi; stha %1,[%2]%%asi;"
|
||||
" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (loc) :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
#else
|
||||
static __inline__ void
|
||||
@ -840,14 +752,12 @@ stha(paddr_t loc, int asi, u_short value)
|
||||
|
||||
_loc_hi = (((u_int64_t)loc)>>32);
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;"
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate; "
|
||||
" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; "
|
||||
" rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; "
|
||||
" wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (_loc_hi), "r" (asi),
|
||||
"n" (ASI_DCACHE_TAG) : "memory");
|
||||
"r" (_loc_hi), "r" (asi) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
|
||||
" or %2,%0,%0; stha %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) :
|
||||
@ -863,19 +773,10 @@ stha(paddr_t loc, int asi, u_short value)
|
||||
static __inline__ void
|
||||
sta(paddr_t loc, int asi, u_int value)
|
||||
{
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %3,%%g0,%%asi; sta %1,[%2]%%asi;"
|
||||
" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (loc) :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
__asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
#else
|
||||
static __inline__ void
|
||||
@ -885,14 +786,12 @@ sta(paddr_t loc, int asi, u_int value)
|
||||
|
||||
_loc_hi = (((u_int64_t)loc)>>32);
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;"
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate; "
|
||||
" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; "
|
||||
" rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; "
|
||||
" wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) :
|
||||
"r" ((int)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (_loc_hi), "r" (asi),
|
||||
"n" (ASI_DCACHE_TAG) : "memory");
|
||||
"r" (_loc_hi), "r" (asi) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
|
||||
" or %2,%0,%0; sta %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) :
|
||||
@ -907,19 +806,10 @@ sta(paddr_t loc, int asi, u_int value)
|
||||
static __inline__ void
|
||||
stda(paddr_t loc, int asi, u_int64_t value)
|
||||
{
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %3,%%g0,%%asi; stda %1,[%2]%%asi;"
|
||||
" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (loc) :
|
||||
"r" ((long long)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((long long)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((long long)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (asi) : "memory");
|
||||
}
|
||||
#else
|
||||
static __inline__ void
|
||||
@ -929,14 +819,12 @@ stda(paddr_t loc, int asi, u_int64_t value)
|
||||
|
||||
_loc_hi = (((u_int64_t)loc)>>32);
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; "
|
||||
" or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate;"
|
||||
" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; "
|
||||
" rdpr %%pstate,%1; or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; "
|
||||
" wrpr %1,0,%%pstate; membar #Sync; wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (_loc_hi), "=&r" (_pstate) :
|
||||
"r" ((long long)(value)), "r" ((unsigned long)(loc)),
|
||||
"r" (_loc_hi), "r" (asi),
|
||||
"n" (ASI_DCACHE_TAG) : "memory");
|
||||
"r" (_loc_hi), "r" (asi) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
|
||||
" or %2,%0,%0; stda %1,[%0]%%asi; wr %%g0, 0x82, %%asi" :
|
||||
@ -952,20 +840,10 @@ stda(paddr_t loc, int asi, u_int64_t value)
|
||||
static __inline__ void
|
||||
stxa(paddr_t loc, int asi, u_int64_t value)
|
||||
{
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %3,%%g0,%%asi; stxa %1,[%2]%%asi;"
|
||||
" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (asi) :
|
||||
"r" ((unsigned long)(value)),
|
||||
"r" ((unsigned long)(loc)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((unsigned long)(value)),
|
||||
"r" ((unsigned long)(loc)), "r" (asi) : "memory");
|
||||
}
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi; "
|
||||
" wr %%g0, 0x82, %%asi" : :
|
||||
"r" ((unsigned long)(value)),
|
||||
"r" ((unsigned long)(loc)), "r" (asi) : "memory");
|
||||
}
|
||||
#else
|
||||
/* native store 64-bit int to alternate address space w/32-bit compiler*/
|
||||
@ -979,15 +857,15 @@ stxa(paddr_t loc, int asi, u_int64_t value)
|
||||
_loc_hi = (((u_int64_t)(u_long)loc)>>32);
|
||||
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; "
|
||||
" or %1,%3,%1; rdpr %%pstate,%2; or %0,%5,%0; wrpr %2,8,%%pstate; "
|
||||
" stxa %1,[%0]%%asi; wrpr %2,0,%%pstate; andn %0,0x1f,%1; "
|
||||
" membar #Sync; stxa %%g0,[%1] %8; membar #Sync; wr %%g0, 0x82, %%asi" :
|
||||
__asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; "
|
||||
" sllx %6,32,%0; or %1,%3,%1; rdpr %%pstate,%2; or %0,%5,%0; "
|
||||
" wrpr %2,8,%%pstate; stxa %1,[%0]%%asi; wrpr %2,0,%%pstate; "
|
||||
" membar #Sync; wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (_loc_hi), "=&r" (_stxa_hi),
|
||||
"=&r" ((int)(_stxa_lo)) :
|
||||
"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)),
|
||||
"r" ((unsigned long)(loc)), "r" (_loc_hi),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
"r" (asi) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; "
|
||||
" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi; wr %%g0, 0x82, %%asi" :
|
||||
@ -1005,21 +883,11 @@ stxa(paddr_t loc, int asi, u_int64_t value)
|
||||
static __inline__ u_int64_t
|
||||
casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
|
||||
{
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %4,%%g0,%%asi; casxa [%3]%%asi,%2,%1;"
|
||||
" andn %3,0x1f,%0; membar #Sync; stxa %%g0,[%0] %5; membar #Sync; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"=&r" (loc), "+r" (value) :
|
||||
"r" ((unsigned long)(oldvalue)),
|
||||
"r" ((unsigned long)(loc)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
|
||||
} else {
|
||||
__asm __volatile("wr %3,%%g0,%%asi; casxa [%1]%%asi,%2,%0; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"+r" (value) :
|
||||
"r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) :
|
||||
"memory");
|
||||
}
|
||||
__asm __volatile("wr %3,%%g0,%%asi; casxa [%1]%%asi,%2,%0; "
|
||||
" wr %%g0, 0x82, %%asi" :
|
||||
"+r" (value) :
|
||||
"r" ((unsigned long)(loc)), "r" (oldvalue), "r" (asi) :
|
||||
"memory");
|
||||
return (value);
|
||||
}
|
||||
#else
|
||||
@ -1039,16 +907,16 @@ casxa(paddr_t loc, int asi, u_int64_t value, u_int64_t oldvalue)
|
||||
* gcc cannot handle this since it thinks it has >10 asm operands.
|
||||
*/
|
||||
if (PHYS_ASI(asi)) {
|
||||
__asm __volatile("wr %6,%%g0,%%asi; sllx %1,32,%1; sllx %0,32,%0; "
|
||||
" sllx %3,32,%3; or %1,%2,%1; rdpr %%pstate,%2; or %0,%4,%0; or %3,%5,%3; "
|
||||
__asm __volatile("wr %6,%%g0,%%asi; sllx %1,32,%1; rdpr %%pstate,%2; "
|
||||
" sllx %0,32,%0; or %1,%2,%1; sllx %3,32,%3; or %0,%4,%0; or %3,%5,%3; "
|
||||
" wrpr %2,8,%%pstate; casxa [%0]%%asi,%3,%1; wrpr %2,0,%%pstate; "
|
||||
" andn %0,0x1f,%3; membar #Sync; stxa %%g0,[%3] %7; membar #Sync; "
|
||||
" andn %0,0x1f,%3; membar #Sync; "
|
||||
" sll %1,0,%2; srax %1,32,%1; wr %%g0, 0x82, %%asi " :
|
||||
"+r" (_loc_hi), "+r" (_casxa_hi),
|
||||
"+r" (_casxa_lo), "+r" (_oval_hi) :
|
||||
"r" ((unsigned long)(loc)),
|
||||
"r" ((unsigned int)(oldvalue)),
|
||||
"r" (asi), "n" (ASI_DCACHE_TAG));
|
||||
"r" (asi));
|
||||
} else {
|
||||
__asm __volatile("wr %7,%%g0,%%asi; sllx %1,32,%1; sllx %5,32,%0; "
|
||||
" or %1,%2,%1; sllx %3,32,%2; or %0,%4,%0; or %2,%4,%2; "
|
||||
|
||||
Loading…
Reference in New Issue
Block a user