Use the common MII bit-bang module.
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thorpej
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b5fd53184a
commit
dc5a586c1c
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@ -1,4 +1,4 @@
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/* $NetBSD: elink3.c,v 1.66 1999/11/12 18:14:17 thorpej Exp $ */
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/* $NetBSD: elink3.c,v 1.67 1999/11/19 18:17:14 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -116,6 +116,7 @@
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/mii_bitbang.h>
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#include <dev/ic/elink3var.h>
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#include <dev/ic/elink3reg.h>
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@ -227,12 +228,6 @@ void ep_statchg __P((struct device *));
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void ep_tick __P((void *));
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void ep_mii_setbit __P((struct ep_softc *, u_int16_t));
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void ep_mii_clrbit __P((struct ep_softc *, u_int16_t));
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u_int16_t ep_mii_readbit __P((struct ep_softc *, u_int16_t));
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void ep_mii_sync __P((struct ep_softc *));
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void ep_mii_sendbits __P((struct ep_softc *, u_int32_t, int));
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static int epbusyeeprom __P((struct ep_softc *));
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u_int16_t ep_read_eeprom __P((struct ep_softc *, u_int16_t));
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static inline void ep_reset_cmd __P((struct ep_softc *sc,
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@ -241,6 +236,24 @@ static inline void ep_finish_reset __P((bus_space_tag_t, bus_space_handle_t));
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static inline void ep_discard_rxtop __P((bus_space_tag_t, bus_space_handle_t));
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static __inline int ep_w1_reg __P((struct ep_softc *, int));
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/*
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* MII bit-bang glue.
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*/
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u_int32_t ep_mii_bitbang_read __P((struct device *));
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void ep_mii_bitbang_write __P((struct device *, u_int32_t));
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const struct mii_bitbang_ops ep_mii_bitbang_ops = {
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ep_mii_bitbang_read,
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ep_mii_bitbang_write,
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{
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PHYSMGMT_DATA, /* MII_BIT_MDO */
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PHYSMGMT_DATA, /* MII_BIT_MDI */
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PHYSMGMT_CLK, /* MII_BIT_MDC */
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PHYSMGMT_DIR, /* MII_BIT_DIR_HOST_PHY */
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0, /* MII_BIT_DIR_PHY_HOST */
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}
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};
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/*
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* Some chips (3c515 [Corkscrew] and 3c574 [RoadRunner]) have
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* Window 1 registers offset!
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@ -2119,77 +2132,27 @@ ep_activate(self, act)
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return (rv);
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}
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void
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ep_mii_setbit(sc, bit)
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struct ep_softc *sc;
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u_int16_t bit;
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u_int32_t
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ep_mii_bitbang_read(self)
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struct device *self;
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{
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u_int16_t val;
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struct ep_softc *sc = (void *) self;
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/* We assume we're already in Window 4 */
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val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT,
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val | bit);
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/* We're already in Window 4. */
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return (bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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ELINK_W4_BOOM_PHYSMGMT));
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}
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void
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ep_mii_clrbit(sc, bit)
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struct ep_softc *sc;
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u_int16_t bit;
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ep_mii_bitbang_write(self, val)
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struct device *self;
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u_int32_t val;
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{
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u_int16_t val;
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struct ep_softc *sc = (void *) self;
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/* We assume we're already in Window 4 */
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val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT,
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val & ~bit);
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}
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u_int16_t
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ep_mii_readbit(sc, bit)
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struct ep_softc *sc;
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u_int16_t bit;
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{
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/* We assume we're already in Window 4 */
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return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT) &
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bit);
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}
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void
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ep_mii_sync(sc)
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struct ep_softc *sc;
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{
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int i;
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/* We assume we're already in Window 4 */
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ep_mii_clrbit(sc, PHYSMGMT_DIR);
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for (i = 0; i < 32; i++) {
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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}
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}
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void
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ep_mii_sendbits(sc, data, nbits)
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struct ep_softc *sc;
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u_int32_t data;
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int nbits;
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{
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int i;
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/* We assume we're already in Window 4 */
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ep_mii_setbit(sc, PHYSMGMT_DIR);
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for (i = 1 << (nbits - 1); i; i = i >> 1) {
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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ep_mii_readbit(sc, PHYSMGMT_CLK);
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if (data & i)
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ep_mii_setbit(sc, PHYSMGMT_DATA);
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else
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ep_mii_clrbit(sc, PHYSMGMT_DATA);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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ep_mii_readbit(sc, PHYSMGMT_CLK);
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}
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/* We're already in Window 4. */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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ELINK_W4_BOOM_PHYSMGMT, val);
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}
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int
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@ -2197,45 +2160,16 @@ ep_mii_readreg(self, phy, reg)
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struct device *self;
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int phy, reg;
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{
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struct ep_softc *sc = (struct ep_softc *)self;
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int val = 0, i, err;
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/*
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* Read the PHY register by manually driving the MII control lines.
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*/
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struct ep_softc *sc = (void *) self;
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int val;
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GO_WINDOW(4);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_BOOM_PHYSMGMT, 0);
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val = mii_bitbang_readreg(self, &ep_mii_bitbang_ops, phy, reg);
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ep_mii_sync(sc);
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ep_mii_sendbits(sc, MII_COMMAND_START, 2);
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ep_mii_sendbits(sc, MII_COMMAND_READ, 2);
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ep_mii_sendbits(sc, phy, 5);
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ep_mii_sendbits(sc, reg, 5);
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GO_WINDOW(1);
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ep_mii_clrbit(sc, PHYSMGMT_DIR);
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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err = ep_mii_readbit(sc, PHYSMGMT_DATA);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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/* Even if an error occurs, must still clock out the cycle. */
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for (i = 0; i < 16; i++) {
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val <<= 1;
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA))
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val |= 1;
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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}
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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GO_WINDOW(1); /* back to operating window */
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return (err ? 0 : val);
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return (val);
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}
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void
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@ -2243,26 +2177,13 @@ ep_mii_writereg(self, phy, reg, val)
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struct device *self;
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int phy, reg, val;
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{
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struct ep_softc *sc = (struct ep_softc *)self;
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/*
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* Write the PHY register by manually driving the MII control lines.
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*/
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struct ep_softc *sc = (void *) self;
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GO_WINDOW(4);
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ep_mii_sync(sc);
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ep_mii_sendbits(sc, MII_COMMAND_START, 2);
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ep_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
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ep_mii_sendbits(sc, phy, 5);
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ep_mii_sendbits(sc, reg, 5);
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ep_mii_sendbits(sc, MII_COMMAND_ACK, 2);
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ep_mii_sendbits(sc, val, 16);
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mii_bitbang_writereg(self, &ep_mii_bitbang_ops, phy, reg, val);
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ep_mii_clrbit(sc, PHYSMGMT_CLK);
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ep_mii_setbit(sc, PHYSMGMT_CLK);
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GO_WINDOW(1); /* back to operating window */
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GO_WINDOW(1);
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}
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void
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