sun4i_spi: spi(4) driver for Allwinner A10/A20 platform
This commit is contained in:
tnn
parent
1dc95d4f1e
commit
dbb0007161
@ -1,4 +1,4 @@
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# $NetBSD: files.sunxi,v 1.65 2019/06/14 21:26:36 tnn Exp $
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# $NetBSD: files.sunxi,v 1.66 2019/08/03 13:28:42 tnn Exp $
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#
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# Configuration info for Allwinner sunxi family SoCs
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#
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@ -306,7 +306,10 @@ device sunxinand: nandbus
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attach sunxinand at fdt with sunxi_nand
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file arch/arm/sunxi/sunxi_nand.c sunxi_nand
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# SPI Controller (sun6i-compatible)
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# SPI Controller
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device sun4ispi: spibus
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attach sun4ispi at fdt with sun4i_spi
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file arch/arm/sunxi/sun4i_spi.c sun4i_spi
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device sun6ispi: spibus
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attach sun6ispi at fdt with sun6i_spi
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file arch/arm/sunxi/sun6i_spi.c sun6i_spi
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417
sys/arch/arm/sunxi/sun4i_spi.c
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417
sys/arch/arm/sunxi/sun4i_spi.c
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@ -0,0 +1,417 @@
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/* $NetBSD: sun4i_spi.c,v 1.1 2019/08/03 13:28:42 tnn Exp $ */
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/*
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* Copyright (c) 2019 Tobias Nygren
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* Copyright (c) 2018 Jonathan A. Kollasch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sun4i_spi.c,v 1.1 2019/08/03 13:28:42 tnn Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <sys/kernel.h>
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#include <sys/bitops.h>
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#include <dev/spi/spivar.h>
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#include <arm/sunxi/sun4i_spireg.h>
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#include <dev/fdt/fdtvar.h>
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static const char * const compatible[] = {
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"allwinner,sun4i-a10-spi",
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NULL
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};
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struct sun4ispi_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void *sc_intrh;
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struct spi_controller sc_spi;
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SIMPLEQ_HEAD(,spi_transfer) sc_q;
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struct spi_transfer *sc_transfer;
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struct spi_chunk *sc_rchunk, *sc_wchunk;
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uint32_t sc_CTL;
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u_int sc_modclkrate;
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volatile bool sc_running;
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};
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#define SPIREG_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define SPIREG_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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static int sun4ispi_match(device_t, cfdata_t, void *);
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static void sun4ispi_attach(device_t, device_t, void *);
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static int sun4ispi_configure(void *, int, int, int);
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static int sun4ispi_transfer(void *, struct spi_transfer *);
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static void sun4ispi_txfifo_fill(struct sun4ispi_softc * const, size_t);
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static void sun4ispi_rxfifo_drain(struct sun4ispi_softc * const, size_t);
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static void sun4ispi_rxtx(struct sun4ispi_softc *);
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static void sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const);
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static void sun4ispi_start(struct sun4ispi_softc * const);
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static int sun4ispi_intr(void *);
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CFATTACH_DECL_NEW(sun4i_spi, sizeof(struct sun4ispi_softc),
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sun4ispi_match, sun4ispi_attach, NULL, NULL);
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static int
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sun4ispi_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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sun4ispi_attach(device_t parent, device_t self, void *aux)
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{
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struct sun4ispi_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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struct clk *clk, *modclk;
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char intrstr[128];
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struct spibus_attach_args sba;
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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SIMPLEQ_INIT(&sc->sc_q);
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if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL
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|| clk_enable(clk) != 0) {
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aprint_error(": couldn't enable clock\n");
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return;
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}
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if ((modclk = fdtbus_clock_get(phandle, "mod")) == NULL
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|| clk_set_rate(modclk, clk_get_rate(clk)) != 0
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|| clk_enable(modclk) != 0) {
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aprint_error(": couldn't enable module clock\n");
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return;
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}
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sc->sc_modclkrate = clk_get_rate(modclk);
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0
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|| bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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SPIREG_WRITE(sc, SPI_CTL, SPI_CTL_SSPOL | SPI_CTL_RF_RST
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| SPI_CTL_TF_RST | SPI_CTL_MODE);
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SPIREG_WRITE(sc, SPI_DMACTL, 0);
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SPIREG_WRITE(sc, SPI_WAIT, 0);
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SPIREG_WRITE(sc, SPI_INTCTL, 0);
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SPIREG_WRITE(sc, SPI_INT_STA, ~0);
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if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
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aprint_error(": failed to decode interrupt\n");
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return;
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}
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sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, sun4ispi_intr, sc);
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if (sc->sc_intrh == NULL) {
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aprint_error("unable to establish interrupt\n");
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return;
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}
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aprint_naive("\n");
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aprint_normal(": SPI\n");
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aprint_normal_dev(self, "interrupting on %s\n", intrstr);
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sc->sc_spi.sct_cookie = sc;
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sc->sc_spi.sct_configure = sun4ispi_configure;
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sc->sc_spi.sct_transfer = sun4ispi_transfer;
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(void) of_getprop_uint32(phandle, "num-cs", &sc->sc_spi.sct_nslaves);
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sba.sba_controller = &sc->sc_spi;
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(void) config_found_ia(self, "spibus", &sba, spibus_print);
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}
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static int
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sun4ispi_configure(void *cookie, int slave, int mode, int speed)
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{
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struct sun4ispi_softc * const sc = cookie;
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uint32_t ctl, cctl;
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uint32_t minfreq, maxfreq;
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minfreq = sc->sc_modclkrate >> 16;
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maxfreq = sc->sc_modclkrate >> 1;
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if (speed <= 0 || speed < minfreq || speed > maxfreq)
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return EINVAL;
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if (slave >= sc->sc_spi.sct_nslaves)
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return EINVAL;
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ctl = SPI_CTL_SDM | SPI_CTL_TP_EN | SPI_CTL_SSPOL | SPI_CTL_MODE | SPI_CTL_EN;
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switch (mode) {
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case SPI_MODE_0:
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ctl |= 0;
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break;
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case SPI_MODE_1:
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ctl |= SPI_CTL_PHA;
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break;
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case SPI_MODE_2:
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ctl |= SPI_CTL_POL;
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break;
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case SPI_MODE_3:
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ctl |= SPI_CTL_PHA | SPI_CTL_POL;
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break;
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default:
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return EINVAL;
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}
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if (speed < sc->sc_modclkrate / 512) {
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for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) {
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if ((sc->sc_modclkrate / (1 << cctl)) <= speed)
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goto cdr1_found;
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}
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return EINVAL;
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cdr1_found:
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cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1);
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} else {
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cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1;
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cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2);
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}
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device_printf(sc->sc_dev, "ctl 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n",
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ctl, cctl, sc->sc_modclkrate,
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(cctl & SPI_CCTL_DRS)
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? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1)))
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: (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1))
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);
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sc->sc_CTL = ctl;
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SPIREG_WRITE(sc, SPI_CTL, (ctl | SPI_CTL_RF_RST | SPI_CTL_TF_RST) & ~SPI_CTL_EN);
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SPIREG_WRITE(sc, SPI_CCTL, cctl);
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SPIREG_WRITE(sc, SPI_CTL, ctl);
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return 0;
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}
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static int
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sun4ispi_transfer(void *cookie, struct spi_transfer *st)
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{
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struct sun4ispi_softc * const sc = cookie;
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int s;
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s = splbio();
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spi_transq_enqueue(&sc->sc_q, st);
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if (sc->sc_running == false) {
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sun4ispi_start(sc);
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}
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splx(s);
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return 0;
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}
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static void
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sun4ispi_txfifo_fill(struct sun4ispi_softc * const sc, size_t maxlen)
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{
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struct spi_chunk *chunk = sc->sc_wchunk;
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size_t len;
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uint8_t b;
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if (chunk == NULL)
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return;
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len = MIN(maxlen, chunk->chunk_wresid);
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chunk->chunk_wresid -= len;
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while (len--) {
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if (chunk->chunk_wptr) {
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b = *chunk->chunk_wptr++;
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} else {
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b = 0;
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}
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bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDATA, b);
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}
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if (sc->sc_wchunk->chunk_wresid == 0) {
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sc->sc_wchunk = sc->sc_wchunk->chunk_next;
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}
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}
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static void
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sun4ispi_rxfifo_drain(struct sun4ispi_softc * const sc, size_t maxlen)
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{
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struct spi_chunk *chunk = sc->sc_rchunk;
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size_t len;
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uint8_t b;
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if (chunk == NULL)
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return;
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len = MIN(maxlen, chunk->chunk_rresid);
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chunk->chunk_rresid -= len;
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while (len--) {
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b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDATA);
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if (chunk->chunk_rptr) {
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*chunk->chunk_rptr++ = b;
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}
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}
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if (sc->sc_rchunk->chunk_rresid == 0) {
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sc->sc_rchunk = sc->sc_rchunk->chunk_next;
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}
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}
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static void
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sun4ispi_rxtx(struct sun4ispi_softc * const sc)
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{
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bool again;
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size_t rxavail, txavail;
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uint32_t fsr;
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/* service both FIFOs until no more progress can be made */
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again = true;
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while (again) {
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again = false;
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fsr = SPIREG_READ(sc, SPI_FIFO_STA);
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rxavail = __SHIFTOUT(fsr, SPI_FIFO_STA_RF_CNT);
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txavail = 64 - __SHIFTOUT(fsr, SPI_FIFO_STA_TF_CNT);
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if (rxavail > 0) {
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KASSERT(sc->sc_rchunk != NULL);
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sun4ispi_rxfifo_drain(sc, rxavail);
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again = true;
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}
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if (txavail > 0 && sc->sc_wchunk != NULL) {
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sun4ispi_txfifo_fill(sc, txavail);
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again = true;
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}
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}
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}
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static void
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sun4ispi_set_interrupt_mask(struct sun4ispi_softc * const sc)
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{
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uint32_t intctl;
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intctl = SPI_INTCTL_TX_INT_EN;
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intctl |= SPI_INTCTL_RF_OF_INT_EN;
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intctl |= SPI_INTCTL_TF_UR_INT_EN;
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if (sc->sc_rchunk) {
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if (sc->sc_rchunk->chunk_rresid >= 32) {
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intctl |= SPI_INTCTL_RF_HALF_FU_INT_EN;
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} else {
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intctl |= SPI_INTCTL_RF_RDY_INT_EN;
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}
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}
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if (sc->sc_wchunk) {
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intctl |= SPI_INTCTL_TF_HALF_EMP_INT_EN;
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}
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SPIREG_WRITE(sc, SPI_INTCTL, intctl);
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}
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static void
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sun4ispi_start(struct sun4ispi_softc * const sc)
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{
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struct spi_transfer *st;
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uint32_t ctl;
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int s;
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struct spi_chunk *chunk;
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size_t burstcount;
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while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
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spi_transq_dequeue(&sc->sc_q);
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KASSERT(sc->sc_transfer == NULL);
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sc->sc_transfer = st;
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sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
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sc->sc_running = true;
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burstcount = 0;
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for (chunk = st->st_chunks; chunk; chunk = chunk->chunk_next) {
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burstcount += chunk->chunk_count;
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}
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KASSERT(burstcount <= SPI_BC_BC);
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SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_BC));
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SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_WTC));
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sun4ispi_rxtx(sc);
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sun4ispi_set_interrupt_mask(sc);
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KASSERT(st->st_slave < sc->sc_spi.sct_nslaves);
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ctl = sc->sc_CTL | __SHIFTIN(st->st_slave, SPI_CTL_SS) | SPI_CTL_XCH;
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SPIREG_WRITE(sc, SPI_CTL, ctl);
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if (!cold)
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return;
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s = splbio();
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for (;;) {
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(void) sun4ispi_intr(sc);
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if (ISSET(st->st_flags, SPI_F_DONE))
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break;
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}
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splx(s);
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}
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sc->sc_running = false;
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}
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static int
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sun4ispi_intr(void *cookie)
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{
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struct sun4ispi_softc * const sc = cookie;
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struct spi_transfer *st;
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uint32_t isr;
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isr = SPIREG_READ(sc, SPI_INT_STA);
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if (!isr)
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return 0;
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if (ISSET(isr, SPI_INT_STA_RO)) {
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device_printf(sc->sc_dev, "RXFIFO overflow\n");
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}
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if (ISSET(isr, SPI_INT_STA_TU)) {
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device_printf(sc->sc_dev, "TXFIFO underrun\n");
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}
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sun4ispi_rxtx(sc);
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if (ISSET(isr, SPI_INT_STA_TC)) {
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SPIREG_WRITE(sc, SPI_INTCTL, 0);
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KASSERT(sc->sc_rchunk == NULL);
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KASSERT(sc->sc_wchunk == NULL);
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st = sc->sc_transfer;
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sc->sc_transfer = NULL;
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KASSERT(st != NULL);
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spi_done(st, 0);
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sc->sc_running = false;
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} else {
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sun4ispi_set_interrupt_mask(sc);
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}
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SPIREG_WRITE(sc, SPI_INT_STA, isr);
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return 1;
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}
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127
sys/arch/arm/sunxi/sun4i_spireg.h
Normal file
127
sys/arch/arm/sunxi/sun4i_spireg.h
Normal file
@ -0,0 +1,127 @@
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/* $NetBSD: sun4i_spireg.h,v 1.1 2019/08/03 13:28:42 tnn Exp $ */
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/*
|
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* Copyright (c) 2019 Tobias Nygren
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SUNXI_SUN4I_SPIREG_H_
|
||||
#define _SUNXI_SUN4I_SPIREG_H_
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
#define SPI_RXDATA 0x00
|
||||
|
||||
#define SPI_TXDATA 0x04
|
||||
|
||||
#define SPI_CTL 0x08
|
||||
#define SPI_CTL_SDM __BIT(20)
|
||||
#define SPI_CTL_SDC __BIT(19)
|
||||
#define SPI_CTL_TP_EN __BIT(18)
|
||||
#define SPI_CTL_SS_LEVEL __BIT(17)
|
||||
#define SPI_CTL_SS_CTRL __BIT(16)
|
||||
#define SPI_CTL_DHB __BIT(15)
|
||||
#define SPI_CTL_DDB __BIT(14)
|
||||
#define SPI_CTL_SS __BITS(13, 12)
|
||||
#define SPI_CTL_RPSM __BIT(11)
|
||||
#define SPI_CTL_XCH __BIT(10)
|
||||
#define SPI_CTL_RF_RST __BIT(9)
|
||||
#define SPI_CTL_TF_RST __BIT(8)
|
||||
#define SPI_CTL_SSCTL __BIT(7)
|
||||
#define SPI_CTL_LMTF __BIT(6)
|
||||
#define SPI_CTL_DMAMC __BIT(5)
|
||||
#define SPI_CTL_SSPOL __BIT(4)
|
||||
#define SPI_CTL_POL __BIT(3)
|
||||
#define SPI_CTL_PHA __BIT(2)
|
||||
#define SPI_CTL_MODE __BIT(1)
|
||||
#define SPI_CTL_EN __BIT(0)
|
||||
|
||||
#define SPI_INTCTL 0x0c
|
||||
#define SPI_INTCTL_SS_INT_EN __BIT(17)
|
||||
#define SPI_INTCTL_TX_INT_EN __BIT(16)
|
||||
#define SPI_INTCTL_TF_UR_INT_EN __BIT(14)
|
||||
#define SPI_INTCTL_TF_OF_INT_EN __BIT(13)
|
||||
#define SPI_INTCTL_TF_E34_INT_EN __BIT(12)
|
||||
#define SPI_INTCTL_TF_E14_INT_EN __BIT(11)
|
||||
#define SPI_INTCTL_TF_FL_INT_EN __BIT(10)
|
||||
#define SPI_INTCTL_TF_HALF_EMP_INT_EN __BIT(9)
|
||||
#define SPI_INTCTL_TF_EMP_INT_EN __BIT(8)
|
||||
#define SPI_INTCTL_RF_UR_INT_EN __BIT(6)
|
||||
#define SPI_INTCTL_RF_OF_INT_EN __BIT(5)
|
||||
#define SPI_INTCTL_RF_F34_INT_EN __BIT(4)
|
||||
#define SPI_INTCTL_RF_F14_INT_EN __BIT(3)
|
||||
#define SPI_INTCTL_RF_FU_INT_EN __BIT(2)
|
||||
#define SPI_INTCTL_RF_HALF_FU_INT_EN __BIT(1)
|
||||
#define SPI_INTCTL_RF_RDY_INT_EN __BIT(0)
|
||||
|
||||
#define SPI_INT_STA 0x10
|
||||
#define SPI_INT_STA_INT_CBF __BIT(31)
|
||||
#define SPI_INT_STA_SSI __BIT(17)
|
||||
#define SPI_INT_STA_TC __BIT(16)
|
||||
#define SPI_INT_STA_TU __BIT(14)
|
||||
#define SPI_INT_STA_TO __BIT(13)
|
||||
#define SPI_INT_STA_TE34 __BIT(12)
|
||||
#define SPI_INT_STA_TE14 __BIT(11)
|
||||
#define SPI_INT_STA_TF __BIT(10)
|
||||
#define SPI_INT_STA_THE __BIT(9)
|
||||
#define SPI_INT_STA_TE __BIT(8)
|
||||
#define SPI_INT_STA_RU __BIT(6)
|
||||
#define SPI_INT_STA_RO __BIT(5)
|
||||
#define SPI_INT_STA_RF34 __BIT(4)
|
||||
#define SPI_INT_STA_RF14 __BIT(3)
|
||||
#define SPI_INT_STA_RF __BIT(2)
|
||||
#define SPI_INT_STA_RHF __BIT(1)
|
||||
#define SPI_INT_STA_RR __BIT(0)
|
||||
|
||||
#define SPI_DMACTL 0x14
|
||||
#define SPI_DMACTL_TF_EMP34_DMA __BIT(12)
|
||||
#define SPI_DMACTL_TF_EMP14_DMA __BIT(11)
|
||||
#define SPI_DMACTL_TF_NF_DMA __BIT(10)
|
||||
#define SPI_DMACTL_TF_HE_DMA __BIT(9)
|
||||
#define SPI_DMACTL_TF_EMP_DMA __BIT(8)
|
||||
#define SPI_DMACTL_RF_FU34_DMA __BIT(4)
|
||||
#define SPI_DMACTL_RF_FU14_DMA __BIT(3)
|
||||
#define SPI_DMACTL_RF_FU_DMA __BIT(2)
|
||||
#define SPI_DMACTL_RF_HF_DMA __BIT(1)
|
||||
#define SPI_DMACTL_RF_RDY_DMA __BIT(0)
|
||||
|
||||
#define SPI_WAIT 0x18
|
||||
#define SPI_WAIT_WCC __BITS(15, 0)
|
||||
|
||||
#define SPI_CCTL 0x1c
|
||||
#define SPI_CCTL_DRS __BIT(12)
|
||||
#define SPI_CCTL_CDR1 __BITS(11, 8)
|
||||
#define SPI_CCTL_CDR2 __BITS(7, 0)
|
||||
|
||||
#define SPI_BC 0x20
|
||||
#define SPI_BC_BC __BITS(23, 0)
|
||||
|
||||
#define SPI_TC 0x24
|
||||
#define SPI_TC_WTC __BITS(23, 0)
|
||||
|
||||
#define SPI_FIFO_STA 0x28
|
||||
#define SPI_FIFO_STA_TF_CNT __BITS(22, 16)
|
||||
#define SPI_FIFO_STA_RF_CNT __BITS(6, 0)
|
||||
|
||||
#endif /* _SUNXI_SUN4I_SPIREG_H_ */
|
||||
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Reference in New Issue
Block a user